WO1999045590A1 - Flipchip assembly having rigid inner core bumps - Google Patents

Flipchip assembly having rigid inner core bumps Download PDF

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Publication number
WO1999045590A1
WO1999045590A1 PCT/US1998/027769 US9827769W WO9945590A1 WO 1999045590 A1 WO1999045590 A1 WO 1999045590A1 US 9827769 W US9827769 W US 9827769W WO 9945590 A1 WO9945590 A1 WO 9945590A1
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WIPO (PCT)
Prior art keywords
inner core
temperature
bump
outer layer
bumps
Prior art date
Application number
PCT/US1998/027769
Other languages
French (fr)
Inventor
Lillian Charell Thompson
Theodore G. Tessier
Li Li
Original Assignee
Motorola Inc.
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Filing date
Publication date
Application filed by Motorola Inc. filed Critical Motorola Inc.
Publication of WO1999045590A1 publication Critical patent/WO1999045590A1/en

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract

A two-layer bump (24) having an inner core (38) and an outer layer (40) encasing the inner core (38) are formed on an under bump metallization (28) of a semiconductor die (20). The bump (24) forms electrical contacts between the semiconductor die (20) and the substrate (22). The outer layer (40) can have a reflow temperature that is either less than or substantially equivalent to the reflow temperature of the inner core (38). The bumps (24) maintain a substantially uniform bump-height and standoff separation between the semiconductor die (20) and the substrate (22). An underfill material (26) fills the space of void surrounding the bumps (24) that are located between the semiconductor die (20) and the substrate (22).

Description

FLIPCHIP ASSEMBLY HAVING RIGID INNER CORE BUMPS
Background of the Invention
The present invention relates, in general, to electrical interconnects and, more particularly, to interconnect bumps.
In the semiconductor industry, electrical contact is made to a semiconductor die by forming an interconnect bump or raised metal contact on the surface of the semiconductor die in order to facilitate electrical contact to another surface, such as a printed circuit board or a package. In the past, the interconnect was accomplished by using a passivation layer, to mask out portions of a die on which the bump is not formed. The bumps are formed using a conductive paste which is screen printed on the semiconductor wafer. At a temperature slightly above the eutectic temperature of the conductive paste, the conductive paste forms spherically shaped bumps on the semiconductor wafer.
At temperatures above the reflow temperature of the solder bumps, the electrical interconnects between the semiconductor die and the other surface are formed. The solder bumps provide a standoff or separation distance between the semiconductor die and the other surface. The standoff distance is necessary for injecting an underfill material between the semiconductor die and the other surface. However, the height of the spherically shaped solder bumps can be diminished during the assembly process. The bumps change shape and the standoff distance is not maintained during the assembly process. By not maintaining the standoff distance, an undesired bridging of solder across contacts can occur and the underfill can not be injected to surround the electrical contacts. If the electrical contacts are not surrounded by underfill, reliability problems and defects can occur.
Accordingly, it would be advantageous to form electrical interconnects between the semiconductor die and another surface while maintaining a standoff distance. In addition, it would be advantageous to have a low cost packaging solution that provides uniform bump heights and reliable electrical interconnects. Brief Description of the Drawings
FIG. 1 illustrates a cross-sectional view of a flipchip assembly having a semiconductor die attached to a substrate using bumps;
FIG. 2 illustrates a cross-sectional view of a bump of FIG. 1 formed on an under-bump metallization on the surface of the semiconductor die; and FIG. 3 illustrates a cross-sectional view of another embodiment of a bump formed on the under-bump metallization on the surface of the semiconductor die.
Detailed Description of the Drawings
Generally, the present invention applies to the formation of electrical contacts or bumps on substrates such as semiconductor wafers, printed circuit boards, flex circuits, or metallized ceramic or glass substrates. In accordance with the present invention, a bump is formed having an inner core and an outer layer encasing the inner core. The outer layer can have a reflow temperature that is either less than or substantially equivalent to the reflow temperature of the inner core. Thus, the two-layer bumps maintain a substantially uniform bump-height and standoff separation between the two surfaces when an electrical contact between the two surfaces is formed.
FIG. 1 illustrates a cross-sectional view of a flipchip assembly 10 having a semiconductor die 20 for attaching to a substrate 22 using bumps 24. Flipchip assembly 10 is also referred to as an electrical assembly or a solder bump assembly. Semiconductor die 20 includes semiconductor devices such as transistors, diodes or integrated circuits (not shown). A metal interconnect pattern 30 provides electrically conductive paths for transferring electrical signals such as Input/Output (I/O) signals between transistors and an array of conductive bond pads, e.g., under-bump metallization 28, on semiconductor die 20. Metal interconnect pattern 30 is typically either a patterned aluminum or copper conductive layer. By way of example, under-bump metallization 28 comprises adhesion layer 32, barrier layer 34, and protective layer 36 (see FIG. 2), and is typically arranged in an M by N array, where M is the number or rows and N is the number of columns. An underfill material 26 fills the space or void surrounding bumps 24 that are located between semiconductor die 20 and substrate 22. Semiconductor die 20 is shown in highly simplified form for illustrative convenience. Although bumps 24 are illustrated showing semiconductor die 20 electrically connected with substrate 22, bumps 24 could have other uses. For instance, bumps 24 could be used in attaching modules to printed circuit boards, flex circuits to substrates, glass substrates to other glass substrates as in liquid crystal displays or flat panel displays. Bump 24 is a multi-layer bump having an inner core 38 and an outer layer 40 (see FIG. 2) encasing or enclosing inner core 38. The two-layer bump 24 is used to form electrical interconnects between opposing metallized surfaces while maintaining a substantially uniform bump-height and standoff distance between the surfaces. By way of example, bumps 24 provide electrical connectivity between two glass substrates of an optical display and the standoff distance allows a liquid crystal material to be injected between two glass substrates.
FIG. 2 illustrates a cross-sectional view of a bump 24A formed on under-bump metallization 28 on the surface of semiconductor die 20. The letter "A" is attached to the reference number 24 to show that bump 24A is one of the bumps from the group of bumps 24. It should be noted that the same reference numerals are used in the figures to denote the same elements. Under-bump metallization 28 is a multi-layer metallization system, wherein each layer is formed using sputter deposition techniques, an electroplating process, or vacuum evaporation techniques. It should be understood that the method of forming under-bump metallization 28 is not a limitation of the present invention.
In accordance with one embodiment of the present invention, under-bump metallization 28 is comprised of three layers of metal at each conductive bond pad site in the M by N array. The first metal layer is an adhesion layer 32 formed over a portion of metal interconnect pattern 30. Suitable materials for adhesion layer 32 include metals such as titanium or chromium. Adhesion layer 32 promotes adhesion between metal interconnect pattern 30 on semiconductor die 20 and subsequently formed metal layers as described hereinafter. It should be noted that the coefficient of thermal expansion of adhesion layer 32 matches those of subsequently formed metal layers, thus ensuring a quality mechanical and chemical bond at elevated temperatures. The second metal layer is a barrier layer 34 that is formed on adhesion layer 32. Barrier layer 34 provides protection against solder components diffusing inward toward a surface of semiconductor die 20. By way of example, barrier layer 34 is a copper layer. Other suitable compositions for barrier layer 34 include nickel or a nickel alloy such as nickel-niobium (NiNb), nickel-tantalum (NiTa), nickel-sulfur (NiS), nickel-antimony (NiSb), nickel-scandium (NiSc), nickel-samarium (NiSm), nickel- tin (NiSn), nickel-magnesium (NiMg), and nickel-yttrium (NiY).
The third metal layer is a protective layer 36 that is formed on barrier layer 34. Suitable materials for protective layer 36 include gold and gold alloys. Protective layer 36 is solder wetable and prevents barrier layer 34 from becoming oxidized. The gold in protective layer 36 dissolves into an inner core 38 during the high temperatures that occur during a solder re-flow process.
In accordance with another embodiment of the present invention, under-bump metallization 28 is comprised of two layers of metal at each conductive bond pad site in the M by N array. The first metal layer includes metals such as nickel that are formed or sputter deposited over a portion of metal interconnect pattern 30. The second metal layer includes metals such as gold that are formed or sputter deposited over the first metal layer. It should be understood that the number of layers, the shape, and the composition of metals in under-bump metallization 28 are not a limitation of the present invention. In forming inner core 38, a metal stencil or screen (not shown) has holes that are larger than openings or vias 42 that are positioned over selected portions of under-bump metallization 28. Alternatively, a radiation-active film or photoresist layer (not shown) defines a larger area above openings 42 that is deposited with a conductive paste (not shown) to overlie a portion of under- bump metallization 28. The holes in the photoresist layer that correspond to openings 42 are formed by standard patterning processes used in photolithography.
A conductive paste (not shown) such as solder paste or lead paste is applied to a wafer having semiconductor die 20 and under-bump metallization 28. Preferably, the conductive paste is dispensed or spread on the surface of a screen in order to roughly cover the screen and fill the corresponding hole defined in the screen above openings 42. A squeegee or other suitable instrument is used to sweep the conductive paste across the screen and thereby force the conductive paste into openings 42. Typically, the wafer having semiconductor die 20 is placed on a belt moving through a reflow oven and subjected to a temperature that is slightly higher than the reflow temperature of the conductive paste. The reflow process re-forms the rectangular shaped conductive paste contained in the patterned area above opening 42 into a spherically shaped inner core 38 that is attached to under-bump metallization 28. The attachment of inner core 38 to under-bump metallization 28 occurs along the entire exposed surface of under-bump metallization 28. Thus, the conductive paste is re-shaped during the reflow process into inner core 38 having a dome or spherical structure extending from the surface of under-bump metallization 28.
The first conductive paste has a reflow temperature typically between a range of about 140 and 350 degrees Celsius (°C). Examples of suitable conductive pastes include Sn/Pb (tin/lead) that is about 5% tin and about 95% lead, or alloys composed of silver, zinc, antimony, or the like. It should be noted that the shape of inner core 38 is not a limitation of the present invention.
Following the formation of inner core 38, an outer layer 40 is formed to complete bump 24A. A photoresist layer, a metal stencil, or a screen is used to define an area above openings 42A that are located over inner core 38. The letter A is attached to the reference number 42 to indicate that opening 42A may or may not have the same dimensions as opening 42. Preferably, a second conductive paste is dispensed or spread on the surface of the screen in order to roughly fill corresponding holes that are patterned in the screen above openings 42A. A squeegee or other suitable instrument is again used to sweep the second conductive paste across the screen and thereby force the second conductive paste into openings 42A. Typically, semiconductor die 20 is placed on a belt moving through a reflow oven and subjected to a temperature in the reflow oven that is the same or slightly higher than the reflow temperature of the second conductive paste. The second conductive paste has a reflow temperature that is typically less or equivalent to the reflow temperature of inner core 38. Reflowing the second conductive paste forms an outer layer 40 that encases or encloses inner core 38 of bump 24A. In other words, outer layer 40 covers or surrounds the exposed surface of inner core 38. Thus, outer layer 40 wraps around the portion of inner core 38 that is not attached to under bump metallization 28. It should be noted that the shape of bump 24A is not a limitation of the present invention. It should be further noted that the first conductive paste used to form inner core 38 and the second conductive paste used to form outer layer 40 could be the same material and form a homogeneous bump.
Examples of suitable second conductive pastes include Sn/Pb (tin/lead) that is about 63% tin and about 37% lead, or alloys composed of silver, zinc, antimony, or the like. Outer layer 40 is a solder composition such as (Sb)/5% tin (Sn), or 80% lead (Pb)/10% tin (Sn)/10% antimony (Sb), or 62% tin (Sn)/36% lead (Pb)/2% silver (Ag). The first conductive paste has a reflow temperature typically between a range of about 140 and 300 degrees Celsius (°C). It should be noted that bumps 24 could be formed by conductive materials other than lead solders. By way of example, bumps 24 could be formed having an inner core and an outer layer, wherein both the inner core and outer layer are a conductive epoxy material. The inner core and outer layer would have different epoxy curing temperatures or degrees of cure. FIG. 3 illustrates a cross-sectional view of another embodiment of a bump 24B formed on under-bump metallization 28 on the surface of semiconductor die 20. The letter "B" is attached to the reference number 24 to show that bump 24B is one of a group of bumps 24 that has a flattened side. Under-bump metallization 28 is a multi-layer metallization system comprised of a first layer 34 and a second layer 36. Under-bump metallization 28 is formed over a portion of metal interconnect pattern 30. A first screen (not shown) is used to define an area above openings 42 over selected portions of under-bump metallization 28. An application of a first conductive paste followed by a solder reflow step is used to define inner core 38A. The conductive paste contained in the area above opening 42 is re-shaped during a reflow process into inner core 38A having a dome or spherical structure as described hereinbefore. A second screen (not shown) is used to define an area above openings 42 that overlie inner core 38. A second conductive paste is applied to fill the area above openings 42 in the second screen. Reflowing the second conductive paste forms an outer layer 40A that encases inner core 38A of bump 24B. It should be noted that inner core 38A and outer layer 40A have been flattened. Thus, the height of bump 24B has been reduced through a step referred to as "coining".
In operation, semiconductor die 20 of flipchip assembly 10 has a plurality of electrical contacts or bonding sites provided by metal interconnect pattern 30. Under-bump metallization 28 is configured in an M by N array and connected to corresponding bonding sites of interconnect pattern 30. A plurality of bumps 24 are coupled to the plurality of electrical contacts. Bump 24 has an inner core 38 made of a first alloy that reflows at a first temperature. Bump 24 also has an outer layer 40 enclosing the inner core 38. The outer layer 40 is a second alloy that reflows at a second temperature that typically is less than the first temperature.
The two-layer bump 24, i.e., inner core 38 and outer layer 40, allow semiconductor die 20 to be attached to substrate 22 while maintaining a standoff distance between semiconductor die 20 and substrate 22. During the assembly process, a temperature equal to the reflow temperature of outer layer 40 but less than or equal to the reflow temperature of inner core 38 is supplied to flipchip assembly 10 causing outer layer 40 to form a metallurgical bond and be joined to substrate 22. Inner core 38 substantially retains its form during the assembly process while the metallurgical bond is formed between outer layer 40 and substrate 22. Inner core 38 having a higher reflow temperature than the reflow temperature of outer layer 40 allows a rigid inner core to maintain the standoff or separation distance between semiconductor die 20 and substrate 22. In other words, the height of inner core 38 remains substantially unchanged during the assembly process. Thus, bump 24 is a non-homogenous bump formed by inner core 38 and outer layer 40 that provides both an electrical contact and the standoff distance. An underfill material is injected between semiconductor die 20 and substrate 22.
By now it should be appreciated that a multi-layer bump formed on a semiconductor die maintains a standoff separation of the die to a printed circuit board during assembly. By maintaining the standoff separation, an underfill material can reliably be injected between the semiconductor die and printed circuit board. The multi-layer bumps formed by the present invention are particularly advantageous for providing a tall bump and a tight pitch in providing a low cost and low profile packaging solution. In addition, the present invention applies to the formation of electrical contacts or bumps on substrates such as printed circuit boards, flex circuits, or metallized ceramic or glass substrates. In particular, a multi-layer bump having an inner core and an outer layer encasing the inner core maintain a substantially uniform bump-height and standoff separation that could be used to form electrical interconnect for displays.

Claims

1 . A flipchip assembly (10), comprising: a die (20) having a plurality of electrical contacts (30); and a plurality of bumps (24) respectively coupled to the plurality of electrical contacts, where one of the plurality of bumps includes,
(a) an inner core (38) comprising a first alloy that reflows at a first temperature, and (b) an outer layer (40) enclosing the inner core (38) and comprising a second alloy that reflows at a second temperature less than the first temperature.
2. The flipchip assembly (10) of claim 1 , wherein the first alloy is about 5 percent tin and about 95 percent lead.
3. An electrical assembly having a metallization pattern coupled to an electrical contact, comprising: a rigid inner core (38) coupled to the electrical contact where the rigid inner core (38) substantially maintains its form at a temperature less than a first temperature; and an outer layer (40) enclosing the rigid inner core (38) and comprising an alloy that reflows at a second temperature that is substantially the same as the first temperature.
4. A solder bump assembly, comprising: a die (20) having an electrical contact (30); and a bump (24) coupled to the electrical contact (30), where the bump (24) includes, (a) an inner core (38) formed with a solder paste comprising a first alloy having a first reflow temperature, and
(b) an outer layer (40) encasing the inner core (38) and comprising a second alloy having a second reflow temperature.
5. The solder bump assembly of claim 4, wherein the second reflow temperature is less than the first reflow temperature.
6. The solder bump assembly of claim 4, wherein the second reflow temperature is substantially the same as the first reflow temperature.
7. A method of forming a flipchip assembly, comprising the steps of: providing a die (20) having a plurality of electrical contacts (30); and forming a plurality of bumps (24) respectively coupled to the plurality of electrical contacts (30), where one of the plurality of bumps (24) is formed by,
(a) reflowing a first alloy at a first temperature to form an inner core (38), and
(b) reflowing a second alloy at a second temperature less than the first temperature to form an outer layer (40) enclosing the inner core (38).
8. A method of joining a substrate (22) to an electrical assembly having a metallization pattern terminating in an electrical contact (30), comprising the steps of: providing a bump (24) having a rigid inner core (38) and an outer layer (40) enclosing the rigid inner core (38), where the bump (24) is coupled to the electrical contact (30); maintaining a form of the rigid inner core (38) at a temperature less than a first temperature; and joining the outer layer (40) to the substrate (22) at a second temperature less than the first temperature.
9. The method of claim 8, wherein the rigid inner core (38) and the outer layer (40) further include forming a non- homogenous bump.
10. The method of claim 8, wherein the rigid inner core (38) further includes maintaining a standoff separation distance between the substrate (22) and the electrical assembly.
10
PCT/US1998/027769 1998-03-02 1998-12-29 Flipchip assembly having rigid inner core bumps WO1999045590A1 (en)

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US09/033,938 1998-03-02

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
WO2002003461A3 (en) * 2000-06-30 2003-05-30 Intel Corp Ball limiting metallurgy for input/outputs and methods of fabrication
EP2075834A1 (en) * 2007-12-28 2009-07-01 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) Solder bumps for flip chip bonding with higher density

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JPS57106057A (en) * 1980-12-23 1982-07-01 Citizen Watch Co Ltd Bump structure of ic
JPS5958843A (en) * 1982-09-28 1984-04-04 Sharp Corp Manufacture of bump for flip chip
US5466635A (en) * 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
EP0747954A2 (en) * 1995-06-07 1996-12-11 International Business Machines Corporation Reflowed solder ball with low melting point metal cap

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002003461A3 (en) * 2000-06-30 2003-05-30 Intel Corp Ball limiting metallurgy for input/outputs and methods of fabrication
EP2075834A1 (en) * 2007-12-28 2009-07-01 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) Solder bumps for flip chip bonding with higher density

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