WO1999050890A1 - Method for making multilayer thin-film electronics - Google Patents

Method for making multilayer thin-film electronics Download PDF

Info

Publication number
WO1999050890A1
WO1999050890A1 PCT/US1999/006453 US9906453W WO9950890A1 WO 1999050890 A1 WO1999050890 A1 WO 1999050890A1 US 9906453 W US9906453 W US 9906453W WO 9950890 A1 WO9950890 A1 WO 9950890A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrates
thin film
conductor
light emitting
organic light
Prior art date
Application number
PCT/US1999/006453
Other languages
French (fr)
Inventor
Sigurd Wagner
Original Assignee
Trustees Of Princeton University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Trustees Of Princeton University filed Critical Trustees Of Princeton University
Priority to AU32030/99A priority Critical patent/AU3203099A/en
Priority to US09/647,193 priority patent/US6893896B1/en
Publication of WO1999050890A1 publication Critical patent/WO1999050890A1/en
Priority to US10/945,610 priority patent/US7115983B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H01L21/02288—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating printing, e.g. ink-jet printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to large-area electronics and to methods for manufacturing thin film electronics continuously on separate carrier substrate foils, and then to combining these foils using anisotropic electrical conductors or light guides.
  • the present invention maintains high-speed manufacturing while the various component functions are manufactured separately under conditions tailored to optimize component performance and yield.
  • the method involves the production of each function or group of functions on a separate flexible substrate, and bonding these flexible substrates to each other by using anisotropic electrically conducting or optical lightguide adhesives. The bonding is performed by laminating the flexible substrates to each other via the adhesive in a continuous process.
  • Anisotropic conductors conduct in one direction (i.e. top to bottom) but do not conduct sideways. 3
  • FIG. 1 is a schematic drawing of a pixel for a display of organic light emitting diodes driven by an active matrix of thin film transistors made on a steel back plane.
  • FIG. 2 is a diagram of a co-laminated thin film transistor using anisotropic electrically conducting adhesive.
  • An active-matrix liquid-crystal display is an example of such a product. It consists of a light source, a plane of transistor electronics, a layer of liquid crystal sandwiched between transparent conductors and polarizers, and a plane of color filters.
  • Such products are made by separately manufacturing the individual components, such as the light source, the transistor back plane, and the color filter plane, followed by assembly and filling of the liquid crystal material.
  • the separate manufacture allows the individual optimization of the performance of each component.
  • separate manufacture is necessary to obtain the desired functionality.
  • the transistor back plane of a liquid crystal display could not be manufactured after assembly, because assembly renders the required substrate surface inaccessible.
  • integration of several functions on one substrate leads to savings in cost, improvement of yield, and increased functionality.
  • Macroelectronic products are expected to have very low cost per unit area, rather than per function as is the case for conventional microelectronics. This requirement is apparent for typical examples of future macroelectronic products, such as disposable, intelligent shipping/shopping labels, digital wallpaper, and dial-your-pattern dresses. These products may include transistor electronics, input/output devices such as antennae, optoelectronic functions including photodetectors and light-emitting diodes, and microelectromechanical devices.
  • FIG. 1 shows a pixel for a display of organic light emitting diodes driven by an active matrix of thin film transistors made on a steel back plane. In such devices, thin film transistors must make good electrical contact to the OLEDs to provide sufficient drive current.
  • This is an active matrix emissive display which consists of a back plane of thin film transistors that drive organic light emitting diodes. Such a pixel is shown in the paper by Wu. et al. Integration of
  • the display shown in FIG. 1 is manufactured in a sequence of steps that adds the TFT and OLED layers to one substrate.
  • a substrate foil for example, stainless steel, has patterned TFT circuits added first.
  • the OLED circuits are then placed on the substrate.
  • a transparent encapsulation layer (not shown) is then applied.
  • the top contact to the OLED layer must be transparent to transmit the light, which is emitted from the organic semiconductor. In this structure this contact is made in one of the last processing steps.
  • the present invention addresses this problem by making the TFT back plane and the OLEDs separately, and connecting them electrically with an anisotropic conductor, which conducts only in the direction perpendicular to the layers.
  • This sequence of steps is illustrated in FIG. 2. More particularly, the OLED's 6 are formed on a transparent conductor 4 which is, in turn formed onto a transparent substrate/encapsulation 2.
  • the back plane comprises thin film transistors (TFT's) formed onto structural substrate 10. When the substrate 10 is conducted as is the case for metal foils, an insulated barrier layer 12 must be deposited between the TFT layer and the substrate.
  • the front plane OLED's and the back plane TFT's are connected together with an anistropic conductive adhesive 8. The resultant structure is the finished thin film display.
  • the OLEDs are made on a transparent conductor, which in turn is deposited on a transparent substrate. In this way, the best possible electrical contact to the OLEDs is made, and the transparent substrate ultimately serves as the transparent encapsulant.
  • the other electrical contact to the OLEDs may be opaque and is made of a suitable metal.
  • the two planes, TFT and OLED are then laminated to each other, using an adhesive foil of anisotropic conductor (for example, ARclad® 8257 from Adhesives Research, Inc., a 1-mil thick acrylic product).
  • the final assembly step therefore is the co- lamination of TFT foil, anisotropic conductor foil, and OLED foil. It is important to note that the proper TFT-OLED connections are made automatically by this procedure, as long as the TFT and OLED planes are 7 aligned with each other.
  • the same principle can be used to co-laminate component planes with anisotropic light guides, if optical interconnects are desired.
  • the lamination step may be repeated to combine more than two active planes in one product.
  • Having a body of easily deformable adhesive also provides another advantage in production yield and product lift.
  • the anisotropic conductor will accommodate mechanical strain between the circuit planes that it connects. If a rigid connection were used, any strain developing during fabrication or in produce use will be accommodated by the layer with the lowest elastic modulus. This may be an active layer, for example, the organic light-emitter. Straining this layer may destroy the OLED. Straining the adhesive layer will only lead to local shifts in the contact alignment, which will be self-correcting due to the anisotropic conduction or light guiding.
  • Anisotropic conductors are used today to make connections between groups of passive conductors on to different planes.
  • One well-known application is the surface-mount of integrated driver circuits to the row and column conductors of liquid crystal displays.
  • the use of a sheet of an anisotropically conducting adhesive for the direct connection of two active circuit planes is new. The problem solved here is coming into being only now, as macroelectronic integrated circuits are developed.

Abstract

Multilayer thin-film electronics are manufactured at high speed, even while the various component functions are manufactured separately under conditions tailored to optimize component performance and yield. Each function or group of functions is fabricated on a separate flexible substrate. These flexible substrates are bonded to each other using adhesive films that are anisotropic electrical conductors or optical light guides. The bonding is performed by laminating the flexible substrates to each other in a continuous process, using the anisotropic conductor as the bonding layer.

Description

METHOD FOR MAKING MULTILAYER THIN-FILM ELECTRONICS
SPECIFICATION BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
This invention relates to large-area electronics and to methods for manufacturing thin film electronics continuously on separate carrier substrate foils, and then to combining these foils using anisotropic electrical conductors or light guides.
RELATED ART
In the field of thin film electronics where two or more layers of active circuits are employed, many technologies exist for connection of separate planes of passive circuits. One of these technologies is multilevel metallization on top of integrated silicon circuits, for which several levels of metal lines are built up by alternating between the fabrication of metal patterns, the deposition of insulators, the opening of vertical connections, followed by the fabrication of the next level of metal pattern, etc. Another of these technologies is multilevel printed wire boards (PWBs), for which passive metal connections are deposited on epoxy-based or ceramic boards that are fabricated with openings to make vertical connections. Individual boards are bonded to each other to form multilevel PWBs by bonding techniques that depend on the material of the board. These techniques are used industrially. However, there are drawbacks associated with these existing techniques. 2
OBJECTS AND SUMMARY OF THE INVENTION It is an object of this invention to provide a method of manufacturing macroelectronic circuits.
It is a further object of this invention to provide a method of manufacturing macroelectronic circuits which results in low cost and high yield.
It is yet another object of this invention to provide a method for manufacturing electronic circuits in a continuous process.
It is still a further object of the invention to provide a method of manufacturing electronic circuits where thin film electronics are manufactured continuously on separate carrier substrate foils.
It is another object of the invention to provide a method of combining the separately manufactured foils.
It is a still further object of the invention to combine separately manufactured foils using adhesives and anisotropic electrical conductors or light guides.
The present invention maintains high-speed manufacturing while the various component functions are manufactured separately under conditions tailored to optimize component performance and yield. The method involves the production of each function or group of functions on a separate flexible substrate, and bonding these flexible substrates to each other by using anisotropic electrically conducting or optical lightguide adhesives. The bonding is performed by laminating the flexible substrates to each other via the adhesive in a continuous process. Anisotropic conductors conduct in one direction (i.e. top to bottom) but do not conduct sideways. 3
BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a schematic drawing of a pixel for a display of organic light emitting diodes driven by an active matrix of thin film transistors made on a steel back plane.
FIG. 2 is a diagram of a co-laminated thin film transistor using anisotropic electrically conducting adhesive.
4
DETAILED DESCRIPTION OF THE INVENTION Many electronic products combine several electronic and/or optical functions. An active-matrix liquid-crystal display is an example of such a product. It consists of a light source, a plane of transistor electronics, a layer of liquid crystal sandwiched between transparent conductors and polarizers, and a plane of color filters. Typically, such products are made by separately manufacturing the individual components, such as the light source, the transistor back plane, and the color filter plane, followed by assembly and filling of the liquid crystal material. The separate manufacture allows the individual optimization of the performance of each component. Often, separate manufacture is necessary to obtain the desired functionality. For example, the transistor back plane of a liquid crystal display could not be manufactured after assembly, because assembly renders the required substrate surface inaccessible. However, it is well known that integration of several functions on one substrate leads to savings in cost, improvement of yield, and increased functionality.
The need for combining several electronic functions at low cost with high yield becomes paramount in the field of macroelectronics, also called large- area electronics or giant electronics. Macroelectronic products are expected to have very low cost per unit area, rather than per function as is the case for conventional microelectronics. This requirement is apparent for typical examples of future macroelectronic products, such as disposable, intelligent shipping/shopping labels, digital wallpaper, and dial-your-pattern dresses. These products may include transistor electronics, input/output devices such as antennae, optoelectronic functions including photodetectors and light-emitting diodes, and microelectromechanical devices.
To keep costs low and achieve high yield, the manufacture of macroelectronic products must combine high-speed production of these functions with their integration at high yield. High-speed production can be achieved by the printing of macroelectronics on flexible substrates. The substrate will spool off a roll, run through equipment that is configured like a multi-color printing press, and then will be coiled up or cut into product. The diversity of 5 macroelectronic component functions (transistors, LEDs, photodetectors, etc.) requires diverse materials and manufacturing processes. Superposing these materials and processes in a fully integrated sequence reduces yield because the temperature and chemicals required for producing a given function may damage a function that was introduced earlier in a lower layer of the multilayer structure.
The present invention maintains high-speed manufacturing while the various component functions are manufactured separately under conditions tailored to optimize component performance and yield. The basic concept is to produce each function or group of functions on a separate flexible substrate, and to bond these flexible substrates to each other by using anisotropic electrically conducting or optical lightguide adhesives. The bonding is performed by laminating the flexible substrates to each other via the adhesive in a continuous process. FIG. 1 shows a pixel for a display of organic light emitting diodes driven by an active matrix of thin film transistors made on a steel back plane. In such devices, thin film transistors must make good electrical contact to the OLEDs to provide sufficient drive current. This is an active matrix emissive display which consists of a back plane of thin film transistors that drive organic light emitting diodes. Such a pixel is shown in the paper by Wu. et al. Integration of
Organic LEDs and Amorphous TFTs onto Unbreakable Metal Foil Substrates, published in the Tech. Digest Internat. Electron Devices Meeting, San Francisco, CA, December 8011, 1996, IEEE, Piscataway, NJ 1996, Paper 308.1, pp. 957- 959. The display shown in FIG. 1 is manufactured in a sequence of steps that adds the TFT and OLED layers to one substrate. A substrate foil, for example, stainless steel, has patterned TFT circuits added first. The OLED circuits are then placed on the substrate. A transparent encapsulation layer (not shown) is then applied. The top contact to the OLED layer must be transparent to transmit the light, which is emitted from the organic semiconductor. In this structure this contact is made in one of the last processing steps. It was found experimentally 6 that this transparent contact to the OLED functions best when made first, i.e., when the OLED is made on top of it ("Organic LEDs integrated with a-Si TFTs on lightweight metal substrates", C.C. Wu, et al., Society for Information Display, Internat. Symp. Digest, Vol. XXVIII, SID, Santa Ana, CA 1997, pp. 67-70). However, making the OLEDs first on a transparent substrate, followed by making the TFTs on top of the OLEDs is not possible, because the typical TFT process temperature of 200° to 350° C will destroy the OLED, which must not be heated much above room temperature.
The present invention addresses this problem by making the TFT back plane and the OLEDs separately, and connecting them electrically with an anisotropic conductor, which conducts only in the direction perpendicular to the layers. This sequence of steps is illustrated in FIG. 2. More particularly, the OLED's 6 are formed on a transparent conductor 4 which is, in turn formed onto a transparent substrate/encapsulation 2. The back plane comprises thin film transistors (TFT's) formed onto structural substrate 10. When the substrate 10 is conducted as is the case for metal foils, an insulated barrier layer 12 must be deposited between the TFT layer and the substrate. The front plane OLED's and the back plane TFT's are connected together with an anistropic conductive adhesive 8. The resultant structure is the finished thin film display. Nothing is changed in TFT manufacture as compared to the sequence described above. However, the OLEDs are made on a transparent conductor, which in turn is deposited on a transparent substrate. In this way, the best possible electrical contact to the OLEDs is made, and the transparent substrate ultimately serves as the transparent encapsulant. The other electrical contact to the OLEDs may be opaque and is made of a suitable metal. The two planes, TFT and OLED, are then laminated to each other, using an adhesive foil of anisotropic conductor (for example, ARclad® 8257 from Adhesives Research, Inc., a 1-mil thick acrylic product). The final assembly step therefore is the co- lamination of TFT foil, anisotropic conductor foil, and OLED foil. It is important to note that the proper TFT-OLED connections are made automatically by this procedure, as long as the TFT and OLED planes are 7 aligned with each other.
The same principle can be used to co-laminate component planes with anisotropic light guides, if optical interconnects are desired. The lamination step may be repeated to combine more than two active planes in one product. Having a body of easily deformable adhesive also provides another advantage in production yield and product lift. The anisotropic conductor will accommodate mechanical strain between the circuit planes that it connects. If a rigid connection were used, any strain developing during fabrication or in produce use will be accommodated by the layer with the lowest elastic modulus. This may be an active layer, for example, the organic light-emitter. Straining this layer may destroy the OLED. Straining the adhesive layer will only lead to local shifts in the contact alignment, which will be self-correcting due to the anisotropic conduction or light guiding.
Anisotropic conductors are used today to make connections between groups of passive conductors on to different planes. One well-known application is the surface-mount of integrated driver circuits to the row and column conductors of liquid crystal displays. The use of a sheet of an anisotropically conducting adhesive for the direct connection of two active circuit planes is new. The problem solved here is coming into being only now, as macroelectronic integrated circuits are developed.
While several advantageous embodiments have been chosen to illustrate the invention, it will be understood by those skilled in the art that various changes and modifications can be made therein without departing from the scope of the invention as defined in the appended claims. Having thus described the invention in detail, it is to be understood that the foregoing description is not intended to limit the spirit and scope thereof. What is desired to be protected by Letters Patent is set forth in the appended claims.

Claims

8CLAIMS What is claimed is:
1. A process for manufacturing macroelectronics comprising the steps of: producing thin film active electronics on separate carrier substrates; and combining said substrates using anisotropic electrical conductors or light guides.
2. The process of claim 1 wherein one of said substrates is a flexible foil.
3. The process of claim 1 wherein one of said substrates is a rigid plate.
4. The process of claim 2 wherein the material for one of said substrates is plastic.
5. The process of claim 3 wherein the material for one of said substrates is plastic.
6. The process of claim 2 wherein the material for one of said substrates is glass.
7. The process of claim 3 wherein the material for one of said substrates is glass.
8. The process of claim 2 wherein the material for one of said substrates is metal.
9. The process of claim 3 wherein the material for one of said substrates is metal.
10. The process of claim 1 wherein the thin film active electronics are producted continuously on seperate carrier substrates.
11. The process of claim 4 wherein organic light emitting diodes are formed on the plastic substrate.
12. The process of claim 5 wherein organic light emitting diodes are formed on the plastic substrate.
13. The process of claim 6 wherein organic light emitting diodes are formed on the glass substrate.
14. The process of claim 7 wherein organic light emitting diodes are formed on the glass substrate. 9
15. The process of claim 6 wherein thin film transistors are formed on the glass substrate.
16. The process of claim 7 wherein thin film transitors are formed on the glass substrate.
17. A process of making electronic circuits comprising the steps of: forming at least two active circuits on separate carrier substrates; and combining said active circuits by connecting them with a material which conducts in only a single direction.
18. A method of manufacturing an electronic display comprising the steps of: depositing a transparent conductor on a transparent substrate; forming a thin film organic light emitting diode circuit on said transparent conductor; forming a thin film transistor circuit; and laminating said circuits to each other.
19. The method of claim 18 wherein said laminating step uses an adhesive anisotropic conductor.
20. The method of claim 19 wherein the conductor is an electrical or optical conductor.
21. The method of claim 19 wherein the bonding layer is the conductor.
22. A method of manufacturing an electronic circuit comprising the steps of: forming a first active circuit on a first plane; forming a second active circuit on a second plane; and co-laminating said first and second planes with an anisotropic conductor in between.
PCT/US1999/006453 1998-03-27 1999-03-26 Method for making multilayer thin-film electronics WO1999050890A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU32030/99A AU3203099A (en) 1998-03-27 1999-03-26 Method for making multilayer thin-film electronics
US09/647,193 US6893896B1 (en) 1998-03-27 1999-03-26 Method for making multilayer thin-film electronics
US10/945,610 US7115983B2 (en) 1998-03-27 2004-09-21 Multilayer, thin-film electronic devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7974698P 1998-03-27 1998-03-27
US60/079,746 1998-03-27

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US09647193 A-371-Of-International 1999-03-26
US10/945,610 Division US7115983B2 (en) 1998-03-27 2004-09-21 Multilayer, thin-film electronic devices

Publications (1)

Publication Number Publication Date
WO1999050890A1 true WO1999050890A1 (en) 1999-10-07

Family

ID=22152544

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US1999/006453 WO1999050890A1 (en) 1998-03-27 1999-03-26 Method for making multilayer thin-film electronics
PCT/US1999/006454 WO1999050889A2 (en) 1998-03-27 1999-03-26 Printed insulators for active and passive electronic devices

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/US1999/006454 WO1999050889A2 (en) 1998-03-27 1999-03-26 Printed insulators for active and passive electronic devices

Country Status (2)

Country Link
AU (2) AU3203199A (en)
WO (2) WO1999050890A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004068536A3 (en) * 2003-01-30 2005-01-20 Univ Cape Town A thin film semiconductor device and method of manufacturing a thin film semiconductor device
WO2006080839A2 (en) * 2005-01-25 2006-08-03 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Electronic device comprising an electronic component and encapsulation members
US7776724B2 (en) 2006-12-07 2010-08-17 Innovalight, Inc. Methods of filling a set of interstitial spaces of a nanoparticle thin film with a dielectric material
US7851336B2 (en) 2008-03-13 2010-12-14 Innovalight, Inc. Method of forming a passivated densified nanoparticle thin film on a substrate
US8247312B2 (en) 2008-04-24 2012-08-21 Innovalight, Inc. Methods for printing an ink on a textured wafer surface

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0105145D0 (en) 2001-03-02 2001-04-18 Koninkl Philips Electronics Nv Thin film transistors and method of manufacture
DE10151131A1 (en) * 2001-10-17 2003-05-08 Infineon Technologies Ag Production of a structured layer on a surface of a substrate comprises forming a mask made from fixed toner on the surface of the substrate using a laser printing process, and forming the structured layer with a structure defined by a mask
GB2388709A (en) * 2002-05-17 2003-11-19 Seiko Epson Corp Circuit fabrication method
US7906415B2 (en) 2006-07-28 2011-03-15 Xerox Corporation Device having zinc oxide semiconductor and indium/zinc electrode

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4796975A (en) * 1987-05-14 1989-01-10 Amphenol Corporation Method of aligning and attaching optical fibers to substrate optical waveguides and substrate optical waveguide having fibers attached thereto
US4810637A (en) * 1985-05-07 1989-03-07 Thomson-Csf Non-linear control element for a flat electrooptical display screen and a method of fabrication of said control element
US5049527A (en) * 1985-06-25 1991-09-17 Hewlett-Packard Company Optical isolator
US5249245A (en) * 1992-08-31 1993-09-28 Motorola, Inc. Optoelectroinc mount including flexible substrate and method for making same
US5471552A (en) * 1995-02-22 1995-11-28 Industrial Technology Research Institute Fabrication of static-alignment fiber-guiding grooves for planar lightwave circuits
US5496743A (en) * 1992-02-28 1996-03-05 At&T Corp. Method of making an article comprising a semiconductor device
US5698452A (en) * 1994-04-25 1997-12-16 Lucent Technologies Inc. Method of making integrated detector/photoemitter with non-imaging director
US5699073A (en) * 1996-03-04 1997-12-16 Motorola Integrated electro-optical package with carrier ring and method of fabrication

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132248A (en) * 1988-05-31 1992-07-21 The United States Of America As Represented By The United States Department Of Energy Direct write with microelectronic circuit fabrication
US5385848A (en) * 1993-09-20 1995-01-31 Iowa Thin Film Technologies, Inc Method for fabricating an interconnected array of semiconductor devices
US5820932A (en) * 1995-11-30 1998-10-13 Sun Chemical Corporation Process for the production of lithographic printing plates
JP3268723B2 (en) * 1996-03-25 2002-03-25 シャープ株式会社 Active matrix substrate and liquid crystal display

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4810637A (en) * 1985-05-07 1989-03-07 Thomson-Csf Non-linear control element for a flat electrooptical display screen and a method of fabrication of said control element
US5049527A (en) * 1985-06-25 1991-09-17 Hewlett-Packard Company Optical isolator
US4796975A (en) * 1987-05-14 1989-01-10 Amphenol Corporation Method of aligning and attaching optical fibers to substrate optical waveguides and substrate optical waveguide having fibers attached thereto
US5496743A (en) * 1992-02-28 1996-03-05 At&T Corp. Method of making an article comprising a semiconductor device
US5249245A (en) * 1992-08-31 1993-09-28 Motorola, Inc. Optoelectroinc mount including flexible substrate and method for making same
US5698452A (en) * 1994-04-25 1997-12-16 Lucent Technologies Inc. Method of making integrated detector/photoemitter with non-imaging director
US5471552A (en) * 1995-02-22 1995-11-28 Industrial Technology Research Institute Fabrication of static-alignment fiber-guiding grooves for planar lightwave circuits
US5699073A (en) * 1996-03-04 1997-12-16 Motorola Integrated electro-optical package with carrier ring and method of fabrication

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004068536A3 (en) * 2003-01-30 2005-01-20 Univ Cape Town A thin film semiconductor device and method of manufacturing a thin film semiconductor device
WO2006080839A2 (en) * 2005-01-25 2006-08-03 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Electronic device comprising an electronic component and encapsulation members
WO2006080839A3 (en) * 2005-01-25 2006-12-28 Tno Electronic device comprising an electronic component and encapsulation members
US7776724B2 (en) 2006-12-07 2010-08-17 Innovalight, Inc. Methods of filling a set of interstitial spaces of a nanoparticle thin film with a dielectric material
US7851336B2 (en) 2008-03-13 2010-12-14 Innovalight, Inc. Method of forming a passivated densified nanoparticle thin film on a substrate
US8273669B2 (en) 2008-03-13 2012-09-25 Innovalight, Inc. Method of forming a passivated densified nanoparticle thin film on a substrate
US8247312B2 (en) 2008-04-24 2012-08-21 Innovalight, Inc. Methods for printing an ink on a textured wafer surface

Also Published As

Publication number Publication date
WO1999050889A2 (en) 1999-10-07
WO1999050889A3 (en) 1999-12-23
AU3203199A (en) 1999-10-18
AU3203099A (en) 1999-10-18

Similar Documents

Publication Publication Date Title
US7115983B2 (en) Multilayer, thin-film electronic devices
EP1181720B1 (en) Methods and apparatus for fabricating a multiple modular assembly
US6850312B2 (en) Apparatuses and methods for flexible displays
US7046328B2 (en) Apparatuses and methods for flexible displays
US6281038B1 (en) Methods for forming assemblies
US6468638B2 (en) Web process interconnect in electronic assemblies
US6590346B1 (en) Double-metal background driven displays
US6555408B1 (en) Methods for transferring elements from a template to a substrate
US6844673B1 (en) Split-fabrication for light emitting display structures
US6965361B1 (en) Method of manufacture of active matrix addressed polymer LED display
US20080224153A1 (en) Electronic device, method of producing the same, light-emitting diode display unit, and method of producing the same
US20070115645A1 (en) Apparatuses and methods for forming wireless RF labels
KR20040053495A (en) Method for making substrate and method for making Organic electro luminescence display device using the same,Organic electro luminescence display device
WO1999050890A1 (en) Method for making multilayer thin-film electronics
JP2006092908A (en) Double-sided display panel, its manufacturing method, and electronic apparatus
TW200923871A (en) Integrated display module
US20240038775A1 (en) Display panel and method for manufacturing same
CN115101505A (en) Substrate, preparation method and electronic device
CN106358360A (en) Flexible electronic device and manufacturing method thereof
KR100925456B1 (en) Method of manufacturing liquid crystal display
KR100659113B1 (en) Flat panel display apparatus
CN114664745A (en) Display panel and manufacturing method thereof
KR20070050776A (en) Organic light emitting diode display panel
KR20050001782A (en) A multi-layer pcb and the fabricating method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
NENP Non-entry into the national phase

Ref country code: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWE Wipo information: entry into national phase

Ref document number: 09647193

Country of ref document: US

122 Ep: pct application non-entry in european phase