WO1999059190A3 - Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on a workpiece - Google Patents

Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on a workpiece Download PDF

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Publication number
WO1999059190A3
WO1999059190A3 PCT/US1999/010331 US9910331W WO9959190A3 WO 1999059190 A3 WO1999059190 A3 WO 1999059190A3 US 9910331 W US9910331 W US 9910331W WO 9959190 A3 WO9959190 A3 WO 9959190A3
Authority
WO
WIPO (PCT)
Prior art keywords
workpiece
manufacture
manufacturing tool
metallization levels
tool architecture
Prior art date
Application number
PCT/US1999/010331
Other languages
French (fr)
Other versions
WO1999059190A2 (en
Inventor
E Henry Stevens
Robert W Berner
Original Assignee
Semitool Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/076,695 external-priority patent/US6143126A/en
Priority claimed from US09/076,565 external-priority patent/US6376374B1/en
Priority claimed from US09/128,238 external-priority patent/US6120641A/en
Application filed by Semitool Inc filed Critical Semitool Inc
Priority to EP99922934A priority Critical patent/EP1086485A2/en
Priority to JP2000548908A priority patent/JP2002515645A/en
Publication of WO1999059190A2 publication Critical patent/WO1999059190A2/en
Publication of WO1999059190A3 publication Critical patent/WO1999059190A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation

Abstract

A semiconductor manufacturing tool configuration and corresponding process for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a semiconductor workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed.
PCT/US1999/010331 1998-05-12 1999-05-12 Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on a workpiece WO1999059190A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP99922934A EP1086485A2 (en) 1998-05-12 1999-05-12 Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on a workpiece
JP2000548908A JP2002515645A (en) 1998-05-12 1999-05-12 Method and manufacturing tool structure for use in forming one or more metallization levels in a workpiece

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US09/076,695 US6143126A (en) 1998-05-12 1998-05-12 Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on an integrated circuit
US09/076,565 US6376374B1 (en) 1998-05-12 1998-05-12 Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece
US09/076,695 1998-05-12
US09/076,565 1998-05-12
US09/128,238 US6120641A (en) 1998-05-12 1998-08-03 Process architecture and manufacturing tool sets employing hard mask patterning for use in the manufacture of one or more metallization levels on a workpiece
US09/128,238 1998-08-03

Publications (2)

Publication Number Publication Date
WO1999059190A2 WO1999059190A2 (en) 1999-11-18
WO1999059190A3 true WO1999059190A3 (en) 2000-04-06

Family

ID=27372911

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/010331 WO1999059190A2 (en) 1998-05-12 1999-05-12 Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on a workpiece

Country Status (4)

Country Link
EP (1) EP1086485A2 (en)
JP (1) JP2002515645A (en)
TW (1) TW494443B (en)
WO (1) WO1999059190A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9570330B2 (en) 2002-07-22 2017-02-14 Brooks Automation, Inc. Substrate processing apparatus

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004010476A2 (en) 2002-07-22 2004-01-29 Brooks Automation, Inc. Substrate processing apparatus
US8960099B2 (en) 2002-07-22 2015-02-24 Brooks Automation, Inc Substrate processing apparatus
US7988398B2 (en) 2002-07-22 2011-08-02 Brooks Automation, Inc. Linear substrate transport apparatus
JP2011154380A (en) * 2003-03-20 2011-08-11 Toshiba Mobile Display Co Ltd Method of forming display device
US7215006B2 (en) * 2005-10-07 2007-05-08 International Business Machines Corporation Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement
US20070117377A1 (en) * 2005-11-23 2007-05-24 Chih-Chao Yang Conductor-dielectric structure and method for fabricating
US8496790B2 (en) * 2011-05-18 2013-07-30 Applied Materials, Inc. Electrochemical processor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5178682A (en) * 1988-06-21 1993-01-12 Mitsubishi Denki Kabushiki Kaisha Method for forming a thin layer on a semiconductor substrate and apparatus therefor
US5256565A (en) * 1989-05-08 1993-10-26 The United States Of America As Represented By The United States Department Of Energy Electrochemical planarization
US5302209A (en) * 1991-02-15 1994-04-12 Semiconductor Process Laboratory Co., Ltd. Apparatus for manufacturing semiconductor device
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5563095A (en) * 1994-12-01 1996-10-08 Frey; Jeffrey Method for manufacturing semiconductor devices
US5933758A (en) * 1997-05-12 1999-08-03 Motorola, Inc. Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer
US5994678A (en) * 1997-02-12 1999-11-30 Applied Materials, Inc. Apparatus for ceramic pedestal and metal shaft assembly

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5178682A (en) * 1988-06-21 1993-01-12 Mitsubishi Denki Kabushiki Kaisha Method for forming a thin layer on a semiconductor substrate and apparatus therefor
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5256565A (en) * 1989-05-08 1993-10-26 The United States Of America As Represented By The United States Department Of Energy Electrochemical planarization
US5302209A (en) * 1991-02-15 1994-04-12 Semiconductor Process Laboratory Co., Ltd. Apparatus for manufacturing semiconductor device
US5563095A (en) * 1994-12-01 1996-10-08 Frey; Jeffrey Method for manufacturing semiconductor devices
US5994678A (en) * 1997-02-12 1999-11-30 Applied Materials, Inc. Apparatus for ceramic pedestal and metal shaft assembly
US5933758A (en) * 1997-05-12 1999-08-03 Motorola, Inc. Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9570330B2 (en) 2002-07-22 2017-02-14 Brooks Automation, Inc. Substrate processing apparatus

Also Published As

Publication number Publication date
TW494443B (en) 2002-07-11
EP1086485A2 (en) 2001-03-28
JP2002515645A (en) 2002-05-28
WO1999059190A2 (en) 1999-11-18

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