WO1999066711A1

WO1999066711A1 - Method and circuit for improving an imaging system with a charge coupled device

Info

Publication number: WO1999066711A1
Application number: PCT/US1999/013640
Authority: WO
Inventors: Andrew Paule; Thomas Domagala
Original assignee: Zap Technologies, Inc.
Priority date: 1998-06-19
Filing date: 1999-06-18
Publication date: 1999-12-23
Also published as: WO1999066711A9; AU4689599A

Abstract

The present invention provides a circuit which is advantageously adaptable to existing CCD phase and transfer gate circuitry (140) to eliminate most of the input, and consequently most of the output noise which heretofore has been an unrecognized (or at least unaddressed) problem associated with poor resolution and image distortion of CCD based imaging systems. The invention is based on designing a circuit device for driving the CCD phase and transfer gates (140) to feed a clean signal such that the distortion present on the output signal is minimized. The present invention utilizes a pre-driver circuit (110a-c) that functions as a filter to control the voltage present on the gate of a FET driver (120a-c), and minimizes ring in the turn-on and turn-off regions where input/output are non-linear.

Description

Title: METHOD AND CIRCUIT FOR IMPROVING AN IMAGING SYSTEM WITH A CHARGE COUPLED DEVICE

1. Technical Field

The present invention relates to circuit devices for improving image quality in digital

imaging systems. Specifically, the invention pertains to a discovery that ringing and other

disturbances within the phase and transfer gate drive circuitry lead to exaggerated imaging

problems with charge coupled devices. Thus, the present invention relates to removing this

problem by filtering the noise and other disturbances. In particular, the present invention

provides circuit solutions that are adaptable for charge-coupled device digital imaging and

camera systems to enable clean current drive while enhancing the digital images.

2. Background

A charge coupled device ("CCD") is a device capable of generating charge by intrinsic

absorption, collecting the charge into packets, and shifting the charge packets in response to

input voltages. CCD based imaging systems are commonly used in capturing images.

Specifically digital camera systems have been in use for a few years now and there is sufficient

familiarity of these products by consumers in the market.

CCD imaging systems are used in various applications, including digital photography

(where the CCD replaces familiar film), industrial optical inspection and grading, and optical

data acquisition. The application of digital imaging systems includes such varied uses as:

measurement of size and shape of objects-color, size and shape classification; and object sorting

based on the above measurements.

CCD imaging systems generally contain arrays of evenly spaced, solid state

photosensitive elements commonly referred to as pixels. These pixels comprise two separate

parts: 1) a photosite, where light striking the surface is converted into a charge packet by a

process known as intrinsic absorption, and; 2) a set of transfer wells that are used to store and shift the charge packets created by the photosites. By applying accurate control voltages to these two parts, the CCD is capable of measuring photon flux, more commonly referred to as brightness.

To start an image capture, the photosites are generally emptied of stored charge, and then allowed to integrate the charge generated by intrinsic absorption for a given period of time, and then this charge is emptied into the associated transfer well creating a charge packet. These charge packets are then shifted in a perpendicular plane to an output amplifier stage. By applying accurate control of this charge packet shifting, precise measurements of brightness over a desired area can be achieved.

In the last few years, CCD based digital imaging systems are gaining in popularity, applied in desktop scanners, digital cameras, and other device methodologies.

Unfortunately, charge transfer has not been ideal, resulting in a loss of modulation transfer function ("MTF") in image data and appearing as smears, non-linear transfers, and the like observed as distortions of the resultant digital image. Although current CCD technology extends into the 70dB+ range, the standards for digital imaging are still stuck in the 60dB range. Accordingly, what is needed in the art is a better understanding and a corresponding solution for the alleviation of these problems. 3. Summary of the Invention

The present invention provides a circuit which is advantageously adaptable to existing CCD phase and transfer gate circuitry to eliminate most of the input, and consequently most of the output noise which heretofore has been an unrecognized (or at least unaddressed) problem associated with poor resolution and image distortion of CCD based imaging systems. The invention is based on designing a circuit device for driving the CCD phase and transfer gates to feed a clean signal such that the distortion present on the output signal is minimized. The present invention utilizes a pre-driver circuit that functions as a filter to control the voltage present on the gate of a FET driver, and minimize ring in the turn-on and turn-off regions where input/output are non-linear.

4. Brief Description of the Drawings

Figure 1 is a prior art schematic block diagram of a CCD phase and transfer gate driver circuit showing multiple gate drivers from an N gate CCD.

Figure 2 is a prior art schematic diagram of a phase and transfer gate drive circuit . Figure 3 shows a transconductance curve of a typical FET.

Figure 4 is a schematic block diagram of one embodiment of a CCD phase and transfer gate driver circuit of the present invention showing multiple gate drivers from an N gate CCD. Figure 5 is a schematic diagram of one embodiment of a phase and transfer gate drive circuit of the present invention.

Figure 6 is a schematic diagram of another embodiment of a phase and transfer gate drive circuit of the present invention.

Figure 7 is a schematic diagram of yet another embodiment of a phase and transfer gate drive circuit of the present invention.

5. Detailed Description

5.1 Problem Discovery and Overview

Since amplifiers have long since surpassed the 73dB capability, and most CCDs are capable of reaching into this realm, we had suspected that the most likely other analog signal link attributable for inhibiting CCD performance was the transfer and gate (clock) driver circuitry.

The basis for the invention was the evaluation and analysis of existing CCD phase and transfer gate drive systems. Figure 1 represents such a system 50. As shown in Figure 1, typical phase and transfer drive circuitry 50 includes a pre-driver circuit 60 connected in series with a driver circuit 70 to drive phase and transfer signals 55a-c to corresponding phase and transfer gates 77a-c of a CCD 70, which can have from 1 to N phase and transfer gates.

As shown in Figure 2, a typical pre-drive circuit 60 includes pre-drive input 61, Rl resistor 62, R2 resistor 64, and pre-drive output 69. A driver circuit 70 for a CCD 80 is normally implemented with a field effect transistor ("FET") driver 72 that has driver input 71 and driver output 77. The CCD 80 includes phase and transfer gates 81 for driving (or clocking) the charged photo cells, which may be modeled with a capacitor 83. A FET driver 72 is basically a FET with its gate corresponding to the driver input 71 and its drain/source serving as the controllable channel between a supply voltage, a current limiting resistor 74 and the driver output 77. The gate of a FET is the capacitive node that allows control of the current through the pinch region of the device. Small variations in the gate voltage result in large changes in the current through a FET. Thus, amplification is possible with these devices.

Current is fed through FET (driver 72) to the capacitive node on the phase and transfer gates to create the needed voltages to force char e packet transfer. Because the drivers 70 are trying to charge what may be seen as capacitors 83 with up 10,000pF, the instantaneous current changes may be enormous. Accurate control of these current changes has traditionally been done by utilizing a resistor 74 to control slope and ring on the capacitive node 83. However, it has been discovered that control on these drivers 70 still results in a large proportion of inaccurate ring and transient behavior.

The output signal at driver output 77 was evaluated, and noise, ringing and similar disturbances were noted. Various techniques of reducing the noise and ring were attempted with conventional approaches (e.g., varying the values of resistors 62 and 64 of the pre-driver circuit 60. This approach was not successful, and the characteristics of the FET driver 72 were more particularly analyzed. Figure 3 represents a transconductance curve 95 for a typical FET. This curve is taken when the FET is in turn on and mobility limited regions, and are not generally thought of when using them as capacitive drive elements.

There are four distinct regions of gate voltage vs. conductivity in a FET: the nonconducting region; the turn-on region; the linear region; and the saturation region. The non- conducting and linear regions are well understood and documented in data sheets for most devices, but the basis of the analysis was directed to the turn-on and saturation regions because these are the regions where small voltage differences on the gate give non-linear response in the output current, which was suspected to be a possible source for the problems.

The turn-on region in a FET is best described as the region in which the FET's diffused channel is reaching (I)e point of surface inversion required to conduct current from the drain to the source. In this region, there is still sonic current being transferred due to mobility of the carriers, and this current is very non-linear and best described by a function of the nature

I_D=k(V_GSN_T)² where k is sonic proportionality constant that is dependant on temperature to the form k° T ^M and various FET characteristics out of the scope of this description. Note that the actual function used to describe this region will vary from manufacturing process and FET type being used, but all FETs have this type of nonlinear response due to the fundamental physics being applied. The saturation region of a FET is best described as the region where the FET is no longer able to supply additional current due to carrier mobility constraints. In the linear region, ID is proportional to V_GS - V_τ according to the following equation:

I_D=2k[V_GS-V_T)V_DS-0.5_DS ²] As V_GS approaches V_DS, I_D once again enters a non-linear region. These two regions are generally supplied in data sheets characterized for individual device types, with the regions under discussion being in the "On-Region" and "Transfer" curves. Examination of these curves for my device will reveal what is under discussion. What is to be remembered is that these two regions are non-linear in terms of the controlling voltage vs. the output current (and voltage). Thus, it was discovered that not only ringing and noise created at the driver output 77 was problematic, but also, that even seemingly small ring and disturbances at the driver input 71 is also problematic because of nonlinear nature of the operated region of the driver 72.

The first problem is ring in the control inputs. Ring can cause a number of factors to appear on the output of the CCD amplifier chain, not the least of which is smear. Smear is the inability of the transfer well to be fully emptied in one direction without electrons being accumulated from neighboring wells. This facet is easily shown on output images, and causes a loss of MFT in the image. MTF loss due to these factors and the general charge transfer inefficiency in CCD's can be as high as 8%, well beyond the justification for having even 8 bit A/D converters at the output.

The next item is charge injection. CCD devices typically use a diode to protect inputs from transients. Reverse biasing this diode (V^ < V_ss) will result in die diode transferring electrons from the substrate to the photosite or transfer well. If this happens, it shows up as an increase in signal from the place that it occurs, mid because of the complicated structure of a CCD, this may occur at any number of pixels in the CCD, and can ruin a digital image.

An ideal drive voltage would force the voltage V_GS to go from 0 to high side instantaneously, and there would be no consideration for the linearity of the FET transimpedance characteristics. In reality, the ability to move electrons from one position to another is limited, and there is ringing associated with both the low-high transition, and the high-low transition which is magnified non-linearly through the FET because of the above noted R_DS vs. V_GS curve. This severe non-linearity and ring generation has been discovered to be a cause of many of the problems associated with digital imaging systems.

The basic model for this understanding is the control of the region of a FET in between the full on and full off points, where non-linear effects occur. By controlling the input ring, control of these non-linear regions is realized, and by controlling the voltage over/undershoot that accompany the ringing, other non-desirable aspects of CCD use are also minimized.

In general, transfer and phase control clock signals are required to have rise and fall times sufficient so that there is no capacative coupling to the input waveform or the device's ground plane. In addition, charge injection can occur if the gate voltage on the CCD swings below it's ground for periods related to specific device structure. In addition, these waveforms must be controlled to the extent that the well is allowed to fully empty during the period, and no electrons from neighboring wells can spill into the well.

Thus, CCD phase and transfer gate drive circuitry should produce a clean current drive source that can charge a capacitive input of up to 10,000pF as quickly and with as little noise as possible. In order to produce such a signal, as now realized from the above discussion, the phase and transfer signal 55 coming input to the driver 72 should be reasonably free of noise, ringing, and/or other disturbances. Therefore, the present invention provides circuitry for achieving such objectives.

5.2 Description of a First Embodiment Figure 4 depicts one embodiment of a circuit 100 for implementing the present invention.

Circuit 100 includes pre-driver circuits HOa-c, driver circuits 120a-c, and a CCD 140 having N (e.g., 3) transfer and phase gate inputs 141a-c. Each pre-driver circuit 110 receives a phase and transfer ("P&T") signal 105 (e.g., TTL driven), filters the signal, and outputs filtered signal at a pre-driver output 119. The driver circuit 120 has a driver input 121 connected to the pre-driver output 119 and a driver output 127 connected to a phase and transfer gate 141 of the CCD 140. With reference to Figure 5, one embodiment of the pre-driver circuit 110 comprises an inductive low-pass filter, which includes an inductive device 112, and resistors 114 and 116 configured to form a low-pass filter with an input at 105 and an output at 119. An inductive device 112 may be any device that functions as an inductor. Such a device could include but is not limited to passive inductor devices (e.g., coil, bead) and active simulated inductors (e.g., gyrator configurations as are described for example in Dorf s the Electrical Engineering Handbook, pp. 680-81, [1993], which is hereby incoφorated by reference into this application). The values for the particular pre-driver circuit 110 components should be selected in light of the particular phase and transfer signal, as well as the particular characteristics (e.g, trace effects, ambient noise) of the circuit environment, the pre-driver circuit 110 should be tuned to optimally filter noise from the phase and transfer signal 105 and to inhibit ringing at the input of the driver input 12 1. For example, with phase and transfer signals ranging, e.g., from 50 KHz. to 5 MHZ., component values could be as follows: inductive device 112 (10-500 pH), resistor 114 (10K Ohms), and resistor 116 (100K Ohms).

As shown in Figure 5, one embodiment of the driver circuit 120 includes a FET driver 122 (e.g., Maxim 627), resistor 124 (e.g., 10-20 Ohms), and inputs/outputs 121 and 127, respectively. The driver input 121 is connected to the gate of the FET from FET driver 122. Resistor 124 is connected between the output of the FET driver 122 and the driver output 127 to control the amount of current output from the FET driver 122.

The CCD 140 includes phase and transfer gates 141 and charge coupled transfer wells, which may be modeled with capacitors 143. (Note that in Figure 5, only one phase and transfer gate is depicted. However, a CCD may include from 1 to N phase and transfer gates.) In one embodiment, the CCD is implemented with a Kodak™ KLI-6003 CCD.

In operation, the pre-driver circuit 110 functions as a low-pass filter to filter noise from the P&T signal 105 before it is provided to the driver circuit 120. In addition, the predriver circuit is tuned to inhibit ringing at the driver circuit input 121. In turn, the driver circuit 120 drives the phase and transfer gate 141 in response to the phase and transfer signal 105. It should be noted that the pre-driver circuit 110 may be implemented with any suitable filter (e.g., low- pass, band-pass), depending on the particular application and operational parameters. 5.3 Other Embodiments

It will be seen by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention. For example, as shown in Figure 6, the driver circuit could include a relatively large resistor (such as resistor 226) coupled between the driver output and ground to assist in dissipating noise at the driver output. In addition, as shown in Figure 7, the pre-driver circuit could be implemented with a capacitive solution for a filter (e.g., low-pass filter). However, in order to reduce the noise and ringing on the gate of the FET to the level required, the rise time of the signal on the gate of the FET may be slowed beyond the FET drivers recommended time for pinch voltage delta.

Accordingly, the invention is not limited to what is shown in the drawings and described in the specification but only as indicated in the appended claims. 6. Remarks With proper implementation, the present invention provides a system where the CCD is the weak link in the chain, resulting in true 12 bit (and above) capable systems. A universally implementable set of circuit devices to control transfer characteristics of FET type devices in driving CCD clock (or phase and transfer gate) circuitry is provided herein. Other advantages of the present invention will become more fully apparent and understood with reference to the appended drawings and claims.

Claims

7. ClaimsWe claim as follows:

1. A charge coupled device circuit for an imaging system, comprising:

(a) a charge coupled device having a phase and transfer gate input for receiving a phase and transfer signal; and (b) a driver having a driver input and a driver output, the driver output being electrically connected to the phase and transfer gate; and

(c) a pre-driver circuit having a pre-driver input, a pre-driver output and a low pass filter connected between the pre-driver input and the pre-driver output, the pre- driver output being electrically connected to the driver input and the pre-driver input adapted to receive the phase and transfer signal, wherein the pre-driver circuit filters from the phase and transfer signal before being applied to the driver input.

2. The imaging apparatus of claim 1, wherein the driver is a FET driver.

3. The circuit of claim 2, wherein the low pass filter includes an inductive device connected between the pre-drive input and output.

4. The apparatus of claim 2, wherein the inductive device is a bead inductor.

5. The apparatus of claim 1 , wherein the inductive device is implemented with an active circuit for simulating a floating inductor.

6. The apparatus of claim 2, further comprising a first resistor connected in series with the inductive device.

7. The apparatus of claim 6, wherein the first resistor is connected between the pre- driver output and the driver input.

8. The apparatus of claim 7, further including a second resistor electrically connected between the driver input and a ground.

9. The apparatus of claim 8, further comprising a third resistor electrically connected between the driver output and the phase and transfer gate.

10. The apparatus of claim 9, further including a fourth resistor electrically connected between the phase and transfer gate and the ground.

11. The apparatus of claim 10, further comprising a TTL driver connected in series with the inductive device and having an input for receiving the phase and transfer gate signal.

12. A method for applying a phase and transfer signal to a phase and transfer gate of a charge coupled device, the method comprising: (a) filtering the phase and transfer signal with a low pass filter; and

(b) driving the phase and transfer gate with the filtered phase and transfer signal.

13. The method of claim 12, wherein the act of filtering the phase and transfer signal with a low pass filter includes the act of filtering the phase and transfer signal with an inductive device.

14. The method of claim 13, wherein the act of filtering the phase and transfer signal with an inductive device includes the act of filtering the phase and transfer signal with a passive inductor.

15. The method of claim 13, wherein the act of filtering the phase and transfer signal with an inductive device includes the act of filtering the phase and transfer signal with an active inductive simulator.

16. The method of claim 12, wherein the act of filtering the phase and transfer signal with a low pass filter includes the act of filtering the phase and transfer signal with an inductive device that is connected in series with a first resistor.

17. The method of claim 16, further including the act of coupling a node of the first resistor to ground with a second resistor.

18. The method of claim 17, wherein the act of driving the phase and transfer gate with the filtered phase and transfer signal includes the act of driving the filtered phase and transfer signal through a third resistor that is coupled to the phase and transfer gate.

19. The method of claim 12, wherein the act of driving the phase and transfer gate with the filtered phase and transfer signal includes the act of driving the filtered phase and transfer signal through a FET driver.