WO2000013215A1 - Ruthenium silicide diffusion barrier layers and methods of forming same - Google Patents
Ruthenium silicide diffusion barrier layers and methods of forming same Download PDFInfo
- Publication number
- WO2000013215A1 WO2000013215A1 PCT/US1999/018114 US9918114W WO0013215A1 WO 2000013215 A1 WO2000013215 A1 WO 2000013215A1 US 9918114 W US9918114 W US 9918114W WO 0013215 A1 WO0013215 A1 WO 0013215A1
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- WIPO (PCT)
- Prior art keywords
- barrier layer
- layer
- rusi
- ruthenium
- diffusion barrier
- Prior art date
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- 230000004888 barrier function Effects 0.000 title claims abstract description 137
- 238000009792 diffusion process Methods 0.000 title claims abstract description 111
- 238000000034 method Methods 0.000 title claims abstract description 86
- 229910052707 ruthenium Inorganic materials 0.000 title claims abstract description 71
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 title claims abstract description 65
- 229910021332 silicide Inorganic materials 0.000 title description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title description 2
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 78
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 77
- 239000010703 silicon Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000003990 capacitor Substances 0.000 claims abstract description 38
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 36
- 238000000151 deposition Methods 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 28
- 239000002243 precursor Substances 0.000 claims description 27
- 229910052697 platinum Inorganic materials 0.000 claims description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 21
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 21
- 239000003989 dielectric material Substances 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- QXYJCZRRLLQGCR-UHFFFAOYSA-N dioxomolybdenum Chemical compound O=[Mo]=O QXYJCZRRLLQGCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 11
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 239000012686 silicon precursor Substances 0.000 claims description 9
- 229910052741 iridium Inorganic materials 0.000 claims description 8
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 8
- 229910019834 RhO2 Inorganic materials 0.000 claims description 6
- KZYDBKYFEURFNC-UHFFFAOYSA-N dioxorhodium Chemical compound O=[Rh]=O KZYDBKYFEURFNC-UHFFFAOYSA-N 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 6
- 229910052703 rhodium Inorganic materials 0.000 claims description 6
- 239000012298 atmosphere Substances 0.000 claims description 4
- 239000011261 inert gas Substances 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 175
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 43
- 238000006243 chemical reaction Methods 0.000 description 27
- 230000008569 process Effects 0.000 description 24
- 239000007789 gas Substances 0.000 description 21
- 230000008021 deposition Effects 0.000 description 17
- 210000000352 storage cell Anatomy 0.000 description 13
- 235000012431 wafers Nutrition 0.000 description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- -1 for example Chemical class 0.000 description 10
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 9
- 239000000376 reactant Substances 0.000 description 6
- 229910052786 argon Inorganic materials 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 5
- 239000010948 rhodium Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 239000012159 carrier gas Substances 0.000 description 4
- 239000001307 helium Substances 0.000 description 4
- 229910052734 helium Inorganic materials 0.000 description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 210000004027 cell Anatomy 0.000 description 3
- 150000001993 dienes Chemical class 0.000 description 3
- 238000010790 dilution Methods 0.000 description 3
- 239000012895 dilution Substances 0.000 description 3
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 3
- 229910000457 iridium oxide Inorganic materials 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910020294 Pb(Zr,Ti)O3 Inorganic materials 0.000 description 2
- 229910010252 TiO3 Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052746 lanthanum Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000012705 liquid precursor Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 2
- 229910052754 neon Inorganic materials 0.000 description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910003446 platinum oxide Inorganic materials 0.000 description 2
- FGIUAXJPYTZDNR-UHFFFAOYSA-N potassium nitrate Chemical compound [K+].[O-][N+]([O-])=O FGIUAXJPYTZDNR-UHFFFAOYSA-N 0.000 description 2
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000003039 volatile agent Substances 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- 229910003327 LiNbO3 Inorganic materials 0.000 description 1
- 229910003781 PbTiO3 Inorganic materials 0.000 description 1
- 229910000629 Rh alloy Inorganic materials 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 229910003822 SiHCl3 Inorganic materials 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- SIGRRDAVQRKJGV-UHFFFAOYSA-N carbon monoxide;cyclopentane;ruthenium(1+) Chemical class [Ru+].[O+]#[C-].[O+]#[C-].[CH]1[CH][CH][CH][CH]1 SIGRRDAVQRKJGV-UHFFFAOYSA-N 0.000 description 1
- NQZFAUXPNWSLBI-UHFFFAOYSA-N carbon monoxide;ruthenium Chemical group [Ru].[Ru].[Ru].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-] NQZFAUXPNWSLBI-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- YHGGQZOFJGJAMR-UHFFFAOYSA-N cyclopenta-1,3-diene ruthenium Chemical compound C1=CC=CC1.C1=CC=CC1.[Ru] YHGGQZOFJGJAMR-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910003450 rhodium oxide Inorganic materials 0.000 description 1
- 150000003303 ruthenium Chemical class 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052990 silicon hydride Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Definitions
- the present invention relates to semiconductor devices and the fabrication thereof. More particularly, the present invention pertains to diffusion barrier layers.
- DRAMs dynamic random access memories
- SRAMs static random access memories
- FE ferroelectric memories
- conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers in contact holes, vias, etc. In many applications, it is preferable that the materials used provide effective diffusion barrier characteristics.
- conductive materials used in the formation of storage cell capacitors of memory devices e.g., DRAMs.
- memory devices As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices.
- One way to retain storage capacity of storage cell capacitors of the memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes.
- One or more layers of various conductive materials may be used as the electrode material.
- one or more of the layers of the conductive materials used for the electrodes must have certain diffusion barrier properties, e.g., silicon diffusion barrier properties.
- Such properties are particularly required when high dielectric constant materials are used for the dielectric layer of ine storage v-eli capacitor because of the processes used for forming such high dielectric materials, e.g., deposition of high dielectric materials usually occurs at high temperatures (generally greater than about 500° C) in an oxygen-containing atmosphere.
- high temperatures generally greater than about 500° C
- various metals and metallic compounds for example, metals such as platinum, and conductive metal oxides, such as ruthenium oxide, have been proposed as the electrodes or at least one of the layers of an electrode stack for use with high dielectric constant materials.
- reliable electrical connections should generally be constructed which do not diminish the beneficial properties of the high dielectric constant materials.
- Platinum and ruthenium oxide, used alone as an electrode, are generally too permeable to silicon to be used as a bottom electrode of a storage cell capacitor formed on a silicon substrate region. Because of the permeability of such materials to silicon, typically platinum is used as a layer in an electrode stack which acts as the electrode as well as a diffusion barrier for integration of capacitors directly formed on silicon.
- the electrode barrier structure includes layers of platinum:rhodium alloy, in addition to platinum:rhodium oxide layers, to form electrodes with diffusion barrier properties. Such alloy layers are formed using physical vapor deposition (PVD) processing, e.g., reactive RF sputtering processes. Further, for example, the article entitled "(Ba, Sr)TiO 3 Films
- Electrodes are fabricated which include electrode layers that are formed by deposition of a conductive material within a small high aspect ratio opening. Typically, sputtering does not provide a sufficiently conformal layer adequate for formation of an electrode layer within such a small high aspect ratio opening.
- barrier layers for use in other applications, e.g., interconnect applications, is also desirable.
- diffusion barriers are commonly used to prevent undesirable reactions in contact openings.
- RuSi x diffusion barrier layers along with structures incorporating such diffusion barrier layers and methods associated therewith, are described herein.
- a method for use in the fabrication of integrated circuits according to the present invention includes providing a substrate assembly having a surface.
- a diffusion barrier layer is formed over at least a portion of the surface.
- the diffusion barrier layer is formed of RuSi x , where x is in the range of about 0.01 to about 10.
- the diffusion barrier layer is formed of RuSi x , where x is in the range of about 1 to about 3, more preferably about 2.
- the barrier layer is formed by depositing RuSi x by chemical vapor deposition.
- the barrier layer is formed by forming a layer of ruthenium relative to a silicon containing region and performing an anneal to form RuSi x from the layer of ruthenium and the silicon containing region.
- a method for use in the formation of a capacitor according to the present invention includes forming a first electrode on a portion of a substrate assembly.
- a high dielectric material is formed over at least a portion of the first electrode and a second electrode is formed over the high dielectric material.
- At least one of the first and second electrodes includes a barrier layer formed of RuSi x , where x is in the range of about 0.01 to about 10.
- Another method for use in the formation of a capacitor includes providing a silicon containing region of a substrate assembly.
- a first electrode is formed on at least a portion of the silicon containing region of the substrate assembly.
- the first electrode includes a barrier layer of RuSi x , where x is in the range of about 0.01 to about 10.
- a high dielectric material is formed over at least a portion of the first electrode and a second electrode is provided over the high dielectric material.
- the formation of the barrier layer includes forming a layer of ruthenium on at least a portion of the silicon containing region. Thereafter, the layer of ruthenium formed on the at least a portion of the silicon containing region is annealed resulting in the RuSi x barrier layer.
- the layer of ruthenium may be deposited by chemical vapor deposition with a thickness of about 1 O ⁇ to about 300A.
- one or more conductive layers are formed relative to the RuSi x barrier layer.
- the one or more conductive layers are formed of at least one of a metal or a conductive metal oxide, e.g., formed from materials selected from the group of RuO 2 , RhO 2 , MoO 2 , IrO 2 , Ru, Rh, Pd, Pt, and Ir.
- a semiconductor device structure includes a substrate assembly including a surface and a diffusion barrier layer over at least a portion of the surface.
- the diffusion barrier layer is formed of RuSi x , where x is in the range of about 0.01 to about 10.
- at least a portion of the surface is a silicon containing surface and the structure includes one or more additional conductive layers over the diffusion barrier layer formed of at least one of a metal and a conductive metal oxide, e.g., formed from materials selected from the group of RuO 2 , RhO 2 , MoO 2 , IrO 2 , Ru, Rh, Pd, Pt, and Ir.
- a capacitor structure according to the present invention is also described.
- the capacitor structure includes a first electrode, a high dielectric material on at least a portion of the first electrode, and a second electrode on the dielectric material. At least one of the first and second electrode includes a diffusion barrier layer formed of RuSi x , where x is in the range of about 0.01 to about 10.
- An integrated circuit structure includes a substrate assembly including at least one active device and a silicon containing region.
- An interconnect is formed relative to the at least one active device and the silicon containing region.
- the interconnect includes a diffusion barrier layer on at least a portion of the silicon containing region.
- the diffusion barrier layer is formed of RuSi x , where x is in the range of about 0.01 to about 10.
- Figure 1 shows a device structure including a RuSi x diffusion barrier layer according to the present invention.
- Figures 2A-2C show one method of forming the RuSi x diffusion barrier layer according to the present invention.
- Figure 3 shows a structure including a RuSi x diffusion barrier layer according to the present invention as part of a multiple conductive layer stack.
- Figure 4 is a structure showing a high dielectric capacitor including an electrode having a RuSi x diffusion barrier layer according to the present invention.
- Figure 5 illustrates the use of a RuSi x diffusion barrier layer in a storage cell capacitor application.
- Figure 6 illustrates the use of a RuSi x diffusion barrier layer in a contact application.
- Figures 7A-7B show the results of a second example using a Pt/RuSi x stack formed on silicon.
- Figure 1 illustrates a structure 10 including a substrate assembly 11 and a RuSi x diffusion barrier layer 13 according to the present invention formed on a surface 12 of the substrate assembly 11, e.g., a silicon containing surface.
- the structure 10 further includes another conductive layer 14.
- the structure 10 is illustrative of the use of a RuSi x diffusion barrier layer for any application requiring an effective barrier layer, for example, to prevent diffusion from a silicon containing surface.
- the RuSi x diffusion barrier layer 13 may be used in the fabrication of semiconductor devices wherever it is necessary to prevent the diffusion of one material to an adjacent material.
- the substrate assembly 11 may be representative of a contact structure having an opening extending to a silicon containing surface. In such a structure, diffusion barriers are commonly used in such openings to prevent undesirable reactions, such as the reaction of a conductive contact material, e.g, aluminum, with the silicon containing surface.
- the RuSi x diffusion barrier layer 13 may be used in the formation of storage cell capacitors for use in semiconductor devices, e.g., memory devices.
- the RuSi x diffusion barrier layer is used within a stack of layers forming an electrode of a capacitor, e.g., the other layers including layers formed of materials such as platinum, ruthenium oxide, etc.
- substrate assembly refers to either a semiconductor substrate such as the base semiconductor layer, e.g., the lowest layer of a silicon material in a wafer, or a silicon layer deposited on another material, such as silicon on sapphire, or a semiconductor substrate having one or more layers or structures formed thereon or regions formed therein.
- various process steps may have been previously used to form GJ define regions, junctions, various structures or features, and openings such as vias, contact openings, high aspect ratio openings, etc.
- the amount of silicon incorporated into the RuSi x diffusion barrier layer 13 is sufficient to accomplish barrier characteristics for semiconductor devices, particularly for diffusion of silicon.
- the RuSi x diffusion barrier layer 13 according to the present invention includes an atomic composition such that x is in the range of about 0.01 to about 10. More preferably, x is in the range of about 1 to about 3, and yet more preferably, x is about 2.
- the thickness of the RuSi x diffusion barrier layer 13 is dependent upon the application for which it is used. Preferably, the thickness is in the range of about 10 A to about 300 A. More preferably, the thickness of the RuSi x diffusion barrier layer 13 is in the range of about 50 A to about 200 A. For example, this preferred thickness range of about 50 A to about 200 A is applicable to a RuSi x diffusion barrier layer used for forming a bottom electrode stack of a capacitor structure.
- the conductive layer 14 is representative of a single layer or one or more layers.
- the conductive layer may include one or more layers formed of a metal or metal oxide, or combinations thereof.
- such layers may include one of RuO 2 , MoO 2 , Rh, RhO 2 , IrO 2 , Ru, Pt, Pd and Ir, such as in the use of the RuSi x diffusion barrier layer in an electrode stack.
- the conductive layer 14 may be a contact material such as aluminum when the RuSi x diffusion barrier layer is used in a contact or interconnect application.
- Such conductive layers may be formed by any method known to those skilled in the art. The present invention is in no manner limited to any particular conductive layer or method for forming such conductive layers.
- the RuSi x diffusion barrier layer 13 may be formed by one or more various processes.
- the formation of the RuSi x diffusion barrier layer may be sputter deposited from a deposition target of RuSi x , may be deposited by the sputtering from a deposition target of ruthenium onto a silicon containing surface followed by an anneal, and may be deposited by chemical vapor deposition (CVD) using a ruthenium precursor and a silicon precursor, for example, such as atmospheric pressure chemical vaocr deposition, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or any other chemical vapor deposition technique.
- CVD chemical vapor deposition
- the RuSi x diffusion barrier layer may be formed by depositing a layer of ruthenium using CVD onto a silicon containing surface followed by an annealing process.
- the formation of the RuSi x diffusion barrier layer is attained with the use of CVD.
- Such a CVD process may be carried out in a chemical vapor deposition reactor, such as a reaction chamber available under the trade designation of 7000 from Genus, Inc., (Sunnyvale, CA), a reaction chamber available under the trade designation of 5000 from Applied Materials, Inc., (Santa Clara, CA), or a reaction chamber available under the trade designation of Prism from Novelus, Inc., (San Jose, CA).
- a chemical vapor deposition reactor such as a reaction chamber available under the trade designation of 7000 from Genus, Inc., (Sunnyvale, CA), a reaction chamber available under the trade designation of 5000 from Applied Materials, Inc., (Santa Clara, CA), or a reaction chamber available under the trade designation of Prism from Novelus, Inc., (San Jose, CA).
- any reaction chamber suitable for performing CVD may be used.
- Chemical vapor deposition is defined as the formation of a non- volatile solid film on a substrate by the reaction of vapor phase reactants, i.e., reactant gases, that contain desired components.
- the reactant gases are introduced into the reaction chamber.
- the gases decompose and react at a heated wafer surface to form the desired layer.
- Chemical vapor deposition is just one process of providing thin layers on semiconductor wafers, such as films of elemental metals or compounds, e.g., platinum, ruthenium oxide, iridium, molybdenum oxide, etc. Chemical vapor deposition processes are favored in many respects because of the process capability to provide highly conformal layers even within deep contacts and other openings.
- CVD processing is preferably used to provide highly conformal layers within deep contacts and other openings such as for lower electrodes of storage cell capacitors. It will be readily apparent to one skilled in the art that although CVD is the preferred process, that the CVD process may be enhanced by various related techniques such as plasma assistance, photo assistance, laser assistance, as well as other techniques.
- One preferred method of forming the RuSi x diffusion barrier layer 13 is by depositing RuSi x by chemical vapor deposition (CVD).
- the CVD process is conducted with a ruthenium precursor being delivered to a reaction chamber along with a silicon precursor.
- the ruthenium precursor is generally a liquid precursor.
- the ruthenium precursor is contained in a bubbler reservoir through which a carrier gas, such as helium or any other inert gas, i.e., a gas that is nonreactive with other gases of the process (e.g., nitrogen, argon, neon, and xenon), is bubbled through the reservoir containing the precursor to deliver the precursor to the reaction chamber.
- a carrier gas having a flow in the range of about one seem to about 500 seem may be used in a bubbler having a pressure in the range of about 0.5 torr to about 50 torr and a temperature in the range of about 30° C to about 70° C to deliver a ruthenium precursor to the reaction chamber.
- the ruthenium precursors are liquid ruthenium complexes of the following formula (Formula I): (diene)Ru(CO) 3 wherein: “diene” refers to linear, branched, or cyclic dienes, bicyclic dienes, tricyclic dienes, fluorinated derivatives thereof, combinations thereof, and derivatives thereof additionally containing heteroatoms such as halide, Si, S, Se, P, As, or N.
- die refers to linear, branched, or cyclic dienes, bicyclic dienes, tricyclic dienes, fluorinated derivatives thereof, combinations thereof, and derivatives thereof additionally containing heteroatoms such as halide, Si, S, Se, P, As, or N.
- the ruthenium precursors used according to the present invention include one of C 6 H g Ru(CO) 3 , bis(cyclopentadienyl) ruthenium (II), triruthenium dodecacarbonyl, and cyclopentadienyl dicarbonyl ruthenium (II) dimer.
- the silicon precursor is also provided to the reaction chamber.
- the silicon precursor may include a silicon hydride or silane such as dichlorosilane (DCS, SiH 2 Cl 2 ), silane (SiH 4 ), disilane (H 3 SiSiH 3 ), trichlorosilane (TCS, SiHCl 3 ), or any other silicon precursor as would be recongnized by one skilled in the art.
- the silicon precursor may be provided to the reaction chamber at a rate in the range of about 5 seem to about 500 seem. Preferably, the rate is about 100 seem.
- the manner in which the gases are introduced into the reaction chamber may include one of various techniques.
- the introduction may be accomplished with the use of compounds which are gases at room temperature or by heating a volatile compound and delivering the volatile compound to the reaction chamber using a carrier gas.
- solid precursors and various methods of vaporizing such solid precursors may also be used for introduction of reactant compounds into the chamber.
- the present invention is not limited to any particular technique.
- the reactant gases are admitted at separate inlet ports.
- an optional dilution gas i.e., a gas that is non- reactive with the reactant gases
- argon gas may be introduced into the chamber at a varied flow rate.
- the reaction chamber pressure is preferably maintained at a deposition pressure of about 0.1 torr to about 10 torr.
- the deposition temperature at the wafer surface upon which the RuSi x diffusion barrier layer 13 is deposited is preferably held at a temperature in a range of about 100° C to about 700° C, more preferably in the range of about 200° C to about 500° C.
- FIG. 2A-2C Another preferred method of forming a RuSi x diffusion barrier layer 19 according to the present invention is shown in Figures 2A-2C.
- This method forms the RuSi x diffusion barrier layer 19 by depositing a layer of ruthenium 18 as shown in Figure 2A onto a silicon containing region of substrate assembly 16 using CVD. The deposition of the ruthenium layer 18 is then followed by an annealing process to react the silicon containing region having silicon containing surface 17 with the ruthenium layer 18 to form the R.uSi x diffusion barrier layer 19 as shown in Figure 2B. Thereafter, a conductive layer 21 (e.g., one or more conductive layers like conductive layer 14 of Figure 1) is formed on the RuSi x diffusion barrier layer 19.
- a conductive layer 21 e.g., one or more conductive layers like conductive layer 14 of Figure 1
- the CVD process for depositing the ruthenium layer 18 is preferably conducted with a ruthenium precursor being delivered to a reaction chamber in generally the same manner as described above with regard to the deposition of RuSi x .
- the ruthenium precursor is generally a liquid precursor.
- the ruthenium precursor is contained in a bubbler reservoir through which a carrier gas, such as helium or any other inert gas, i.e., a gas that is nonreactive with other gases of the process (e.g., nitrogen, argon, neon, and xenon), is bubbled through the reservoir containing the precursor to deliver the precursor to the reaction chamber.
- a carrier gas such as helium or any other inert gas, i.e., a gas that is nonreactive with other gases of the process (e.g., nitrogen, argon, neon, and xenon)
- any ruthenium- containing precursor may be used in accordance with the present invention.
- the ruthenium precursor gas and optionally a dilution gas is provided to the reaction chamber.
- the reaction chamber pressure is preferably maintained at a deposition pressure of about 0.1 torr to about 10 torr.
- the deposition temperature at the wafer surface upon which the ruthenium layer 18 is deposited is preferably held at a temperature in a range of about 100° C to about 700° C, more preferably in the range of about 200° C to about 500° C.
- an annealing process is performed to form the RuSi x diffusion barrier layer 19 from the ruthenium layer 18 and the silicon containing region of substrate assembly 16.
- the annealing process is preferably performed in situ in the reaction chamber in a nitrogen atmosphere, although any other nonreactive atmosphere may be used, e.g., argon.
- the annealing temperature is within the range of about 400° C to about 1000° C, more preferably about 500° C.
- the anneal is preferably performed for a time period of about 0.5 minutes to about 60 minutes.
- the ruthenium layer 18 deposited for forming the RuSi x diffusion barrier layer 19 is preferably of a thickness in the range of about 10 A to about 300 A. More preferably, the thickness is in the range is about 50 A to about of 200 A; and even more preferably the thickness is about 100 A.
- Figure 3 shows a structure 20 including substrate assembly 22, e.g., a silicon substrate region, and a stack 24.
- the stack 24 includes conductive layers 31-34.
- One or more of the conductive layers 31-34 are RuSi x diffusion barrier layers according to the present invention.
- the one or more conductive layers may include conductive layers formed of various conductive materials.
- the conductive layers may include, but are clearly not limited to, preferably layers formed of metals, metal oxides or combinations thereof.
- such layers may include metals such as rhodium, palladium, ruthenium, platinum, and iridium or metal oxides such as ruthenium oxide, molybdenum oxide and iridium oxide.
- the stack 24 may be used for one or more numerous applications, e.g., interconnection applications, capacitor applications, etc.
- stack 24 may be used as an electrode for a storage cell capacitor with substrate assembly 22 including a silicon containing surface 23.
- the barrier properties of the stack 24 prevent silicon diffusion from silicon-containing surface 23.
- the layer 31 may be formed as the RuSi x diffusion barrier layer to prevent diffusion of silicon from silicon-containing surface 23 through stack 24 to adjacent layer or layers 29 or to the surface of the stack 24, as well as preventing oxygen diffusion to the silicon-containing surface.
- Figure 4 shows a structure 50 including substrate assembly 52, e.g., a silicon substrate, and capacitor structure 54 formed relative thereto.
- Capacitor structure 54 includes a first electrode 56, a second electrode 60, and a high dielectric constant layer 58 interposed therebetween.
- the dielectric layer may be any suitable material having a desirable dielectric constant, such as TaA, Ba ⁇ r ⁇ TiO, [BST], BaTiO 3 , SrTiO 3 , PbTiO 3 , Pb(Zr,Ti)O 3 [PZT], (Pb,La)(Zr,Ti)O 3 [PLZT], (Pb,La)TiO 3 [PLT], KNO 3 , and LiNbO 3 .
- a desirable dielectric constant such as TaA, Ba ⁇ r ⁇ TiO, [BST], BaTiO 3 , SrTiO 3 , PbTiO 3 , Pb(Zr,Ti)O 3 [PZT], (Pb,La)(Zr,Ti)O 3 [PLZT], (Pb,La)TiO 3 [PLT], KNO 3 , and LiNbO 3 .
- the high dielectric constant layer 58 diffusion barrier properties of the electrodes is particularly important.
- the electrode layer or electrode stack must act as an effective barrier to the diffusion of silicon, particularly due to the processes used to form the high dielectric constant materials.
- Such diffusion barrier properties are required when the substrate assembly 52 includes a silicon-containing surface 53 upon which the capacitor is formed, e.g., polysilicon, silicon substrate material, N-doped silicon, P-doped silicon, etc., since oxidation of the diffused silicon may result in degraded capacitance, e.g., capacitance for a memory device.
- the electrode stack must act as an oxygen barrier to protect the silicon-containing surface under the stack from oxidizing. The formation of the RuSi x diffusion barrier layer enhances the barrier properties of the stack.
- stack electrode 56 includes one or more RuSi x diffusion barrier layers and one or more additional conductive layers such as described with reference to Figure 3.
- CMOS devices complementary metal-oxide-semiconductor devices
- memory devices e.g., RAM
- logic devices e.g., CMOS
- the RuSi y diffusion barrier layer may be used for any application requiring diffusion barrier characteristics, particularly those for preventing diffusion of silicon and/or oxygen into adjacent layers.
- a device structure 100 is fabricated in accordance with conventional processing techniques through the formation of an opening 184 prior to depositing a bottom electrode structure 187 on the surface 185, e.g., a silicon containing surface, and surface 186 defining the opening 184.
- a bottom electrode stack 187 including a RuSi x diffusion barrier layer and one or more other conductive layers is formed in opening 184 according to the present invention as previously described herein.
- the substrate assembly 181 may include various elements, such as field oxide regions, active regions, i.e., those regions of a silicon substrate not covered by field oxide, word lines, field effect transistors (FET), source/drain regions created in the silicon substrate, etc.
- An insulative layer of oxide material 183 is formed over the substrate assembly.
- the opening 184 in the insulative layer 183 is a small high aspect ratio opening.
- small high aspect ratio openings have feature sizes or critical dimensions below about 1 micron (e.g., such as a diameter or width of an opening being less than about 1 micron) and aspect ratios greater than about 1.
- Such aspect ratios are applicable to contact holes, vias, trenches, and any other configured openings.
- a trench having an opening of 1 micron and depth of 3 microns has an aspect ratio of 3.
- the present invention is particularly beneficial for forming diffusion barrier layers in small high aspect ratio features due to the use of CVD processes for forming conformal RuSi x diffusion barrier layers over step structures.
- a stack electrode 187 including a RuSi x diffusion barrier layer is formed on the bottom surface 185 and the one or more side walls 186 defining opening 184.
- the electrode stack layers are formed over the entire structure including the bottom surface 185 and sidewalls 186. Then, the layers are formed into lower electrode 187. For example, the stack layers may be etched or planarized to remove the desired regions for forming the bottom electrode 187. Thereafter, dielectric layer 191 is then formed relative to the stack electrode 187. Further thereafter, the second electrode 192 is formed relative to the dielectric material 191.
- such an electrode may be of any conductive material such as tungsten nitride, titanium nitride, tantalum nitride, ruthenium, rhodium, iridium, ruthenium oxide, iridium oxide, any combination thereof, or any other conductive material typically used as an electrode or electrode layer of a storage cell capacitor.
- the bottom electrode formed of a stack of layers including a RuSi x diffusion barrier layer is conformally formed of uniform thickness using CVD processes as described herein within opening 184.
- the RuSi x diffusion barrier layer provides suitable barrier properties.
- container capacitors typically include electrodes formed on surfaces requiring conformal formation of a bottom electrode.
- Such a container capacitor storage cell is described in U.S. Patent No. 5,270,241 to Dennison, et al., entitled “Optimized Container Stack Capacitor DRAM Cell Utilizing Sacrificial Oxide Deposition and Chemical Mechanical Polishing,” issued December 14, 1993.
- device structure 200 is fabricated in accordance with conventional processing techniques through the formation of contact opening 259 prior to metalization of the contact area 255 of substrate 207.
- the device structure 200 prior to metalization, includes field oxide regions 205 and active areas, i.e., those regions of substrate 207 not covered by field oxide. Formed relative to the field oxide regions 205 in the active areas are word line 221 and FET 222.
- doped source/drain regions 225, 230 are formed as known to one skilled in the art.
- a conformal layer of oxide material 240 is formed thereover and contact opening 259 is defined therein to the contact area 255 of doped region 230 of silicon substrate 207.
- contact opening 259 for providing electrical connection to substrate region 230.
- various materials may be formed in contact opening 259, such as titanium nitride or other diffusion barrier materials.
- contact liner 285 is a RuSi x diffusion barrier layer formed according to the present invention on bottom surface 260 and the one or more side walls 261 defining the opening 259.
- the RuSi x diffusion barrier te r is generally deposited over the entire substrate assembly and then planarized to form the contact liner 285.
- Example 1 Figure 7 A shows a depth profile of a sample wafer including a platinum layer having a thickness of about 500 A formed on a RuSi x diffusion barrier layer.
- the RuSi x diffusion barrier layer is formed by annealing a layer of ruthenium having a thickness of about 100 A deposited on a silicon substrate. The anneal is performed at about 500° C for a time period of about 5 minutes.
- the depth profile is for the sample wafer after the structure has undergone rapid thermal oxidation at a temperature of about 850° C for a time period of about 30 seconds. There appears to be little if any silicon diffusion through the RuSi x diffusion barrier layer and therefore, no silicon dioxide formation or platinum silicidation.
- the reaction chamber used for fabricating the sample wafer was a CVD chamber manufactured by MDC Vaccuum Products Corp. (Hayward, CA) and the bubblers used are glass research bubblers from Technical Glass Service (Boise, ID).
- the conditions used for forming the ruthenium layer for use in attaining the RuSi x diffusion barrier layer include: Ruthenium Precursor: C 6 H 8 Ru(CO) 3 .
- Reaction Chamber Conditions pressure of 0.5 torr, deposition temperature of 300° C at wafer surface. Deposition Time: 1 minutes.
- the conditions used for the forming the platinum layer include:
- Platinum Bubbler Conditions pressure of 10 torr, temperature of 25° C.
- Reaction Chamber Conditions pressure of 5 torr, deposition temperature of 350° C at wafer surface.
- the depth profile was attained by using an XPS device available under the trade designation Phi ( ⁇ ) 5600 from Physical Electronics (Eden Prairie, MN).
- Sputtering was performed with a 3 keV Argon ion beam rastored over a 3 mm area.
- the sputter time for the depth profile of Figure 7A was 20 minutes.
- Figure 7B shows a depth profile of a sample wafer including a platinum layer having a thickness of 450 A formed over a ruthenium layer having a thickness of about 100 A formed directly on a silicon substrate without an annealing step to form the RuSi x diffusion barrier layer as was performed above with respect to Figure 7A.
- the depth profile is for the sample wafer after the structure has undergone rapid thermal oxidation at a temperature of about 850 ° C for a time period of 30 seconds.
- the ruthenium and platinum layers are formed in the same manner and conditions as described above with reference to Figure 7A. Further, the depth profiles were attained in the same manner as described above.
- Figure 7B shows the resistance of the platinum film to silicidation after the rapid thermal oxidation step.
Abstract
A method for use in the fabrication of integrated circuits includes providing a substrate assembly (11) having a surface (12). A diffusion barrier layer (13) is formed over at least a portion of the surface (12). The diffusion barrier layer (13) is formed of RuSix, where x is in the range of about 0.01 to about 10. The barrier layer may be formed by depositing RuSix by chemical vapor deposition or the barrier layer may be formed by forming a layer of ruthenium relative to a silicon containing region and performing an anneal to form RuSix from the layer of ruthenium and the silicon containing region. Capacitor electrodes, interconnects or other structures may be formed with such a diffusion barrier layer.
Description
RUTHENIUM SILICIDE DIFFUSION BARRIER LAYERS AND METHODS OF FORMING SAME
Field of the Invention The present invention relates to semiconductor devices and the fabrication thereof. More particularly, the present invention pertains to diffusion barrier layers.
Background of the Invention In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, etc., conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers in contact holes, vias, etc. In many applications, it is preferable that the materials used provide effective diffusion barrier characteristics.
For example, effective diffusion barrier characteristics are required for conductive materials used in the formation of storage cell capacitors of memory devices, e.g., DRAMs. As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices. One way to retain storage capacity of storage cell capacitors of the memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes. One or more layers of various conductive materials may be used as the electrode material. However, generally, one or more of the layers of the conductive materials used for the electrodes (particularly the bottom electrode of a cell capacitor) must have certain diffusion barrier properties, e.g., silicon diffusion barrier properties. Such properties are particularly required when high dielectric constant materials are used for the dielectric layer of ine storage v-eli
capacitor because of the processes used for forming such high dielectric materials, e.g., deposition of high dielectric materials usually occurs at high temperatures (generally greater than about 500° C) in an oxygen-containing atmosphere. Generally, various metals and metallic compounds, for example, metals such as platinum, and conductive metal oxides, such as ruthenium oxide, have been proposed as the electrodes or at least one of the layers of an electrode stack for use with high dielectric constant materials. However, reliable electrical connections should generally be constructed which do not diminish the beneficial properties of the high dielectric constant materials. For platinum or ruthenium oxide to function well as a bottom electrode or as one of the layers of an electrode stack, an effective barrier to the diffusion of silicon from the substrate or other silicon containing region to the top of the electrode needs to be provided. This is required since silicon at the surface of the electrode stack will tend to be oxidized during the oxygen anneal of the high dielectric constant materials, e.g, Ta^ or BaSrTiO3, which will result in a decreased series capacitance, thus degrading the storage capacity of the cell capacitor.
Platinum and ruthenium oxide, used alone as an electrode, are generally too permeable to silicon to be used as a bottom electrode of a storage cell capacitor formed on a silicon substrate region. Because of the permeability of such materials to silicon, typically platinum is used as a layer in an electrode stack which acts as the electrode as well as a diffusion barrier for integration of capacitors directly formed on silicon. For example, as described in the article "Novel High Temperature Multilayer Electrode-Barrier Structure for High Density Ferroelectric Memories" by H.D. Bhatt, et al., Appl. Phys. Letter. 71(5), 4 August 1997, the electrode barrier structure includes layers of platinum:rhodium alloy, in addition to platinum:rhodium oxide layers, to form electrodes with diffusion barrier properties. Such alloy layers are formed using physical vapor deposition (PVD) processing, e.g., reactive RF sputtering processes. Further, for example, the article entitled "(Ba, Sr)TiO3 Films
Prepared by Liquid Source Chemical Vapor Deposition on Ru Electrodes" by Kawahara et al., Jpn.J.Appl.Phvs.. Vol. 35 (1996) Pt. 1, No. 9B, pp. 4880-4885,
describes the use of ruthenium and ruthenium oxide for forming electrodes in conjunction with high dielectric constant materials.
Many storage cell capacitors are fabricated which include electrode layers that are formed by deposition of a conductive material within a small high aspect ratio opening. Typically, sputtering does not provide a sufficiently conformal layer adequate for formation of an electrode layer within such a small high aspect ratio opening.
In addition to the formation of capacitor electrodes, the formation of barrier layers for use in other applications, e.g., interconnect applications, is also desirable. For example, diffusion barriers are commonly used to prevent undesirable reactions in contact openings.
Summary of the Invention
To overcome the problems described above, RuSix diffusion barrier layers, along with structures incorporating such diffusion barrier layers and methods associated therewith, are described herein.
A method for use in the fabrication of integrated circuits according to the present invention includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to about 10.
In one embodiment of the method, the diffusion barrier layer is formed of RuSix, where x is in the range of about 1 to about 3, more preferably about 2. In another embodiment of the method, the barrier layer is formed by depositing RuSix by chemical vapor deposition. In an alternative embodiment, the barrier layer is formed by forming a layer of ruthenium relative to a silicon containing region and performing an anneal to form RuSix from the layer of ruthenium and the silicon containing region.
A method for use in the formation of a capacitor according to the present invention includes forming a first electrode on a portion of a substrate assembly. A high dielectric material is formed over at least a portion of the first electrode and a second electrode is formed over the high dielectric material. At least one
of the first and second electrodes includes a barrier layer formed of RuSix, where x is in the range of about 0.01 to about 10.
Another method according to the present invention for use in the formation of a capacitor includes providing a silicon containing region of a substrate assembly. A first electrode is formed on at least a portion of the silicon containing region of the substrate assembly. The first electrode includes a barrier layer of RuSix, where x is in the range of about 0.01 to about 10. A high dielectric material is formed over at least a portion of the first electrode and a second electrode is provided over the high dielectric material. In one embodiment of the method, the formation of the barrier layer includes forming a layer of ruthenium on at least a portion of the silicon containing region. Thereafter, the layer of ruthenium formed on the at least a portion of the silicon containing region is annealed resulting in the RuSix barrier layer. The layer of ruthenium may be deposited by chemical vapor deposition with a thickness of about 1 Oλ to about 300A.
In another embodiment of the method, one or more conductive layers are formed relative to the RuSix barrier layer. The one or more conductive layers are formed of at least one of a metal or a conductive metal oxide, e.g., formed from materials selected from the group of RuO2, RhO2, MoO2, IrO2, Ru, Rh, Pd, Pt, and Ir.
A semiconductor device structure according to the present invention includes a substrate assembly including a surface and a diffusion barrier layer over at least a portion of the surface. The diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to about 10. In one embodiment of the structure, at least a portion of the surface is a silicon containing surface and the structure includes one or more additional conductive layers over the diffusion barrier layer formed of at least one of a metal and a conductive metal oxide, e.g., formed from materials selected from the group of RuO2, RhO2, MoO2, IrO2, Ru, Rh, Pd, Pt, and Ir. A capacitor structure according to the present invention is also described.
The capacitor structure includes a first electrode, a high dielectric material on at least a portion of the first electrode, and a second electrode on the dielectric
material. At least one of the first and second electrode includes a diffusion barrier layer formed of RuSix, where x is in the range of about 0.01 to about 10.
An integrated circuit structure according to the present invention includes a substrate assembly including at least one active device and a silicon containing region. An interconnect is formed relative to the at least one active device and the silicon containing region. The interconnect includes a diffusion barrier layer on at least a portion of the silicon containing region. The diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to about 10.
Brief Description of the Drawings
The present invention will be better understood from reading the following description of illustrative embodiments with reference to the attached drawings, wherein below:
Figure 1 shows a device structure including a RuSix diffusion barrier layer according to the present invention.
Figures 2A-2C show one method of forming the RuSix diffusion barrier layer according to the present invention.
Figure 3 shows a structure including a RuSix diffusion barrier layer according to the present invention as part of a multiple conductive layer stack. Figure 4 is a structure showing a high dielectric capacitor including an electrode having a RuSix diffusion barrier layer according to the present invention.
Figure 5 illustrates the use of a RuSix diffusion barrier layer in a storage cell capacitor application. Figure 6 illustrates the use of a RuSix diffusion barrier layer in a contact application.
Figures 7A-7B show the results of a second example using a Pt/RuSix stack formed on silicon.
Detailed Description of the Embodiments
The present invention shall be described generally with reference to Figures 1-2. Thereafter, embodiments and illustrations of applications of the
present invention shall be described with reference to Figures 3-6 and an example shall be described with reference to Figure 7.
Figure 1 illustrates a structure 10 including a substrate assembly 11 and a RuSix diffusion barrier layer 13 according to the present invention formed on a surface 12 of the substrate assembly 11, e.g., a silicon containing surface. The structure 10 further includes another conductive layer 14. The structure 10 is illustrative of the use of a RuSix diffusion barrier layer for any application requiring an effective barrier layer, for example, to prevent diffusion from a silicon containing surface. In other words, the RuSix diffusion barrier layer 13 may be used in the fabrication of semiconductor devices wherever it is necessary to prevent the diffusion of one material to an adjacent material. For example, the substrate assembly 11 may be representative of a contact structure having an opening extending to a silicon containing surface. In such a structure, diffusion barriers are commonly used in such openings to prevent undesirable reactions, such as the reaction of a conductive contact material, e.g, aluminum, with the silicon containing surface.
Further, for example, the RuSix diffusion barrier layer 13 may be used in the formation of storage cell capacitors for use in semiconductor devices, e.g., memory devices. As further described herein, the RuSix diffusion barrier layer is used within a stack of layers forming an electrode of a capacitor, e.g., the other layers including layers formed of materials such as platinum, ruthenium oxide, etc. One skilled in the art will recognize that various semiconductor processes and structures for various devices, e.g., CMOS devices, memory devices, etc., would benefit from the barrier characteristics of the barrier layers of the present invention and in no manner is the present invention limited to the illustrative embodiments described herein.
As used in this application, "substrate assembly" refers to either a semiconductor substrate such as the base semiconductor layer, e.g., the lowest layer of a silicon material in a wafer, or a silicon layer deposited on another material, such as silicon on sapphire, or a semiconductor substrate having one or more layers or structures formed thereon or regions formed therein. When reference is made to a substrate assembly in the following description, various process steps may have been previously used to form GJ define regions,
junctions, various structures or features, and openings such as vias, contact openings, high aspect ratio openings, etc.
The amount of silicon incorporated into the RuSix diffusion barrier layer 13 is sufficient to accomplish barrier characteristics for semiconductor devices, particularly for diffusion of silicon. Preferably, the RuSix diffusion barrier layer 13 according to the present invention includes an atomic composition such that x is in the range of about 0.01 to about 10. More preferably, x is in the range of about 1 to about 3, and yet more preferably, x is about 2.
The thickness of the RuSix diffusion barrier layer 13 is dependent upon the application for which it is used. Preferably, the thickness is in the range of about 10 A to about 300 A. More preferably, the thickness of the RuSix diffusion barrier layer 13 is in the range of about 50 A to about 200 A. For example, this preferred thickness range of about 50 A to about 200 A is applicable to a RuSix diffusion barrier layer used for forming a bottom electrode stack of a capacitor structure.
In the general illustration of Figure 1, the conductive layer 14 is representative of a single layer or one or more layers. For example, the conductive layer may include one or more layers formed of a metal or metal oxide, or combinations thereof. For example, such layers may include one of RuO2, MoO2, Rh, RhO2, IrO2, Ru, Pt, Pd and Ir, such as in the use of the RuSix diffusion barrier layer in an electrode stack. Further, for example, the conductive layer 14 may be a contact material such as aluminum when the RuSix diffusion barrier layer is used in a contact or interconnect application. Such conductive layers may be formed by any method known to those skilled in the art. The present invention is in no manner limited to any particular conductive layer or method for forming such conductive layers.
The RuSix diffusion barrier layer 13 may be formed by one or more various processes. For example, the formation of the RuSix diffusion barrier layer may be sputter deposited from a deposition target of RuSix, may be deposited by the sputtering from a deposition target of ruthenium onto a silicon containing surface followed by an anneal, and may be deposited by chemical vapor deposition (CVD) using a ruthenium precursor and a silicon precursor, for example, such as atmospheric pressure chemical vaocr deposition, low pressure
chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or any other chemical vapor deposition technique. Further, the RuSix diffusion barrier layer may be formed by depositing a layer of ruthenium using CVD onto a silicon containing surface followed by an annealing process. Preferably, the formation of the RuSix diffusion barrier layer is attained with the use of CVD.
Such a CVD process may be carried out in a chemical vapor deposition reactor, such as a reaction chamber available under the trade designation of 7000 from Genus, Inc., (Sunnyvale, CA), a reaction chamber available under the trade designation of 5000 from Applied Materials, Inc., (Santa Clara, CA), or a reaction chamber available under the trade designation of Prism from Novelus, Inc., (San Jose, CA). However, any reaction chamber suitable for performing CVD may be used.
Chemical vapor deposition (CVD) is defined as the formation of a non- volatile solid film on a substrate by the reaction of vapor phase reactants, i.e., reactant gases, that contain desired components. The reactant gases are introduced into the reaction chamber. The gases decompose and react at a heated wafer surface to form the desired layer. Chemical vapor deposition is just one process of providing thin layers on semiconductor wafers, such as films of elemental metals or compounds, e.g., platinum, ruthenium oxide, iridium, molybdenum oxide, etc. Chemical vapor deposition processes are favored in many respects because of the process capability to provide highly conformal layers even within deep contacts and other openings. Thus, as described further below with reference to Figures 5 and 6, CVD processing is preferably used to provide highly conformal layers within deep contacts and other openings such as for lower electrodes of storage cell capacitors. It will be readily apparent to one skilled in the art that although CVD is the preferred process, that the CVD process may be enhanced by various related techniques such as plasma assistance, photo assistance, laser assistance, as well as other techniques. One preferred method of forming the RuSix diffusion barrier layer 13 is by depositing RuSix by chemical vapor deposition (CVD). The CVD process is conducted with a ruthenium precursor being delivered to a reaction chamber along with a silicon precursor.
The ruthenium precursor is generally a liquid precursor. The ruthenium precursor is contained in a bubbler reservoir through which a carrier gas, such as helium or any other inert gas, i.e., a gas that is nonreactive with other gases of the process (e.g., nitrogen, argon, neon, and xenon), is bubbled through the reservoir containing the precursor to deliver the precursor to the reaction chamber. For example, a carrier gas having a flow in the range of about one seem to about 500 seem may be used in a bubbler having a pressure in the range of about 0.5 torr to about 50 torr and a temperature in the range of about 30° C to about 70° C to deliver a ruthenium precursor to the reaction chamber. Any ruthenium containing precursor may be used in accordance with the present invention. Preferably, the ruthenium precursors are liquid ruthenium complexes of the following formula (Formula I): (diene)Ru(CO)3 wherein: "diene" refers to linear, branched, or cyclic dienes, bicyclic dienes, tricyclic dienes, fluorinated derivatives thereof, combinations thereof, and derivatives thereof additionally containing heteroatoms such as halide, Si, S, Se, P, As, or N. These precursor complexes and others are described in Assignees' copending patent application entitled "Precursor Chemistries for Chemical Vapor
Deposition of Ruthenium and Ruthenium Oxide" having U.S. Serial No. (Micron Docket No. 97-0675) and in Assignees' copending patent application entitled "Methods for Preparing Ruthenium and Osmium
Compounds" having U.S. Serial No. (Micron Docket No. 97-
0861). Further, for example, additional precursors and methods of depositing ruthenium layers are generally discussed in U.S. Patent No. 5,372,849 to McCormick et al. More preferably, the ruthenium precursors used according to the present invention include one of C6HgRu(CO)3, bis(cyclopentadienyl) ruthenium (II), triruthenium dodecacarbonyl, and cyclopentadienyl dicarbonyl ruthenium (II) dimer.
The silicon precursor is also provided to the reaction chamber. For example, the silicon precursor may include a silicon hydride or silane such as dichlorosilane (DCS, SiH2Cl2), silane (SiH4), disilane (H3SiSiH3), trichlorosilane
(TCS, SiHCl3), or any other silicon precursor as would be recongnized by one skilled in the art. For example, the silicon precursor may be provided to the reaction chamber at a rate in the range of about 5 seem to about 500 seem. Preferably, the rate is about 100 seem. One skilled in the art will recognize that the manner in which the gases are introduced into the reaction chamber may include one of various techniques. For example, in addition to provision by bubbler techniques, the introduction may be accomplished with the use of compounds which are gases at room temperature or by heating a volatile compound and delivering the volatile compound to the reaction chamber using a carrier gas. Further, solid precursors and various methods of vaporizing such solid precursors may also be used for introduction of reactant compounds into the chamber. As such, the present invention is not limited to any particular technique. Further, typically, the reactant gases are admitted at separate inlet ports. In addition to the other gases provided to the reaction chamber, an optional dilution gas (i.e., a gas that is non- reactive with the reactant gases) may also be introduced into the chamber such as to change the concentrations of the gases therein. For example, argon gas may be introduced into the chamber at a varied flow rate.
Therefore, in accordance with one method of forming the RuSix diffusion barrier layer, the ruthenium precursor gas, the silicon precursor gas, and optionally a dilution gas is provided to the reaction chamber. In this preferred CVD process, the reaction chamber pressure is preferably maintained at a deposition pressure of about 0.1 torr to about 10 torr. The deposition temperature at the wafer surface upon which the RuSix diffusion barrier layer 13 is deposited is preferably held at a temperature in a range of about 100° C to about 700° C, more preferably in the range of about 200° C to about 500° C.
Another preferred method of forming a RuSix diffusion barrier layer 19 according to the present invention is shown in Figures 2A-2C. This method forms the RuSix diffusion barrier layer 19 by depositing a layer of ruthenium 18 as shown in Figure 2A onto a silicon containing region of substrate assembly 16 using CVD. The deposition of the ruthenium layer 18 is then followed by an annealing process to react the silicon containing region having silicon containing surface 17 with the ruthenium layer 18 to form the R.uSix diffusion barrier layer
19 as shown in Figure 2B. Thereafter, a conductive layer 21 (e.g., one or more conductive layers like conductive layer 14 of Figure 1) is formed on the RuSix diffusion barrier layer 19.
The CVD process for depositing the ruthenium layer 18 is preferably conducted with a ruthenium precursor being delivered to a reaction chamber in generally the same manner as described above with regard to the deposition of RuSix. As described therein, the ruthenium precursor is generally a liquid precursor. The ruthenium precursor is contained in a bubbler reservoir through which a carrier gas, such as helium or any other inert gas, i.e., a gas that is nonreactive with other gases of the process (e.g., nitrogen, argon, neon, and xenon), is bubbled through the reservoir containing the precursor to deliver the precursor to the reaction chamber. As described above, any ruthenium- containing precursor may be used in accordance with the present invention.
Therefore, in accordance with this method of forming the RuSix diffusion barrier layer, the ruthenium precursor gas and optionally a dilution gas is provided to the reaction chamber. In this particular preferred CVD process, the reaction chamber pressure is preferably maintained at a deposition pressure of about 0.1 torr to about 10 torr. The deposition temperature at the wafer surface upon which the ruthenium layer 18 is deposited is preferably held at a temperature in a range of about 100° C to about 700° C, more preferably in the range of about 200° C to about 500° C.
After the ruthenium layer 18 is conformally deposited using CVD, an annealing process is performed to form the RuSix diffusion barrier layer 19 from the ruthenium layer 18 and the silicon containing region of substrate assembly 16. The annealing process is preferably performed in situ in the reaction chamber in a nitrogen atmosphere, although any other nonreactive atmosphere may be used, e.g., argon. Preferably, the annealing temperature is within the range of about 400° C to about 1000° C, more preferably about 500° C. The anneal is preferably performed for a time period of about 0.5 minutes to about 60 minutes. One skilled in the art will recognize that such temperatures and time periods may vary and that the anneal parameters should be sufficient to convert the ruthenium layer 18 into RuSix 19, where x is in the ranges as previously described herein. For example, furnace anneals and rapid thermal annealing may
be used, and further, such anneals may be performed in one or more annealing steps. Likewise, it may not be necessary to convert the entire ruthenium layer to RuSix as long as sufficient barrier properties are attained with the amount of ruthenium converted. The ruthenium layer 18 deposited for forming the RuSix diffusion barrier layer 19 is preferably of a thickness in the range of about 10 A to about 300 A. More preferably, the thickness is in the range is about 50 A to about of 200 A; and even more preferably the thickness is about 100 A.
Figure 3 shows a structure 20 including substrate assembly 22, e.g., a silicon substrate region, and a stack 24. The stack 24 includes conductive layers 31-34. One or more of the conductive layers 31-34 are RuSix diffusion barrier layers according to the present invention.
The one or more conductive layers, in addition to including one or more RuSix diffusion barrier layers, may include conductive layers formed of various conductive materials. For example, the conductive layers may include, but are clearly not limited to, preferably layers formed of metals, metal oxides or combinations thereof. For example, such layers may include metals such as rhodium, palladium, ruthenium, platinum, and iridium or metal oxides such as ruthenium oxide, molybdenum oxide and iridium oxide. The stack 24 may be used for one or more numerous applications, e.g., interconnection applications, capacitor applications, etc. For example, stack 24 may be used as an electrode for a storage cell capacitor with substrate assembly 22 including a silicon containing surface 23. As such, the barrier properties of the stack 24 prevent silicon diffusion from silicon-containing surface 23. In accordance with the present invention, the layer 31 may be formed as the RuSix diffusion barrier layer to prevent diffusion of silicon from silicon-containing surface 23 through stack 24 to adjacent layer or layers 29 or to the surface of the stack 24, as well as preventing oxygen diffusion to the silicon-containing surface. Figure 4 shows a structure 50 including substrate assembly 52, e.g., a silicon substrate, and capacitor structure 54 formed relative thereto. Capacitor structure 54 includes a first electrode 56, a second electrode 60, and a high dielectric constant layer 58 interposed therebetween. For example, the dielectric
layer may be any suitable material having a desirable dielectric constant, such as TaA, Ba^r^TiO, [BST], BaTiO3, SrTiO3, PbTiO3, Pb(Zr,Ti)O3 [PZT], (Pb,La)(Zr,Ti)O3 [PLZT], (Pb,La)TiO3 [PLT], KNO3, and LiNbO3. With use of the high dielectric constant layer 58, diffusion barrier properties of the electrodes is particularly important. For example, to function well in a bottom electrode of a capacitor structure, the electrode layer or electrode stack must act as an effective barrier to the diffusion of silicon, particularly due to the processes used to form the high dielectric constant materials. Such diffusion barrier properties are required when the substrate assembly 52 includes a silicon-containing surface 53 upon which the capacitor is formed, e.g., polysilicon, silicon substrate material, N-doped silicon, P-doped silicon, etc., since oxidation of the diffused silicon may result in degraded capacitance, e.g., capacitance for a memory device. In addition, the electrode stack must act as an oxygen barrier to protect the silicon-containing surface under the stack from oxidizing. The formation of the RuSix diffusion barrier layer enhances the barrier properties of the stack.
One skilled in the art will recognize that stack electrode 56 includes one or more RuSix diffusion barrier layers and one or more additional conductive layers such as described with reference to Figure 3.
Two illustrations of using the RuSix diffusion barrier layer as described above are shown and described below with reference to Figures 5 and 6. The use of the RuSix diffusion barrier layer according to the present invention is described with reference to Figure 5 wherein a bottom electrode of a high dielectric capacitor of a storage cell includes one or more RuSix diffusion barrier layers as described herein. Further, the use of RuSix diffusion barrier layers according to the present invention is described with reference to Figure 6 wherein a contact liner requiring diffusion barrier characteristics is described. For simplistic purposes, the illustrative descriptions are limited to the use of the RuSix diffusion barrier layers described in these two illustrative structures. There are other semiconductor processes and structures for various devices, e.g., CMOS devices, memory devices, logic devices, etc., that would benefit from the present invention and in no manner is the present invention limited to the illustrative embodiments described herein, e g., contact liner and electrode structure. The RuSiy diffusion barrier layer may be used for any application
requiring diffusion barrier characteristics, particularly those for preventing diffusion of silicon and/or oxygen into adjacent layers.
As shown in Figure 5, a device structure 100 is fabricated in accordance with conventional processing techniques through the formation of an opening 184 prior to depositing a bottom electrode structure 187 on the surface 185, e.g., a silicon containing surface, and surface 186 defining the opening 184. A bottom electrode stack 187 including a RuSix diffusion barrier layer and one or more other conductive layers is formed in opening 184 according to the present invention as previously described herein. The substrate assembly 181 may include various elements, such as field oxide regions, active regions, i.e., those regions of a silicon substrate not covered by field oxide, word lines, field effect transistors (FET), source/drain regions created in the silicon substrate, etc. An insulative layer of oxide material 183 is formed over the substrate assembly. The opening 184 in the insulative layer 183 is a small high aspect ratio opening. As described herein, small high aspect ratio openings have feature sizes or critical dimensions below about 1 micron (e.g., such as a diameter or width of an opening being less than about 1 micron) and aspect ratios greater than about 1. Such aspect ratios are applicable to contact holes, vias, trenches, and any other configured openings. For example, a trench having an opening of 1 micron and depth of 3 microns has an aspect ratio of 3. The present invention is particularly beneficial for forming diffusion barrier layers in small high aspect ratio features due to the use of CVD processes for forming conformal RuSix diffusion barrier layers over step structures.
As shown in Figure 5, a stack electrode 187 including a RuSix diffusion barrier layer is formed on the bottom surface 185 and the one or more side walls 186 defining opening 184. The electrode stack layers are formed over the entire structure including the bottom surface 185 and sidewalls 186. Then, the layers are formed into lower electrode 187. For example, the stack layers may be etched or planarized to remove the desired regions for forming the bottom electrode 187. Thereafter, dielectric layer 191 is then formed relative to the stack electrode 187. Further thereafter, the second electrode 192 is formed relative to the dielectric material 191. For example, such an electrode may be of any conductive material such as tungsten nitride, titanium nitride, tantalum
nitride, ruthenium, rhodium, iridium, ruthenium oxide, iridium oxide, any combination thereof, or any other conductive material typically used as an electrode or electrode layer of a storage cell capacitor. With use of the present invention, the bottom electrode formed of a stack of layers including a RuSix diffusion barrier layer is conformally formed of uniform thickness using CVD processes as described herein within opening 184. The RuSix diffusion barrier layer provides suitable barrier properties.
It will be recognized by one skilled in the art that any capacitor formed relative to a surface, e.g., silicon containing surface, whereupon diffusion barrier properties are required and/or conformally formed conductive layers are required will benefit from the present invention. For example, container capacitors typically include electrodes formed on surfaces requiring conformal formation of a bottom electrode. Such a container capacitor storage cell is described in U.S. Patent No. 5,270,241 to Dennison, et al., entitled "Optimized Container Stack Capacitor DRAM Cell Utilizing Sacrificial Oxide Deposition and Chemical Mechanical Polishing," issued December 14, 1993.
As shown in Figure 6, device structure 200 is fabricated in accordance with conventional processing techniques through the formation of contact opening 259 prior to metalization of the contact area 255 of substrate 207. As such, prior to metalization, the device structure 200 includes field oxide regions 205 and active areas, i.e., those regions of substrate 207 not covered by field oxide. Formed relative to the field oxide regions 205 in the active areas are word line 221 and FET 222. Suitably doped source/drain regions 225, 230 are formed as known to one skilled in the art. A conformal layer of oxide material 240 is formed thereover and contact opening 259 is defined therein to the contact area 255 of doped region 230 of silicon substrate 207. Thereafter, one or more metalization or conductive layers are formed in the contact opening 259 for providing electrical connection to substrate region 230. For example, various materials may be formed in contact opening 259, such as titanium nitride or other diffusion barrier materials. Preferably, contact liner 285 is a RuSix diffusion barrier layer formed according to the present invention on bottom surface 260 and the one or more side walls 261 defining the opening 259. The RuSix diffusion barrier te r is generally deposited over the entire substrate
assembly and then planarized to form the contact liner 285. Thereafter, a conductive material 276, e.g., aluminum, is formed in the contact opening for providing connection to doped region 230 of substrate 207.
Example 1 Figure 7 A shows a depth profile of a sample wafer including a platinum layer having a thickness of about 500 A formed on a RuSix diffusion barrier layer. The RuSix diffusion barrier layer is formed by annealing a layer of ruthenium having a thickness of about 100 A deposited on a silicon substrate. The anneal is performed at about 500° C for a time period of about 5 minutes. The depth profile is for the sample wafer after the structure has undergone rapid thermal oxidation at a temperature of about 850° C for a time period of about 30 seconds. There appears to be little if any silicon diffusion through the RuSix diffusion barrier layer and therefore, no silicon dioxide formation or platinum silicidation. The reaction chamber used for fabricating the sample wafer was a CVD chamber manufactured by MDC Vaccuum Products Corp. (Hayward, CA) and the bubblers used are glass research bubblers from Technical Glass Service (Boise, ID). The conditions used for forming the ruthenium layer for use in attaining the RuSix diffusion barrier layer include: Ruthenium Precursor: C6H8Ru(CO)3.
Ruthenium Carrier Gas for use through Bubbler: 5 seem of helium.
Ruthenium Bubbler Conditions: pressure of 3 torr, temperature of 25° C.
Reaction Chamber Conditions: pressure of 0.5 torr, deposition temperature of 300° C at wafer surface. Deposition Time: 1 minutes.
The conditions used for the forming the platinum layer include:
Platinum Precursor: (methylcyclopentadienyl)PtMe3
Platinum Carrier Gas for use through Bubbler: 10 seem of helium.
Platinum Bubbler Conditions: pressure of 10 torr, temperature of 25° C. Reaction Chamber Conditions: pressure of 5 torr, deposition temperature of 350° C at wafer surface.
Deposition Time: 6 minutes.
The depth profile was attained by using an XPS device available under the trade designation Phi (Φ) 5600 from Physical Electronics (Eden Prairie, MN). The operating conditions for obtaining the profile include x-ray source of 350 W, monochromatic Al kα(hV = 1486.6 eV); 45 degree extraction; 800 μm extraction aperture. Sputtering was performed with a 3 keV Argon ion beam rastored over a 3 mm area. The sputter time for the depth profile of Figure 7A was 20 minutes.
Figure 7B shows a depth profile of a sample wafer including a platinum layer having a thickness of 450 A formed over a ruthenium layer having a thickness of about 100 A formed directly on a silicon substrate without an annealing step to form the RuSix diffusion barrier layer as was performed above with respect to Figure 7A. The depth profile is for the sample wafer after the structure has undergone rapid thermal oxidation at a temperature of about 850 ° C for a time period of 30 seconds. The ruthenium and platinum layers are formed in the same manner and conditions as described above with reference to Figure 7A. Further, the depth profiles were attained in the same manner as described above.
In comparing Figures 7A and 7B, it is shown in Figure 7B that without the RuSix diffusion barrier layer the platinum is fully suicided and forms silicon dioxide at the surface. On the other hand, Figure 7A shows the resistance of the platinum film to silicidation after the rapid thermal oxidation step.
All patents and references cited herein are incorporated in their entirety as if each were incorporated separately. This invention has been described with reference to illustrative embodiments and is not meant to be construed in a limiting sense. As described previously, one skilled in the art will recognize that various other illustrative applications may use the RuSix diffusion barrier layer as described herein to take advantage of the beneficial barrier characteristics thereof. Various modifications of the illustrative embodiments, as well as additional embodiments to the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments that may fall within the scope of the present invention as defined by the accompanying claims.
Claims
1. A method for use in the fabrication of integrated circuits, the method comprising: providing a substrate assembly having a surface; and forming a diffusion barrier layer over at least a portion of the surface, wherein the diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to about 10.
2. The method of claim 1, wherein x is in the range of about 1 to about 3.
3. The method of claim 2, wherein x is about 2.
4. The method of claim 1, wherein forming the barrier layer includes depositing RuSix by chemical vapor deposition.
5. The method of claim 1, wherein forming the barrier layer includes: forming a layer of ruthenium relative to a silicon containing region; and performing an anneal to form RuSix from the layer of ruthenium and the silicon containing region.
6. The method of claim 5, wherein forming the layer of ruthenium includes depositing the layer of ruthenium by chemical vapor deposition.
7. The method of claim 1 , wherein the method further includes forming at least one additional conductive material over the diffusion barrier layer, the at least one additional conductive material selected from a group of a metal and a conductive metal oxide.
8. The method of claim 5, wherein performing the anneal to form RuSix includes performing an anneal at a temperature in the range of about 400┬░ C to about 1000┬░ C for about 0.5 minutes to about 60 minutes in an inert gas atmosphere.
9. The method of claim 8, wherein performing the anneal to form RuSix includes annealing the layer of ruthenium and the silicon containing layer at a temperature of about 500┬░ C for about 5 minutes in a nitrogen atmosphere.
10. The method of claim 5, wherein silicon containing region includes the at least a portion of the surface.
11. A method for use in the formation of a capacitor, the method comprising: forming a first electrode on a portion of a substrate assembly; forming a high dielectric material over at least a portion of the first electrode; and forming a second electrode over the high dielectric material, wherein at least one of the first and second electrodes comprises a barrier layer formed of RuSix, where x is in the range of about 0.01 to about 10.
12. The method of claim 11, wherein x is in the range of about 1 to about 3.
13. The method of claim 12, wherein x is about 2.0.
14. The method of claim 11 , wherein the barrier layer is formed by chemical vapor deposition.
15. A method for use in the formation of a capacitor, the method comprising: providing a silicon containing region of a substrate assembly; forming a first electrode on at least a portion of the silicon containing region of the substrate assembly, the first electrode comprising a barrier layer of RuSix, where x is in the range of about 0.01 to about 10; providing a high dielectric material over at least a portion of the first electrode; and providing a second electrode over the high dielectric material.
16. The method of claim 15, wherein x is in the range of about 1 to about 3.
17. The method of claim 15 , wherein forming the barrier layer includes: forming a layer of ruthenium on the at least a portion of the silicon containing region; and annealing the layer of ruthenium formed on the at least a portion of the silicon containing region resulting in the RuSix barrier layer.
18. The method of claim 17, wherein forming the layer of ruthenium includes depositing the layer of ruthenium by chemical vapor deposition, the layer of ruthenium having a thickness of about 10A to about 300A.
19. The method of claim 18, wherein the layer of ruthenium has a thickness of about 50A to about 20θΛ.
20. The method of claim 19, wherein the layer of ruthenium has a thickness of about lOOA.
21. The method of claim 18, wherein annealing the layer of ruthenium formed on the at least a portion of the silicon containing region includes annealing at a temperature in the range of about 400┬░ C to about 1000┬░ C for about 0.5 minutes to about 60 minutes in an inert gas atmosphere.
22. The method of claim 15, wherein the RuSix barrier layer is formed by chemical vapor deposition using a ruthenium precursor and a silicon precursor.
23. A method for use in the formation of a capacitor, the method comprising: providing a silicon containing region of a substrate assembly; forming a first electrode on at least a portion of the silicon containing region of the substrate assembly, the forming of the first electrode comprising: forming a barrier layer of RuSix , where x is in the range of about 0.01 to about 10, and forming one or more conductive layers relative to the RuSix barrier layer, the one or more conductive layers formed of at least one of a metal or a conductive metai oxide; providing a high dielectric material over at least a portion of the first electrode; and providing a second electrode over the high dielectric material.
24. The method of claim 23, wherein the one or more conductive layers are formed from materials selected from the group of RuO2, RhO2, MoO2, IrO2, Ru, Rh, Pd, Pt, and Ir.
25. The method of claim 23, wherein forming the barrier layer includes: forming a layer of ruthenium on the at least a portion of the silicon containing region; and annealing the layer of ruthenium formed on the at least a portion of the silicon containing region resulting in the RuSix barrier layer.
26. The method of claim 23, wherein the RuSix barrier layer is formed by chemical vapor deposition using a ruthenium precursor and a silicon precursor.
27. A semiconductor device structure, the structure comprising: a substrate assembly including a surface; and a diffusion barrier layer over at least a portion of the surface, wherein the diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to about 10.
28. The structure of claim 27, wherein x is in the range of about 1 to about 3.
29. The structure of claim 28, wherein x is about 2.0.
30. The structure of claim 23, wherein the at least a portion of the surface is a silicon containing surface and further wherein the structure includes one or more additional conductive layers over the diffusion barrier layer formed of at least one of a metal and a conductive metal oxide.
31. The structure of claim 30, wherein the one or more conductive layers are formed from materials selected from the group of RuO2, RhO2, MoO2, IrO2, Ru, Rh, Pd, Pt, and Ir.
32. A capacitor structure comprising: a first electrode; a high dielectric material on at least a portion of the first electrode; and a second electrode on the dielectric material, wherein at least one of the first and second electrode comprises a diffusion barrier layer formed of RuSix, where x is in the range of about 0.01 to about 10.
33. The structure of claim 32, wherein x is in the range of about 1 to about 3.
34. The structure of claim 32, wherein the diffusion barrier layer of the first electrode is formed on at least a portion of a silicon containing region and further wherein the structure includes one or more additional conductive layers over the diffusion barrier layer formed of at least one of a metal and a conductive metal oxide.
35. The structure of claim 34, wherein the one or more additional conductive layers are formed from materials selected from the group of RuO2, RhO2, MoO2, IrO2, Ru, Pt, and Ir.
36. A integrated circuit structure comprising: a substrate assembly including at least one active device and a silicon containing region; and an interconnect formed relative to the at least one active device and the silicon containing region, the interconnect including a diffusion barrier layer on at least a portion of the silicon containing region, wherein the diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to about 10.
37. The structure of claim 36, wherein x is in the range of about 1 to about 3.
38. The structure of claim 36, further comprising a conductive contact material formed relative to the diffusion barrier layer.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP99939124A EP1114449B1 (en) | 1998-08-27 | 1999-08-10 | Method for forming a capacitor with a ruthenium silicide diffusion barrier layer |
| DE69940640T DE69940640D1 (en) | 1998-08-27 | 1999-08-10 | HE DIFFUSION BARRIER LAYER OF RUTHENIUM SILICIDE |
| AU53467/99A AU5346799A (en) | 1998-08-27 | 1999-08-10 | Ruthenium silicide diffusion barrier layers and methods of forming same |
| KR1020017002545A KR20010073044A (en) | 1998-08-27 | 1999-08-10 | Ruthenium silicide diffusion barrier layers and method of forming same |
| JP2000568108A JP4719358B2 (en) | 1998-08-27 | 1999-08-10 | Capacitor manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/141,240 | 1998-08-27 | ||
| US09/141,240 US6197628B1 (en) | 1998-08-27 | 1998-08-27 | Ruthenium silicide diffusion barrier layers and methods of forming same |
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| WO2000013215A1 true WO2000013215A1 (en) | 2000-03-09 |
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| PCT/US1999/018114 WO2000013215A1 (en) | 1998-08-27 | 1999-08-10 | Ruthenium silicide diffusion barrier layers and methods of forming same |
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| US (3) | US6197628B1 (en) |
| EP (1) | EP1114449B1 (en) |
| JP (1) | JP4719358B2 (en) |
| KR (2) | KR20050048625A (en) |
| AT (1) | ATE426915T1 (en) |
| AU (1) | AU5346799A (en) |
| DE (1) | DE69940640D1 (en) |
| MY (1) | MY132400A (en) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002067302A2 (en) * | 2001-02-20 | 2002-08-29 | Micron Technology, Inc. | Rhodium-rich oxygen barriers |
| WO2002071447A2 (en) * | 2001-03-05 | 2002-09-12 | Micron Technology, Inc. | Ruthenium silicide wet etch |
Families Citing this family (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6197628B1 (en) * | 1998-08-27 | 2001-03-06 | Micron Technology, Inc. | Ruthenium silicide diffusion barrier layers and methods of forming same |
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Also Published As
| Publication number | Publication date |
|---|---|
| KR20010073044A (en) | 2001-07-31 |
| TW436957B (en) | 2001-05-28 |
| AU5346799A (en) | 2000-03-21 |
| DE69940640D1 (en) | 2009-05-07 |
| JP4719358B2 (en) | 2011-07-06 |
| US7560815B1 (en) | 2009-07-14 |
| US6197628B1 (en) | 2001-03-06 |
| JP2002524847A (en) | 2002-08-06 |
| ATE426915T1 (en) | 2009-04-15 |
| EP1114449B1 (en) | 2009-03-25 |
| KR20050048625A (en) | 2005-05-24 |
| MY132400A (en) | 2007-10-31 |
| EP1114449A1 (en) | 2001-07-11 |
| US8461682B2 (en) | 2013-06-11 |
| US20090278232A1 (en) | 2009-11-12 |
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