WO2000019343A3 - Block based design methodology - Google Patents

Block based design methodology Download PDF

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Publication number
WO2000019343A3
WO2000019343A3 PCT/US1999/022984 US9922984W WO0019343A3 WO 2000019343 A3 WO2000019343 A3 WO 2000019343A3 US 9922984 W US9922984 W US 9922984W WO 0019343 A3 WO0019343 A3 WO 0019343A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
designer
experience
circuit blocks
block based
Prior art date
Application number
PCT/US1999/022984
Other languages
French (fr)
Other versions
WO2000019343A2 (en
Inventor
Henry Chang
Larry Cooke
Merrill Hunt
Wuudiann Ke
Christopher K Lennard
Grant Martin
Peter Paterson
Khoan Truong
Kumar Venkatramani
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Priority to AU11005/00A priority Critical patent/AU1100500A/en
Priority to BR9914200-7A priority patent/BR9914200A/en
Priority to EEP200100189A priority patent/EE200100189A/en
Priority to IL14227999A priority patent/IL142279A0/en
Priority to HU0301274A priority patent/HUP0301274A2/en
Priority to EP99954722A priority patent/EP1145159A3/en
Priority to CA002345648A priority patent/CA2345648A1/en
Priority to JP2000572780A priority patent/JP2002526908A/en
Publication of WO2000019343A2 publication Critical patent/WO2000019343A2/en
Publication of WO2000019343A3 publication Critical patent/WO2000019343A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/08—Intellectual property [IP] blocks or IP cores

Abstract

A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
PCT/US1999/022984 1998-09-30 1999-09-30 Block based design methodology WO2000019343A2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
AU11005/00A AU1100500A (en) 1998-09-30 1999-09-30 Block based design methodology
BR9914200-7A BR9914200A (en) 1998-09-30 1999-09-30 Methods for designing a circuit system, for expanding an existing methodology for assessing the feasibility of a circuit design, for performing a feasibility assessment for a circuit design, for refining a first decision rule for a circuit design, to form a second decision rule for a circuit design, for organizing a designer's experience data for a plurality of pre-designed circuit blocks, for increasing glue logic distribution efficiency and for distributing a plurality of logic elements of glue between design blocks and distribute glue logic for execution in an integrated circuit device design scheme, to convert a circuit block-specific interface, to select a circuit collector, to design a device that incorporates the enable a device test to verify the correct operation of a and to develop a behavioral test bench, collar interface and interface system
EEP200100189A EE200100189A (en) 1998-09-30 1999-09-30 Block based development methodology
IL14227999A IL142279A0 (en) 1998-09-30 1999-09-30 Block based methodology
HU0301274A HUP0301274A2 (en) 1998-09-30 1999-09-30 Block based design methodology
EP99954722A EP1145159A3 (en) 1998-09-30 1999-09-30 Block based design methodology
CA002345648A CA2345648A1 (en) 1998-09-30 1999-09-30 Block based design methodology
JP2000572780A JP2002526908A (en) 1998-09-30 1999-09-30 Block-based design method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10256698P 1998-09-30 1998-09-30
US60/102,566 1998-09-30

Publications (2)

Publication Number Publication Date
WO2000019343A2 WO2000019343A2 (en) 2000-04-06
WO2000019343A3 true WO2000019343A3 (en) 2002-04-25

Family

ID=22290503

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/022984 WO2000019343A2 (en) 1998-09-30 1999-09-30 Block based design methodology

Country Status (13)

Country Link
US (10) US6269467B1 (en)
EP (1) EP1145159A3 (en)
JP (1) JP2002526908A (en)
KR (1) KR100846089B1 (en)
CN (1) CN1331079C (en)
AU (1) AU1100500A (en)
BR (1) BR9914200A (en)
CA (1) CA2345648A1 (en)
EE (1) EE200100189A (en)
HU (1) HUP0301274A2 (en)
IL (1) IL142279A0 (en)
PL (1) PL350155A1 (en)
WO (1) WO2000019343A2 (en)

Families Citing this family (349)

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