WO2000019445B1 - Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same - Google Patents

Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same

Info

Publication number
WO2000019445B1
WO2000019445B1 PCT/US1999/022894 US9922894W WO0019445B1 WO 2000019445 B1 WO2000019445 B1 WO 2000019445B1 US 9922894 W US9922894 W US 9922894W WO 0019445 B1 WO0019445 B1 WO 0019445B1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
refresh
buffer
bank
memory device
Prior art date
Application number
PCT/US1999/022894
Other languages
French (fr)
Other versions
WO2000019445A1 (en
Inventor
Wingyu Leung
Fu-Chieh Hsu
Original Assignee
Monolithic System Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/405,607 external-priority patent/US6415353B1/en
Application filed by Monolithic System Tech Inc filed Critical Monolithic System Tech Inc
Priority to DE69913366T priority Critical patent/DE69913366T2/en
Priority to JP2000572859A priority patent/JP4025509B2/en
Priority to EP99950102A priority patent/EP1119862B1/en
Publication of WO2000019445A1 publication Critical patent/WO2000019445A1/en
Publication of WO2000019445B1 publication Critical patent/WO2000019445B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/304—In main memory subsystem
    • G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and the memory controller. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A multi-bank refresh scheme is used to cut down the number of collisions between memory refresh operations and memory data access operations. A read buffer is used to buffer read data, thereby allowing memory refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer is used to buffer write data, thereby allowing memory refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. Both the read buffer and the write buffer can be constructed of DRAM cells.

Claims

- 98 -AMENDED CLAIMS treceived by the International Bureau on 30 March 2000 (30.03.00); original claims 1, 3, 6, 7, 10, 14 and 25 amended; original claim 2 cancelled; remaining claims unchanged (7 pages)]
1. A memory device comprising: a plurality of memory cells configured in a plurality of banks, wherein each of the memory cells must be refreshed within a predetermined refresh period to retain a data value; and a control circuit for accessing and refreshing the memory cells, the control circuit being configured to enable the memory cells to be randomly accessed during each memory cycle without any delays for refresh operations, the control circuit being configured to perform a refresh operation to a bank only if the bank has no pending external access request, and the control circuit being configured to always refresh all of the memory cells within the predetermined refresh period.
Claim 2 cancelled.
3. The memory device of Claim 1, wherein the control circuit comprises a static random access memory (SRAM) cache.
4. The memory device of Claim 3, wherein the SRAM cache implements a write-back policy.
5. The memory device of Claim 3, wherein the SRAM cache is configured as a direct map cache.
6. The memory device of Claim 1, wherein the control circuit comprises circuitry for independently controlling refresh operations within each bank.
- 99 - 7. The memory device of Claim 3, wherein the SRAM cache has a capacity sufficient to ensure that each of the multiple banks is refreshed properly within the refresh period.
8. The memory device of Claim 3, further comprising: a read buffer, wherein the banks are coupled to the read buffer in parallel, and wherein data read from any one of the banks is provided to the read buffer; and a cache write buffer coupled between the SRAM cache and the read buffer.
9. The memory device of Claim 3, further comprising: a write buffer, wherein the banks are coupled to the write buffer in parallel, and wherein data is written from the write buffer to any one of the banks; and a cache read buffer coupled between the SRAM cache and the write buffer.
10. The memory device of Claim 1, further comprising: a read buffer coupled to the banks and the control circuit, wherein the read buffer has a capacity greater than or equal to the capacity of a bank minus one row of memory cells; and a write buffer coupled to the banks and the control circuit, wherein the write buffer has a capacity greater than or equal to the capacity of a bank minus one row of memory cells.
11. The memory device of Claim 10, further comprising: a write-only port that couples the write buffer to the banks; and a read-write port that couples the read buffer to the banks.
12. The memory device of Claim 10, wherein the read buffer and the write buffer are constructed from static random access memory (SRAM) cells.
13. The memory device of Claim 10, wherein the read buffer and the write buffer are constructed from dynamic random access memory (DRAM) cells.
14. The memory device of Claim 1, further comprising: a plurality of access control circuits, wherein each of the access control circuits is associated with one of the banks, each access control circuit enabling a refresh operation in its associated bank only when there is a refresh pending in the associated bank and there is no access requirement to the associated bank; a central refresh timer for periodically asserting a refresh request signal; and daisy-chained connections extending between the access control circuits, wherein the daisy-chain connections sequentially pass the refresh request signal to the access control circuits in response to a clock signal.
15. The memory device of Claim 14, further comprising a refresh address generator for generating a - 101 - refresh address, the refresh address generator being coupled in parallel to all of the access control circuits, wherein the refresh address generator increments the refresh address in response to the refresh request signal.
16. The memory device of Claim 14, further comprising: a read buffer; and a write buffer, wherein the daisy-chained connections extend to the read buffer and write buffer, such that the daisy-chain connections sequentially pass the refresh request signal to the read buffer and write buffer in response to the clock signal.
17. A memory device comprising: a plurality of memory cells configured in a plurality of banks, wherein the memory cells must be periodically refreshed to retain data values, and wherein each of the banks includes a plurality of rows and columns of memory cells; a memory controller for controlling the accessing and refreshing of the memory cells such that the refreshing of the memory cells does not interfere with any external read accesses to the memory cells; and a read buffer coupled to the banks and the memory controller, wherein the read buffer has a capacity greater than or equal to the capacity of a bank minus one row of memory cells.
18. The memory device of Claim 17, wherein the read buffer is constructed from static random access memory (SRAM) cells.
19. The memory device of Claim 17, wherein the read buffer is constructed from dynamic random access memory (DRAM) cells.
20. The memory device of Claim 17, wherein the read buffer includes a plurality of entries for storing data values, and wherein the memory controller further comprises: a read buffer bank address memory for storing an address of a bank associated with valid data currently stored in one or more entries of the read buffer; and a read buffer valid bit memory for storing a plurality of valid indicator bits, wherein each of the entries of the read buffer is associated with a corresponding one of the valid indicator bits.
21. A memory device comprising: a plurality of memory cells configured in a plurality of banks, wherein the memory cells must be periodically refreshed to retain data values, and wherein each of the banks includes a plurality of rows and columns of memory cells; a memory controller for controlling the accessing and refreshing of the memory cells such that the refreshing of the memory cells does not interfere with any external write accesses to the memory cells; and - 103 - a write buffer coupled to the banks and the memory controller, wherein the write buffer has a capacity greater than or equal to the capacity of a bank minus one row of memory cells.
22. The memory device of Claim 21, wherein the write buffer is constructed from static random access memory (SRAM) cells.
23. The memory device of Claim 21, wherein the write buffer is constructed from dynamic random access memory (DRAM) cells.
24. The memory device of Claim 21, wherein the write buffer includes a plurality of entries for storing data values, and wherein the memory controller further comprises: a write buffer bank address memory for storing an address of a bank associated with valid data currently stored in one or more entries of the write buffer; and a write buffer valid bit memory for storing a plurality of valid indicator bits, wherein each of the entries of the write buffer is associated with a corresponding one of the valid indicator bits.
25. A method of operating a multi-bank memory comprising a plurality of memory cells that each must be refreshed within a predetermined refresh period to retain a data value, the method comprising the steps of: receiving external access requests to the multi-bank memory; - 104 - generating refresh requests within the multi- bank memory; immediately processing each of the external access requests; and processing a refresh request to a bank of the multi-bank memory only if the bank has no pending external access request, whereby all of the memory cells are always refreshed within the predetermined refresh period. I I I I / I I I I I I /
PCT/US1999/022894 1998-10-01 1999-10-01 Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same WO2000019445A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE69913366T DE69913366T2 (en) 1998-10-01 1999-10-01 READ / WRITE BUFFERS FOR A COMPLETE COVERING OF THE SEMI-FINISHING OF A SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING THE SAME
JP2000572859A JP4025509B2 (en) 1998-10-01 1999-10-01 Read / write buffer which is completely unaffected by refresh of semiconductor memory and its operation method
EP99950102A EP1119862B1 (en) 1998-10-01 1999-10-01 Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/165,228 1998-10-01
US09/165,228 US5999474A (en) 1998-10-01 1998-10-01 Method and apparatus for complete hiding of the refresh of a semiconductor memory
US09/405,607 1999-09-24
US09/405,607 US6415353B1 (en) 1998-10-01 1999-09-24 Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same

Publications (2)

Publication Number Publication Date
WO2000019445A1 WO2000019445A1 (en) 2000-04-06
WO2000019445B1 true WO2000019445B1 (en) 2000-05-25

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Country Status (6)

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US (2) US5999474A (en)
EP (1) EP1119862B1 (en)
JP (1) JP4025509B2 (en)
DE (1) DE69913366T2 (en)
TW (1) TW476960B (en)
WO (1) WO2000019445A1 (en)

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