WO2000019508A1 - Silicon carbide deposition method and use as a barrier layer and passivation layer - Google Patents

Silicon carbide deposition method and use as a barrier layer and passivation layer Download PDF

Info

Publication number
WO2000019508A1
WO2000019508A1 PCT/US1999/022425 US9922425W WO0019508A1 WO 2000019508 A1 WO2000019508 A1 WO 2000019508A1 US 9922425 W US9922425 W US 9922425W WO 0019508 A1 WO0019508 A1 WO 0019508A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
carbon
silicon carbide
substrate
barrier layer
Prior art date
Application number
PCT/US1999/022425
Other languages
French (fr)
Inventor
Sudha Rathi
Ping Xu
Christopher Bencher
Judy Huang
Kegang Huang
Chris Ngai
Original Assignee
Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/165,248 external-priority patent/US20030089992A1/en
Priority claimed from US09/219,945 external-priority patent/US6635583B2/en
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to EP99949929A priority Critical patent/EP1118109A1/en
Priority to JP2000572917A priority patent/JP2002526649A/en
Priority to KR1020017004234A priority patent/KR20010075563A/en
Publication of WO2000019508A1 publication Critical patent/WO2000019508A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/32—Carbides
    • C23C16/325—Silicon carbide
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/10—Heating of the reaction chamber or the substrate
    • C30B25/105—Heating of the reaction chamber or the substrate by irradiation or electric discharge
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02447—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/931—Silicon carbide semiconductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/932—Boron nitride semiconductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/952—Utilizing antireflective layer

Definitions

  • the present invention relates generally to the fabrication of integrated circuits on substrates. More particularly, the invention relates to a low temperature method for producing a silicon carbide film utilizing alkyl silanes under certain process regimes, which may be useful as a barrier layer, etch stop, and passivation layer.
  • conductive materials having low resistivity and low k (dielectric constant less than 4.0) insulators In order to further improve the speed of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and low k (dielectric constant less than 4.0) insulators to reduce the capacitive coupling between adjacent metal lines.
  • typical low k dielectric materials are generally porous and require a barrier layer.
  • typical barrier layer materials have dielectric constants that are significantly greater than 7.0 that result in a combined insulator that does not significantly reduce the dielectric constant.
  • the decreasing feature size has created a need for using a conductive material with greater conductivity.
  • Aluminum has been the choice for some time.
  • copper (Cu) is now being considered as an interconnect material in place of aluminum, because copper has a lower resistivity (1.7 ⁇ -cm compared to 3.1 ⁇ -cm for aluminum) and higher current carrying capacity.
  • copper has its own difficulties for IC manufacturing processes. For instance, copper diffuses more readily into surrounding materials and hence requires better materials for a barrier layer than traditionally has been used for aluminum. This greater diffusion characteristic exacerbates the low k porosity described above and places ever greater emphasis upon the quality of the barrier layers.
  • CMOS complementary metal-oxide-semiconductor
  • CMP chemical mechanical polishing
  • FIG. 1 shows one example of a dual damascene structure.
  • the integrated circuit 10 includes an underlying substrate 12, which may include a series of layers deposited thereon.
  • substrate is used to indicate an underlying material, and can be used to represent a series of underlying layers below the layer in question, such as a copper barrier.
  • a barrier layer 13 may be deposited over the substrate, followed by a dielectric layer 14.
  • the dielectric layer may be un-doped silicon dioxide also known as un-doped silicon glass (USG), fluorine-doped silicon glass (FSG), or some other low k material.
  • An etch stop layer 16 is deposited, pattern etched, and followed by another dielectric layer 18. The structure is again pattern etched to produce a damascene type pattern.
  • a barrier layer 22 may be needed, which typically has been made from Ta, TaN, Ti, TiN, and other materials, prior to the present invention. However, as explained above, with the smaller feature sizes and increased diffusion propensity of copper, the prior barrier layer materials are inadequate for optimal performance.
  • another layer 24, such as a passivation layer may be deposited. This structure is exemplary for a dual damascene structure and others may be more appropriate for the particular application.
  • Silicon nitride has been the etch stop material of choice and used for various overlays, including passivation layers.
  • silicon nitride has a relatively high dielectric constant (dielectric constant greater than 7.0) and may significantly increase the capacitive coupling between interconnect lines. This may lead to cross talk and/or resistance-capacitance (RC) delay, i.e., the time required to dissipate stored energy, that degrades the overall performance of the device.
  • RC resistance-capacitance
  • silicon nitride has relatively poor diffusion resistance compared to the material of the present invention.
  • the present invention generally provides an improved process for depositing silicon carbide, using a silane-based material with certain process parameters, onto an electronic device, such as a semiconductor, that is useful for forming a suitable barrier layer, an etch stop, and a passivation layer for IC applications.
  • a barrier layer in the preferred embodiment, the particular silicon carbide material is used to reduce the diffusion of copper and may also used to minimize the contribution of the barrier layer to the capacitive coupling between interconnect lines. It may also be used as an etch stop, for instance, below an intermetal dielectric (IMD) and especially if the IMD is a low k, silane- based IMD. In another embodiment, it may be used to provide a passivation layer, resistant to moisture and other adverse ambient conditions.
  • IMD intermetal dielectric
  • a preferred process sequence for forming a silicon carbide barrier layer on a substrate comprises introducing silicon, carbon, and a noble gas into a reaction zone of a process chamber, initiating a plasma in the reaction zone, reacting the silicon and the carbon in the presence of the plasma to form silicon carbide, and depositing a silicon carbide barrier layer on a substrate in the chamber.
  • Another sequence comprises introducing silicon, carbon, and a noble gas in a reaction zone of a chamber, initiating a plasma in the reaction zone, reacting the silicon and the carbon in the presence of the plasma to form silicon carbide, and depositing a silicon carbide passivation layer on the substrate.
  • Still another aspect may include a substrate having a silicon carbide barrier layer, comprising a semiconductor substrate, a dielectric layer deposited on the substrate, and a silicon carbide barrier layer having a dielectric constant of about 6 or less.
  • Figure 1 shows a schematic of an exemplary damascene structure.
  • Figure 2 shows a FTIR of the SiC of the present invention, indicating a particular bonding structure.
  • Figure 3 shows a FTIR of a previous SiC, indicating a bonding structure different than the SiC of the present invention.
  • Figure 4 shows a schematic of a multi-layered substrate.
  • Figure 5 shows a graph of copper diffusion into a SiC barrier layer, where the barrier layer was deposited with a plasma enhanced chemical vapor deposition process.
  • Figure 6 shows a transmission electron microscopy photograph of the SiC of the present invention, used as an etch stop.
  • Figure 7 shows a transmission electron microscopy photograph of the SiC of the present invention, used as a passivation layer.
  • the present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer and/or etch stop for an integrated circuit, and particularly for an integrated circuit using copper as a conductive material.
  • the invention also provides processing regimes that includes using a silane-based compound for a silicon source in some embodiments and a methylsilane as a silicon and carbon source, perhaps independently of any other carbon source and perhaps in the absence of a substantial amount of oxygen.
  • the process regimes also include the presence of a noble gas, such as helium or argon, and certain temperatures, pressures, power outputs in a plasma enhanced chemical vapor deposition chamber to produce the SiC of the present invention.
  • the silicon carbide layer may also be used as a passivation layer. This particular SiC material may be especially useful in complex structures, such as a damascene structure.
  • Chart 1 shows some of the general requirements for a barrier layer and/or an etch stop using copper as a conductive material, although other conductors may be applicable.
  • adhesion between the layers is important to reduce delamination between the layers and, in some instances, to reduce capacitance and resistance between the layers.
  • the material should also have no substantial diffusion at a substrate annealing temperature of, for example, 400°-450° C.
  • the term "no substantial" diffusion is intended to be a functional term, such that any actual diffusion into the layer is less than would affect the ability of the layer to function as a barrier layer and/or etch stop.
  • the SiC of the present invention limits the diffusion to about 250 A.
  • the copper diffusion may impair the desired current and voltage paths and contribute to crosstalk.
  • the lower the dielectric constant preferably less than 7.0, the lower the probability for cross talk and RC delay which degrades the overall performance of the device.
  • the "effective" dielectric constant is a value found by multiplying the dielectric constant times the thickness of the layer, where a desirable value should be 3.0 or less.
  • the barrier layer may be used in a damascene structure, it would be beneficial to also have suitable etch stop characteristics, such as an etch selectivity ratio of 40 to 1 or greater with respect to USG, FSG, or other low k dielectric materials.
  • the material should have a high breakdown voltage of 2 MV or more, i.e., the voltage gradient at which the molecules breakdown to allow harmful passage of electrical current. It should also have a low leakage through the layer, i.e., a low stray direct current that capacitively flows through the material.
  • Another desired characteristic from a commercial standpoint is that the material should be compatible with other processes, so the processes may be performed in situ, i.e., in a given chamber, such as in a plasma chamber, or in a system, such as an integrated cluster tool arrangement, without exposing the material to contamination environments, to produce better throughput and process control. This aspect may be particularly important with copper, because of its rapid susceptibility to oxidation.
  • Table 1 shows the process parameters of the present invention used in a 200 mm wafer chamber that allows the SiC material to be used as a barrier/etch stop and a passivation layer.
  • the silicon and carbon were derived from a common compound, such as a silane-based compound.
  • the carbon could be supplemented with other compounds, such as methane.
  • methylsilane as used herein includes any silane- based compound having at least one carbon atom attached, including the preceding list, unless otherwise indicated.
  • Table 1 the compounds used were trimethylsilane and methylsilane.
  • a noble gas such as helium or argon, was present and may assist in stabilizing the process, although other gases could be used.
  • the process regime described below establishes the suitability of the SiC material in meeting the desired criteria of a barrier layer and/or etch stop.
  • the SiC can have a low dielectric constant of about 6.0 or less.
  • the SiC barrier properties described herein enable a thinner layer to be deposited.
  • an effective SiC dielectric constant of the present invention may be about 3.0 or less. This effective dielectric constant meets the needs of a suitable copper- based IC and contrasts with silicon nitride material described above.
  • the SiC material of the present invention has a high resistance to copper diffusion with test data showing that the copper diffusion limit is about 200 to 250 A deep in the barrier layer.
  • This particular SiC material also is suitable for use as a low k, etch stop material.
  • a low k etch stop material is defined herein as an etch stop material having a dielectric constant equal to or lower than that of silicon nitride (dielectric constant of greater than or equal to 7.0) and having a relative oxide to etch selectivity of 40 to 1 or greater when used in conjunction with a silicone-based dielectric. This ratio allows greater control over the etching process and is particularly useful when etching complex structures, such as a damascene structure.
  • a silicon source such as trimethylsilane or methylsilane may be supplied to a plasma reactor, specifically a reaction zone in the chamber that is typically between the substrate surface and the gas dispersion element, such as a "showerhead", commonly known to those with ordinary skill in the art.
  • a plasma reactor specifically a reaction zone in the chamber that is typically between the substrate surface and the gas dispersion element, such as a "showerhead", commonly known to those with ordinary skill in the art.
  • a plasma enhanced chemical vapor deposition (PECND) chamber such as manufactured by Applied Materials, Inc. of Santa Clara, California, a silicon source flow rate of about 30 to 500 standard cubic centimeters (seem) may be used.
  • PECND plasma enhanced chemical vapor deposition
  • the carbon may be derived from the trimethylsilane or methylsilane, independent of other carbon sources.
  • the reaction may occur without a substantial source of oxygen introduced into the reaction zone.
  • a noble gas such as helium or argon
  • the chamber pressure is preferably maintained between about 3 to 10 Torr.
  • a single 13.56 MHz RF power source may apply about 300 to 700 watts with a power density of about 0.67 to 1.55 watts/cm 2 to the anode and cathode to form the plasma in the chamber with the silane-based gas.
  • the substrate surface temperature may be maintained between about 200° to 400° C, during the deposition of the barrier layer and/or etch stop.
  • the gas dispersion from a gas dispersion element such as a "showerhead" may be dispersed at a showerhead to substrate spacing distance between about 300 to 600 mils.
  • the trimethylsilane or methylsilane flow rate may be adjusted to about 50 to 200 seem, the helium or argon flow rate to about 200 to 1000 seem, the chamber pressure to about 6 to 10 Torr, the RF power to about 400 to 600 watts with a power density of about 0.88 to 1.33 watts/cm 2 , the substrate surface temperature maintained between about 300° to 400° C, and a showerhead to substrate spacing of about 300 to 400 mils, as shown in Table 1.
  • the characteristics developed by the preferred and most preferred process regimes differ from the generally accepted silicon carbide characteristics.
  • a different bonding structure occurs in the SiC of the present invention, shown in Figure 2, compared to a prior SiC, shown in Figure 3.
  • the charts are Fourier Transform Infrared (FTIR) charts, one of the standard laboratory tests for indicating the bonding structure, as would be known to those with ordinary skill in the art and needs no detailed explanation.
  • FTIR Fourier Transform Infrared
  • Figure 2 shows a FTIR for the SiC of the present invention.
  • the deposition resulted in a bonding structure containing CH 2 /CH 3 , SiH, SiCH 3 , Si-(CH 2 )n, and SiC.
  • Figure 3 shows comparative results with a prior SiC material deposited using silane and methane. As can be seen, there is no corresponding peak for Si-(CH 2 )n and even the peak for SiCH 3 is not as noticeable.
  • the SiC of the present invention has yielded these unexpected results in providing better barrier layer/etch stop performance than previous known depositions of SiC. These characteristics allow the SiC to be used in the various capacities disclosed herein, including a barrier layer that may or may not be used as an etch stop.
  • Figures 4-6 show charts and aspects of this SiC material used as a barrier layer and/or etch stop.
  • Figure 4 shows a construction of a multi-layer substrate test specimen, incorporating the SiC of the present invention as a barrier layer and/or etch stop material.
  • a 5000 A thick oxide layer 32 was deposited on the silicon substrate 30, followed by a 800 A thick SiC barrier layer 34.
  • the SiC barrier layer was created using the most preferred regime and had a dielectric constant of approximately 5 to 6.
  • a TaN barrier layer 36 was deposited on the SiC barrier layer 34, followed by a 5000 A thick copper layer 38.
  • a 800 A thick SiC barrier layer 40 formed according to the present invention, was deposited on the copper layer 38, followed by a 1000 A thick oxide layer 42.
  • the test specimen was then subjected to six annealing cycles with the substrate surface temperature between about 400° to 450° C in an inert nitrogen atmosphere and the copper diffusion measured. Several annealing cycles were applied to the test specimen to contaminate the barrier layer with diffused copper.
  • Figure 5 shows the test specimen diffusion results, where the lower curve shows the copper content.
  • Figure 5 shows a value 46 of approximately 3 x 10 17 atoms per cubic centimeter (atoms/cc) at a depth of 0 A from the outer surface 44 of Figure 4. This value reduces to value 48 of about 1 x 10 16 atoms/cc at a depth of about 1570 A, before the copper diffusion becomes noticeable.
  • the copper diffusion level then rises logarithmically for the next 230 A to a value 50 of approximately 3 x 10 21 atoms/cc at the copper-copper barrier interface.
  • the level of copper reduces by approximately four orders of magnitude, i.e., 1/10,000, within about 200 A to 250 A of the interface. This decrease in copper diffusion shows the effectiveness of this SiC material.
  • Figure 6 shows a transmission electron microscopy photograph of this SiC, used as an etch stop.
  • SiC layer 52 corresponds to the etch stop 16 of Figure 1 in an exemplary embodiment.
  • the underlying dielectric oxide layer 53 was about 1000 A thick, and the SiC layer 52 was about 1000 A thick.
  • the SiC layer was deposited using the most preferred barrier layer/etch stop process regime of Table 1.
  • An oxide layer 54 with a 5000 A thickness was deposited over the SiC layer 52.
  • an interconnect 55 was etched through the 5000 A thick oxide into the SiC material about 100 A deep or less, using a 150% over etch.
  • the etch selectivity was approximately 40.
  • the SiC of the present invention exhibited etch selectivity without allowing the etching chemical to intrude through or even significantly into the etch stop.
  • the SiC films of the present invention may also be used as a passivation layer.
  • the passivation layer may play an increasingly larger role in copper-based devices, because the copper diffuses into surrounding layers.
  • the silicon carbide material with some process modifications compared to the most preferred parameters of the barrier/etch stop material, offers good resistance against moisture and other adverse conditions. Moisture resistance is generally rated for no substantial loss or penetration to the underlying film in an environment of 20 psi at 150° C for a 24 hour period, as would be known to those with ordinary skill in the art.
  • the parameters for adjusting the process to form a SiC passivation layer are shown in Table 1, as well.
  • a silicon source such as trimethylsilane or methylsilane
  • the carbon may be derived from the same silane-based compound, such as trimethylsilane or methylsilane, used to obtain the silicon.
  • a noble gas such as helium or argon, may also flow into the chamber at a rate of about 1000 to 2000 seem.
  • the chamber pressure is preferably maintained between about 6 to 8 Torr.
  • a single 13.56 MHz RF power source may apply about 600 to 1000 watts with a power density of about 1.33 to 2.22 watts/cm 2 to the anode and cathode to form a plasma in the chamber.
  • the substrate temperature may be maintained between about 200° to 400° C and the showerhead to substrate surface spacing may be between about 200 to 600 mils.
  • the trimethylsilane or methylsilane flow rate is between about 200 to 400 seem, the helium or argon flow rate between about 1200 to 1700 seem, the chamber pressure maintained between about 6 to 8 Torr, the RF power between about 700 to 900 watts with a power density of about 1.55 to 2.00 watts/cm 2 , the substrate temperature between about 300° to 400° C, and a showerhead to substrate spacing between about 300 to 500 mils, as shown in Table 1.
  • Figure 7 shows a transmission electron microscopy photograph of the SiC passivation layer of the present invention. Besides being moisture resistance, one of the desirable characteristics is step coverage to conform to the features.
  • the test specimen features included an Al layer approximately 800 A thick on an underlying silicon substrate 56, having an interconnect 57 approximately 0.3 to 0.4 ⁇ m wide. The test specimen was then etched down to the substrate at about a 800 A depth, prior to deposition of the passivation layer. As can be seen in the microscopy photographs of Figure 7, the passivation layer using the SiC of the present invention provides such step coverage. Test results have shown a greater than about 35 percent sidewall 59 coverage and greater than about 45 percent bottom 59a step coverage with open filed step 59b coverage greater than about 65 percent.
  • the present invention further provides a substrate processing system having a plasma reactor including a chamber, a reaction zone in the chamber, a substrate holder for positioning a substrate in the reaction zone, and a vacuum system.
  • the processing system further comprises a gas/liquid distribution system connecting the reaction zone of the vacuum chamber that supplies an silane-based compound, an inert gas, and an RF generator coupled to the gas distribution system for generating a plasma in the reaction zone.
  • the processing system further includes a controller comprising a computer for controlling the plasma reactor, the gas distribution system, the RF generator, and a memory coupled to the controller, the memory comprising a computer usable medium including a computer readable program code for selecting the process steps for depositing a low dielectric constant film with a plasma of an silane-based compound.
  • the processing system may further comprise in one embodiment computer readable program code for selecting the process steps for depositing a barrier layer and/or etch stop of the silane-based compound, depositing a different dielectric layer, and optionally depositing a capping passivation layer of the silane-based compound.

Abstract

The present invention generally provides an improved process for depositing silicon carbide, using a silane-based material with certain process parameters, onto an electronic device, such as a semiconductor, that is useful for forming a suitable barrier layer, an etch stop, and a passivation layer for IC applications. As a barrier layer, in the preferred embodiment, the particular silicon carbide material is used to reduce the diffusion of copper and may also be used to minimize the contribution of the barrier layer to the capacitive coupling between interconnect lines. It may also be used as an etch stop, for instance, below an intermetal dielectric (IMD) and especially if the IMD is a low k, silane-based IMD. In another embodiment, it may be used to provide a passivation layer, resistant to moisture and other adverse ambient conditions. Each of these aspects may be used in a dual damascene structure.

Description

SILICON CARBIDE DEPOSITION METHOD AND USE AS A BARRIER LAYER AND PASSIVATION LAYER
Field of the Invention
The present invention relates generally to the fabrication of integrated circuits on substrates. More particularly, the invention relates to a low temperature method for producing a silicon carbide film utilizing alkyl silanes under certain process regimes, which may be useful as a barrier layer, etch stop, and passivation layer.
Background of the Invention
Consistent and fairly predictable improvement in integrated circuit design and fabrication has been observed in the last decade. One key to successful improvements is the multilevel interconnect technology, which provides the conductive paths between the devices of an integrated circuit (IC) device. The shrinking dimensions of features, presently in the sub-quarter micron and smaller range, such as horizontal interconnects (typically referred to as lines) and vertical interconnects (typically referred to as contacts or vias; contacts extend to a device on the underlying substrate, while vias extend to an underlying metal layer, such as Ml, M2, etc.) in very large scale integration (VLSI) and ultra large scale integration (ULSI) technology, has increased the importance of reducing capacitive coupling between interconnect lines in particular. In order to further improve the speed of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and low k (dielectric constant less than 4.0) insulators to reduce the capacitive coupling between adjacent metal lines. However, typical low k dielectric materials are generally porous and require a barrier layer. However, typical barrier layer materials have dielectric constants that are significantly greater than 7.0 that result in a combined insulator that does not significantly reduce the dielectric constant.
Furthermore, the decreasing feature size has created a need for using a conductive material with greater conductivity. Aluminum has been the choice for some time. However, because of the decrease in feature sizes, copper (Cu) is now being considered as an interconnect material in place of aluminum, because copper has a lower resistivity (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum) and higher current carrying capacity. However, copper has its own difficulties for IC manufacturing processes. For instance, copper diffuses more readily into surrounding materials and hence requires better materials for a barrier layer than traditionally has been used for aluminum. This greater diffusion characteristic exacerbates the low k porosity described above and places ever greater emphasis upon the quality of the barrier layers.
Adding to the difficulties of low k materials and copper diffusion is the difficulty of obtaining precise pattern etching with copper, using traditional deposition/etch processes for forming interconnects. Thus, new and more complicated processes are being developed, such as a dual damascene structure for forming copper interconnects. In a dual damascene structure, the dielectric layer is etched to define both the contacts/vias and the interconnect lines. Metal is then inlaid into the defined pattern and any excess metal is removed from the top of the structure in a planarization process, such as chemical mechanical polishing (CMP).
Figure 1 shows one example of a dual damascene structure. The integrated circuit 10 includes an underlying substrate 12, which may include a series of layers deposited thereon. In this patent, "substrate" is used to indicate an underlying material, and can be used to represent a series of underlying layers below the layer in question, such as a copper barrier. A barrier layer 13 may be deposited over the substrate, followed by a dielectric layer 14. The dielectric layer may be un-doped silicon dioxide also known as un-doped silicon glass (USG), fluorine-doped silicon glass (FSG), or some other low k material. An etch stop layer 16 is deposited, pattern etched, and followed by another dielectric layer 18. The structure is again pattern etched to produce a damascene type pattern. A barrier layer 22 may be needed, which typically has been made from Ta, TaN, Ti, TiN, and other materials, prior to the present invention. However, as explained above, with the smaller feature sizes and increased diffusion propensity of copper, the prior barrier layer materials are inadequate for optimal performance. Once the conductive material 20 has filled the features, another layer 24, such as a passivation layer, may be deposited. This structure is exemplary for a dual damascene structure and others may be more appropriate for the particular application.
Thus, with the decreasing feature sizes, the low k needs, the use of copper, and the complex dual damascene structures, new methods and materials are needed to provide improved barrier, etch stop, and passivation characteristics. Silicon nitride has been the etch stop material of choice and used for various overlays, including passivation layers. However, silicon nitride has a relatively high dielectric constant (dielectric constant greater than 7.0) and may significantly increase the capacitive coupling between interconnect lines. This may lead to cross talk and/or resistance-capacitance (RC) delay, i.e., the time required to dissipate stored energy, that degrades the overall performance of the device. Additionally, silicon nitride has relatively poor diffusion resistance compared to the material of the present invention.
In searching for new materials, others have recognized some potential in silicon carbide (SiC). But to the knowledge of the inventors, no source has adequately sought and developed a suitable barrier, etch stop, and passivation layer using SiC, and certainly not a SiC material deposited according to the process regimes disclosed herein. One such reference is U.S. Pat. No. 4,532,150 to Endo et al., which is incorporated by reference, wherein Endo refers to a specific formulation of SixC,.x in which x is a positive number of 0.2 to 0.9 for providing SiC to a substrate surface. Endo provides no disclosure of SiC as a barrier, etch stop, or passivation layer, and the process parameters given in its examples are below the preferred or most preferred parameters of the present invention. U.S. Pat. No. 5,465,680 to Loboda, incorporated by reference, discloses a SiC film in a CVD chamber, but fails to produce the film at low temperatures by requiring about 600° to 1000° C and above. Another reference, U.S. Pat. No. 5,238,866 to Bolz et al., also incorporated by reference, uses methane, silane, and phosphine to create a hydrogenated silicon carbide coating for use in the medical field, having an improved compatibility with blood. However, none of these references contain a disclosure for SiC with the following process regimes used as a barrier layer and etch stop layer.
Therefore, there is a need for an improved process using silicon carbide as a barrier layer, an etch stop, and a passivation layer for ICs.
Summary of the Invention
The present invention generally provides an improved process for depositing silicon carbide, using a silane-based material with certain process parameters, onto an electronic device, such as a semiconductor, that is useful for forming a suitable barrier layer, an etch stop, and a passivation layer for IC applications. As a barrier layer, in the preferred embodiment, the particular silicon carbide material is used to reduce the diffusion of copper and may also used to minimize the contribution of the barrier layer to the capacitive coupling between interconnect lines. It may also be used as an etch stop, for instance, below an intermetal dielectric (IMD) and especially if the IMD is a low k, silane- based IMD. In another embodiment, it may be used to provide a passivation layer, resistant to moisture and other adverse ambient conditions. Each of these aspects may be used in a dual damascene structure.
A preferred process sequence for forming a silicon carbide barrier layer on a substrate, comprises introducing silicon, carbon, and a noble gas into a reaction zone of a process chamber, initiating a plasma in the reaction zone, reacting the silicon and the carbon in the presence of the plasma to form silicon carbide, and depositing a silicon carbide barrier layer on a substrate in the chamber. Another sequence comprises introducing silicon, carbon, and a noble gas in a reaction zone of a chamber, initiating a plasma in the reaction zone, reacting the silicon and the carbon in the presence of the plasma to form silicon carbide, and depositing a silicon carbide passivation layer on the substrate. Still another aspect may include a substrate having a silicon carbide barrier layer, comprising a semiconductor substrate, a dielectric layer deposited on the substrate, and a silicon carbide barrier layer having a dielectric constant of about 6 or less.
Brief Description of the Drawings
So that the manner in which the above recited features, advantages and objects of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
Figure 1 shows a schematic of an exemplary damascene structure.
Figure 2 shows a FTIR of the SiC of the present invention, indicating a particular bonding structure.
Figure 3 shows a FTIR of a previous SiC, indicating a bonding structure different than the SiC of the present invention.
Figure 4 shows a schematic of a multi-layered substrate.
Figure 5 shows a graph of copper diffusion into a SiC barrier layer, where the barrier layer was deposited with a plasma enhanced chemical vapor deposition process.
Figure 6 shows a transmission electron microscopy photograph of the SiC of the present invention, used as an etch stop. Figure 7 shows a transmission electron microscopy photograph of the SiC of the present invention, used as a passivation layer.
Detailed Description of a Preferred Embodiment
The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer and/or etch stop for an integrated circuit, and particularly for an integrated circuit using copper as a conductive material. The invention also provides processing regimes that includes using a silane-based compound for a silicon source in some embodiments and a methylsilane as a silicon and carbon source, perhaps independently of any other carbon source and perhaps in the absence of a substantial amount of oxygen. The process regimes also include the presence of a noble gas, such as helium or argon, and certain temperatures, pressures, power outputs in a plasma enhanced chemical vapor deposition chamber to produce the SiC of the present invention. By adjusting the parameters, the silicon carbide layer may also be used as a passivation layer. This particular SiC material may be especially useful in complex structures, such as a damascene structure.
Chart 1 shows some of the general requirements for a barrier layer and/or an etch stop using copper as a conductive material, although other conductors may be applicable.
Figure imgf000007_0001
Referring to Chart 1, adhesion between the layers is important to reduce delamination between the layers and, in some instances, to reduce capacitance and resistance between the layers. The material should also have no substantial diffusion at a substrate annealing temperature of, for example, 400°-450° C. The term "no substantial" diffusion is intended to be a functional term, such that any actual diffusion into the layer is less than would affect the ability of the layer to function as a barrier layer and/or etch stop. For instance, the SiC of the present invention limits the diffusion to about 250 A. The copper diffusion may impair the desired current and voltage paths and contribute to crosstalk. Because of the decreasing feature size, as described above, the lower the dielectric constant, preferably less than 7.0, the lower the probability for cross talk and RC delay which degrades the overall performance of the device. Related to the low dielectric value is the "effective" dielectric constant, which is a value found by multiplying the dielectric constant times the thickness of the layer, where a desirable value should be 3.0 or less. Because the barrier layer may be used in a damascene structure, it would be beneficial to also have suitable etch stop characteristics, such as an etch selectivity ratio of 40 to 1 or greater with respect to USG, FSG, or other low k dielectric materials. Additionally, the material should have a high breakdown voltage of 2 MV or more, i.e., the voltage gradient at which the molecules breakdown to allow harmful passage of electrical current. It should also have a low leakage through the layer, i.e., a low stray direct current that capacitively flows through the material. Another desired characteristic from a commercial standpoint is that the material should be compatible with other processes, so the processes may be performed in situ, i.e., in a given chamber, such as in a plasma chamber, or in a system, such as an integrated cluster tool arrangement, without exposing the material to contamination environments, to produce better throughput and process control. This aspect may be particularly important with copper, because of its rapid susceptibility to oxidation.
Table 1 shows the process parameters of the present invention used in a 200 mm wafer chamber that allows the SiC material to be used as a barrier/etch stop and a passivation layer. In the embodiments tested, the silicon and carbon were derived from a common compound, such as a silane-based compound. However, the carbon could be supplemented with other compounds, such as methane. Without limitation, suitable silane-based compounds could include: methylsilane (CH3SiH3), dimethysilane ((CH3)2SiH2), trimethylsilane ((CH3)3SiH), diethylsilane ((C2H5)2SiH2), propylsilane (C3H8SiH3), vinyl methylsilane (CH2=CH)CH3SiH2), 1, 1, 2, 2-tetramethyl disilane (HSi(CH3)2— Si(CH3)2H), hexamethyl disilane ((CH3)3Si— Si(CH3)3), 1, 1, 2, 2, 3, 3- hexamethyl trisilane (H(CH3)2Si — Si(CH3)2 — SiH(CH3)2), 1, 1, 2, 3, 3-pentamethyl trisilane (H(CH3)2Si — SiH(CH3) — SiH(CH3)2), and other silane related compounds. For the purposes of this invention, the term "methylsilane" as used herein includes any silane- based compound having at least one carbon atom attached, including the preceding list, unless otherwise indicated. In Table 1, the compounds used were trimethylsilane and methylsilane. A noble gas, such as helium or argon, was present and may assist in stabilizing the process, although other gases could be used.
TABLE 1
Figure imgf000009_0001
Example 1 — Barrier/Etch Stop Layer
The inventors have discovered that the process regime described below establishes the suitability of the SiC material in meeting the desired criteria of a barrier layer and/or etch stop. Using the process regimes, the SiC can have a low dielectric constant of about 6.0 or less. Importantly, the SiC barrier properties described herein enable a thinner layer to be deposited. Thus, an effective SiC dielectric constant of the present invention may be about 3.0 or less. This effective dielectric constant meets the needs of a suitable copper- based IC and contrasts with silicon nitride material described above. Furthermore, the SiC material of the present invention has a high resistance to copper diffusion with test data showing that the copper diffusion limit is about 200 to 250 A deep in the barrier layer. This particular SiC material also is suitable for use as a low k, etch stop material. A low k etch stop material is defined herein as an etch stop material having a dielectric constant equal to or lower than that of silicon nitride (dielectric constant of greater than or equal to 7.0) and having a relative oxide to etch selectivity of 40 to 1 or greater when used in conjunction with a silicone-based dielectric. This ratio allows greater control over the etching process and is particularly useful when etching complex structures, such as a damascene structure.
To create a barrier layer and/or etch stop in the preferred process regimes, a silicon source such as trimethylsilane or methylsilane may be supplied to a plasma reactor, specifically a reaction zone in the chamber that is typically between the substrate surface and the gas dispersion element, such as a "showerhead", commonly known to those with ordinary skill in the art. For a typical commercial plasma enhanced chemical vapor deposition (PECND) chamber such as manufactured by Applied Materials, Inc. of Santa Clara, California, a silicon source flow rate of about 30 to 500 standard cubic centimeters (seem) may be used. The sequence and operation of a commercial PECND chamber are well known and need no explanation for the present invention process regimes. The carbon may be derived from the trimethylsilane or methylsilane, independent of other carbon sources. The reaction may occur without a substantial source of oxygen introduced into the reaction zone. In conjunction with the silicon and carbon sources, a noble gas, such as helium or argon, may flow into the chamber at a rate of about 100 to 2000 seem. The chamber pressure is preferably maintained between about 3 to 10 Torr. A single 13.56 MHz RF power source may apply about 300 to 700 watts with a power density of about 0.67 to 1.55 watts/cm2 to the anode and cathode to form the plasma in the chamber with the silane-based gas. The substrate surface temperature may be maintained between about 200° to 400° C, during the deposition of the barrier layer and/or etch stop. The gas dispersion from a gas dispersion element, such as a "showerhead", may be dispersed at a showerhead to substrate spacing distance between about 300 to 600 mils.
For a more optimal, designated "most preferred," process regime, the trimethylsilane or methylsilane flow rate may be adjusted to about 50 to 200 seem, the helium or argon flow rate to about 200 to 1000 seem, the chamber pressure to about 6 to 10 Torr, the RF power to about 400 to 600 watts with a power density of about 0.88 to 1.33 watts/cm2, the substrate surface temperature maintained between about 300° to 400° C, and a showerhead to substrate spacing of about 300 to 400 mils, as shown in Table 1.
The characteristics developed by the preferred and most preferred process regimes differ from the generally accepted silicon carbide characteristics. At these parameters, a different bonding structure occurs in the SiC of the present invention, shown in Figure 2, compared to a prior SiC, shown in Figure 3. The charts are Fourier Transform Infrared (FTIR) charts, one of the standard laboratory tests for indicating the bonding structure, as would be known to those with ordinary skill in the art and needs no detailed explanation. The various peaks at various wave numbers are structure specific and this graph is indicative of the particular interstitial bonding structure.
Figure 2 shows a FTIR for the SiC of the present invention. Using the most preferred range of process parameters of Table 1 with trimethylsilane, the deposition resulted in a bonding structure containing CH2/CH3, SiH, SiCH3, Si-(CH2)n, and SiC. Figure 3 shows comparative results with a prior SiC material deposited using silane and methane. As can be seen, there is no corresponding peak for Si-(CH2)n and even the peak for SiCH3 is not as noticeable. The SiC of the present invention has yielded these unexpected results in providing better barrier layer/etch stop performance than previous known depositions of SiC. These characteristics allow the SiC to be used in the various capacities disclosed herein, including a barrier layer that may or may not be used as an etch stop.
Figures 4-6 show charts and aspects of this SiC material used as a barrier layer and/or etch stop. Figure 4 shows a construction of a multi-layer substrate test specimen, incorporating the SiC of the present invention as a barrier layer and/or etch stop material. In Figure 4, a 5000 A thick oxide layer 32 was deposited on the silicon substrate 30, followed by a 800 A thick SiC barrier layer 34. The SiC barrier layer was created using the most preferred regime and had a dielectric constant of approximately 5 to 6. Next, a TaN barrier layer 36 was deposited on the SiC barrier layer 34, followed by a 5000 A thick copper layer 38. Next, a 800 A thick SiC barrier layer 40, formed according to the present invention, was deposited on the copper layer 38, followed by a 1000 A thick oxide layer 42. The test specimen was then subjected to six annealing cycles with the substrate surface temperature between about 400° to 450° C in an inert nitrogen atmosphere and the copper diffusion measured. Several annealing cycles were applied to the test specimen to contaminate the barrier layer with diffused copper.
Figure 5 shows the test specimen diffusion results, where the lower curve shows the copper content. Starting with the y-axis, Figure 5 shows a value 46 of approximately 3 x 1017 atoms per cubic centimeter (atoms/cc) at a depth of 0 A from the outer surface 44 of Figure 4. This value reduces to value 48 of about 1 x 1016 atoms/cc at a depth of about 1570 A, before the copper diffusion becomes noticeable. The copper diffusion level then rises logarithmically for the next 230 A to a value 50 of approximately 3 x 1021 atoms/cc at the copper-copper barrier interface. Thus, the level of copper reduces by approximately four orders of magnitude, i.e., 1/10,000, within about 200 A to 250 A of the interface. This decrease in copper diffusion shows the effectiveness of this SiC material.
Using the same or similar process regimes, Figure 6 shows a transmission electron microscopy photograph of this SiC, used as an etch stop. SiC layer 52 corresponds to the etch stop 16 of Figure 1 in an exemplary embodiment. The underlying dielectric oxide layer 53 was about 1000 A thick, and the SiC layer 52 was about 1000 A thick. The SiC layer was deposited using the most preferred barrier layer/etch stop process regime of Table 1. An oxide layer 54 with a 5000 A thickness was deposited over the SiC layer 52. Using an etching material, that in this case was a dry etch of octafluorocyclobutane (C4F8) and Ar, an interconnect 55 was etched through the 5000 A thick oxide into the SiC material about 100 A deep or less, using a 150% over etch. The etch selectivity was approximately 40. The SiC of the present invention exhibited etch selectivity without allowing the etching chemical to intrude through or even significantly into the etch stop.
Example 2 — Passivation Layer
In addition to serving as an improved barrier/etch stop layer, the SiC films of the present invention may also be used as a passivation layer. The passivation layer may play an increasingly larger role in copper-based devices, because the copper diffuses into surrounding layers. Furthermore, the silicon carbide material, with some process modifications compared to the most preferred parameters of the barrier/etch stop material, offers good resistance against moisture and other adverse conditions. Moisture resistance is generally rated for no substantial loss or penetration to the underlying film in an environment of 20 psi at 150° C for a 24 hour period, as would be known to those with ordinary skill in the art. The parameters for adjusting the process to form a SiC passivation layer are shown in Table 1, as well. In the preferred process regimes, a silicon source, such as trimethylsilane or methylsilane, may flow in the chamber at a rate of about 100 to 500 seem for a typical commercial PECND chamber, such as one manufactured by Applied Materials, Inc. The carbon may be derived from the same silane-based compound, such as trimethylsilane or methylsilane, used to obtain the silicon. In conjunction with the silicon and carbon source, a noble gas, such as helium or argon, may also flow into the chamber at a rate of about 1000 to 2000 seem. The chamber pressure is preferably maintained between about 6 to 8 Torr. A single 13.56 MHz RF power source may apply about 600 to 1000 watts with a power density of about 1.33 to 2.22 watts/cm2 to the anode and cathode to form a plasma in the chamber. The substrate temperature may be maintained between about 200° to 400° C and the showerhead to substrate surface spacing may be between about 200 to 600 mils. For a more optimal, designated "most preferred," process regime, the trimethylsilane or methylsilane flow rate is between about 200 to 400 seem, the helium or argon flow rate between about 1200 to 1700 seem, the chamber pressure maintained between about 6 to 8 Torr, the RF power between about 700 to 900 watts with a power density of about 1.55 to 2.00 watts/cm2, the substrate temperature between about 300° to 400° C, and a showerhead to substrate spacing between about 300 to 500 mils, as shown in Table 1.
Figure 7 shows a transmission electron microscopy photograph of the SiC passivation layer of the present invention. Besides being moisture resistance, one of the desirable characteristics is step coverage to conform to the features. The test specimen features included an Al layer approximately 800 A thick on an underlying silicon substrate 56, having an interconnect 57 approximately 0.3 to 0.4 μm wide. The test specimen was then etched down to the substrate at about a 800 A depth, prior to deposition of the passivation layer. As can be seen in the microscopy photographs of Figure 7, the passivation layer using the SiC of the present invention provides such step coverage. Test results have shown a greater than about 35 percent sidewall 59 coverage and greater than about 45 percent bottom 59a step coverage with open filed step 59b coverage greater than about 65 percent.
The present invention further provides a substrate processing system having a plasma reactor including a chamber, a reaction zone in the chamber, a substrate holder for positioning a substrate in the reaction zone, and a vacuum system. The processing system further comprises a gas/liquid distribution system connecting the reaction zone of the vacuum chamber that supplies an silane-based compound, an inert gas, and an RF generator coupled to the gas distribution system for generating a plasma in the reaction zone. The processing system further includes a controller comprising a computer for controlling the plasma reactor, the gas distribution system, the RF generator, and a memory coupled to the controller, the memory comprising a computer usable medium including a computer readable program code for selecting the process steps for depositing a low dielectric constant film with a plasma of an silane-based compound.
The processing system may further comprise in one embodiment computer readable program code for selecting the process steps for depositing a barrier layer and/or etch stop of the silane-based compound, depositing a different dielectric layer, and optionally depositing a capping passivation layer of the silane-based compound.
While the foregoing is directed to the preferred embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims which follow.

Claims

What Is Claimed Is:
1. A method of forming a silicon carbide barrier layer on a substrate, comprising: a) introducing silicon, carbon, and a noble gas into a chamber; b) initiating a plasma in the chamber; b) reacting the silicon and the carbon in the presence of the plasma to form silicon carbide; and c) depositing a silicon carbide barrier layer on the substrate in the chamber.
2. A method of claim 1, wherein the silicon comprises a silane.
3. A method of claim 1, wherein the silicon and carbon are derived from a common methylsilane, independent of other carbon sources.
4. A method of claim 1, further comprising depositing the silicon carbide barrier layer at a temperature of between about 100° to about 450° C.
5. A method of claim 1, further comprising depositing the silicon carbide barrier layer at a temperature of between about 300° to about 400° C.
6. A method of claim 1, further comprising producing a silicon carbide barrier layer having a dielectric constant of no greater than about 6.
7. A method of claim 1, further comprising producing a silicon carbide barrier layer having an effective dielectric constant of no greater than about 3.
8. A method of claim 1, further comprising producing a silicon carbide barrier layer which is copper diffusion resistant.
9. A method of claim 1, further comprising producing a silicon carbide barrier layer having a copper diffusion of about 300 A or less.
10. A method of claim 1, wherein reacting the silicon and the carbon comprises reacting the silicon and the carbon while maintaining a chamber pressure between about 6 to about 10 Torr.
11. A method of claim 1, wherein reacting the silicon and the carbon comprises reacting the silicon and the carbon using an RF power supply supplying a power density of about 0.67 to about 1.55 watts per square centimeter to an anode and cathode in the chamber.
12. A method of claim 1, wherein providing the silicon comprises providing a silane flow rate of between about 10 to about 1000 seem and providing the noble gas comprises providing a helium or argon flow rate of between about 50 to about 5000 seem.
13. A method of claim 1, wherein providing the silicon, the carbon, and the noble gas comprises providing a methylsilane flow rate of between about 30 to about 500 seem as the silicon and carbon source and a helium or argon gas flow rate of between about 100 to 2000 seem as the noble gas source and further comprising reacting the silicon and the carbon in a chamber pressure range of about 3 to about 10 Torr with an RF power source supplying a power density of about 0.67 to about 1.55 watts per square centimeter to an anode and cathode in the chamber and a substrate surface temperature of between about 200° to about 400° C and having a showerhead to substrate surface spacing of between about 300 to about 600 mils.
14. A method of claim 1, wherein the silicon carbide barrier layer comprises an etch selectivity ratio of at least about 40 to 1.
15. A method of forming a silicon carbide passivation layer on a substrate, comprising: a) introducing silicon, carbon, and a noble gas into a chamber; b) initiating a plasma in the chamber; b) reacting the silicon and the carbon in the presence of the plasma to form silicon carbide; and c) depositing a silicon carbide passivation layer on the substrate in the chamber.
16. A method of claim 15, wherein the silicon and carbon comprise a methylsilane.
17. A method of claim 15, further comprising depositing the silicon carbide barrier layer at a temperature of between about 300° to about 400° C.
18. A method of claim 15, wherein reacting the silicon and the carbon comprises reacting the silicon and the carbon using a chamber pressure between about 6 to about 8 Torr.
19. A method of claim 15, further comprising producing a silicon carbide passivation layer having no substantial penetration of moisture.
20. A method of claim 15, wherein reacting the silicon and the carbon comprises reacting the silicon and the carbon using an RF power supply supplying a power density of about 1.33 to about 2.22 watts per square centimeter to an anode and cathode in the chamber.
21. A method of claim 15, wherein providing the silicon, the carbon, and the noble gas comprises providing a methylsilane flow rate of between about 100 to about 500 seem as the silicon and the carbon source and providing a helium or argon gas flow rate between about 1000 to about 2000 seem as the noble gas source and further comprising reacting the silicon and the carbon in a chamber pressure range of about 6 to about 8 Torr with an RF power source supplying a power density of about 1.33 to about 2.22 watts per square centimeter to an anode and cathode in the chamber and a substrate temperature of between about 200° to about 400° C and having a gas dispersion head to substrate spacing of between about 200 to about 600 mils.
22. A method of claim 15, wherein the silicon and carbon are derived from a common methylsilane, independent of other carbon sources.
23. A substrate having a silicon carbide layer, comprising: a) a semiconductor substrate; b) a dielectric layer deposited on the substrate; and c) a silicon carbide layer having a dielectric constant of about 6 or less.
24. The substrate of claim 23, wherein the silicon carbide layer comprises an effective dielectric constant of about 3 or less.
25. The substrate of claim 23, wherein the silicon carbide layer comprises a copper diffusion of about 300 A or less.
26. The substrate of claim 23, wherein the silicon carbide layer comprises an etch selectivity ratio of at least about 40 to 1.
27. The substrate of claim 23, wherein the silicon carbide layer is produced by the process of providing silicon, carbon, and a noble gas comprising providing a methylsilane flow rate of between about 30 to about 500 seem as the silicon and carbon source and a helium or argon gas flow rate of between about 100 to 2000 seem as the noble gas source and further comprising reacting the silicon and the carbon in a chamber pressure range of about 3 to about 10 Torr with an RF power source supplying a power density of about 0.67 to about 1.55 watts per square centimeter to an anode and cathode in the chamber and a substrate surface temperature of between about 200° to about 400° C and having a showerhead to substrate surface spacing of between about 300 to about 600 mils.
PCT/US1999/022425 1998-10-01 1999-09-27 Silicon carbide deposition method and use as a barrier layer and passivation layer WO2000019508A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP99949929A EP1118109A1 (en) 1998-10-01 1999-09-27 Silicon carbide deposition method and use as a barrier layer and passivation layer
JP2000572917A JP2002526649A (en) 1998-10-01 1999-09-27 Method of depositing silicon carbide and use as barrier and passivation layers
KR1020017004234A KR20010075563A (en) 1998-10-01 1999-09-27 Silicon carbide deposition method and use as a barrier layer and passivation layer

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US09/165,248 1998-10-01
US09/165,248 US20030089992A1 (en) 1998-10-01 1998-10-01 Silicon carbide deposition for use as a barrier layer and an etch stop
US09/219,945 US6635583B2 (en) 1998-10-01 1998-12-23 Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating
US09/219,945 1998-12-23
US09/270,039 1999-03-16
US09/270,039 US6974766B1 (en) 1998-10-01 1999-03-16 In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application

Publications (1)

Publication Number Publication Date
WO2000019508A1 true WO2000019508A1 (en) 2000-04-06

Family

ID=27389120

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US1999/022317 WO2000020900A2 (en) 1998-10-01 1999-09-27 Silicon carbide for use as a low dielectric constant anti-reflective coating and its deposition method
PCT/US1999/022424 WO2000019498A1 (en) 1998-10-01 1999-09-27 In situ deposition of low k si carbide barrier layer, etch stop, and anti-reflective coating for damascene applications
PCT/US1999/022425 WO2000019508A1 (en) 1998-10-01 1999-09-27 Silicon carbide deposition method and use as a barrier layer and passivation layer

Family Applications Before (2)

Application Number Title Priority Date Filing Date
PCT/US1999/022317 WO2000020900A2 (en) 1998-10-01 1999-09-27 Silicon carbide for use as a low dielectric constant anti-reflective coating and its deposition method
PCT/US1999/022424 WO2000019498A1 (en) 1998-10-01 1999-09-27 In situ deposition of low k si carbide barrier layer, etch stop, and anti-reflective coating for damascene applications

Country Status (6)

Country Link
US (3) US6974766B1 (en)
EP (3) EP1118107A1 (en)
JP (2) JP2002526916A (en)
KR (4) KR100650226B1 (en)
TW (3) TW523803B (en)
WO (3) WO2000020900A2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1176226A1 (en) * 2000-07-28 2002-01-30 Applied Materials, Inc. Method of deposition of silicon carbide film in integrated circuit fabrication
EP1191123A2 (en) * 2000-09-12 2002-03-27 Applied Materials, Inc. Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers
EP1282164A2 (en) * 2001-08-01 2003-02-05 Texas Instruments Incorporated Method to improve the adhesion of dielectric layers to copper
US6537733B2 (en) 2001-02-23 2003-03-25 Applied Materials, Inc. Method of depositing low dielectric constant silicon carbide layers
EP1286387A3 (en) * 2001-08-21 2003-07-02 Texas Instruments Incorporated Method to reduce photoresist contamination from silicon carbide films
EP1351290A2 (en) * 2002-03-19 2003-10-08 Texas Instruments Incorporated Methods for forming vias and trenches with controlled SiC etch rate and selectivity
US6656840B2 (en) 2002-04-29 2003-12-02 Applied Materials Inc. Method for forming silicon containing layers on a substrate
JP2006054487A (en) * 2005-10-13 2006-02-23 Fujitsu Ltd Semiconductor integrated circuit device
US7105442B2 (en) 2002-05-22 2006-09-12 Applied Materials, Inc. Ashable layers for reducing critical dimensions of integrated circuit features
RU2687343C1 (en) * 2018-03-22 2019-05-13 Открытое акционерное общество "Композит" Method of producing composite material

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627532B1 (en) * 1998-02-11 2003-09-30 Applied Materials, Inc. Method of decreasing the K value in SiOC layer deposited by chemical vapor deposition
US6660656B2 (en) 1998-02-11 2003-12-09 Applied Materials Inc. Plasma processes for depositing low dielectric constant films
US6303523B2 (en) 1998-02-11 2001-10-16 Applied Materials, Inc. Plasma processes for depositing low dielectric constant films
US6974766B1 (en) * 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
US6821571B2 (en) * 1999-06-18 2004-11-23 Applied Materials Inc. Plasma treatment to enhance adhesion and to minimize oxidation of carbon-containing layers
GB0001179D0 (en) 2000-01-19 2000-03-08 Trikon Holdings Ltd Methods & apparatus for forming a film on a substrate
DE10042948C2 (en) * 2000-08-31 2002-07-18 Infineon Technologies Ag Integrated component and method for its production
TW535253B (en) * 2000-09-08 2003-06-01 Applied Materials Inc Plasma treatment of silicon carbide films
JP4698813B2 (en) * 2000-10-19 2011-06-08 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP3516941B2 (en) 2000-11-30 2004-04-05 キヤノン販売株式会社 Semiconductor device and manufacturing method thereof
DE10062660B4 (en) * 2000-12-15 2010-05-06 Advanced Micro Devices, Inc., Sunnyvale A method of making a silicon oxynitride ARC layer over a semiconductor structure
US6429121B1 (en) * 2001-02-07 2002-08-06 Advanced Micro Devices, Inc. Method of fabricating dual damascene with silicon carbide via mask/ARC
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
US6759327B2 (en) 2001-10-09 2004-07-06 Applied Materials Inc. Method of depositing low k barrier layers
GB0129567D0 (en) 2001-12-11 2002-01-30 Trikon Technologies Ltd Diffusion barrier
DE10297447T5 (en) * 2001-12-11 2004-11-11 Trikon Technologies Limited, Newport diffusion barrier
US6890850B2 (en) 2001-12-14 2005-05-10 Applied Materials, Inc. Method of depositing dielectric materials in damascene applications
US6838393B2 (en) 2001-12-14 2005-01-04 Applied Materials, Inc. Method for producing semiconductor including forming a layer containing at least silicon carbide and forming a second layer containing at least silicon oxygen carbide
KR100799118B1 (en) * 2001-12-19 2008-01-29 주식회사 하이닉스반도체 Method for forming multi-Cu interconnection layer
JP4340040B2 (en) * 2002-03-28 2009-10-07 富士通マイクロエレクトロニクス株式会社 Manufacturing method of semiconductor device
US7097923B2 (en) * 2002-04-30 2006-08-29 Hitachi Global Storage Technologies Method for forming thin film heads using a tri-layer anti-reflection coating for photolithographic applications and a structure thereof
KR100462759B1 (en) * 2002-05-06 2004-12-20 동부전자 주식회사 Metal line with a diffusion barrier and fabrication method thereof
KR100475931B1 (en) * 2002-07-02 2005-03-10 매그나칩 반도체 유한회사 Method for manufacturing a multi metal line in semiconductor device
JP4282054B2 (en) * 2002-09-09 2009-06-17 東京応化工業株式会社 Cleaning liquid used in dual damascene structure forming process and substrate processing method
US7749563B2 (en) * 2002-10-07 2010-07-06 Applied Materials, Inc. Two-layer film for next generation damascene barrier application with good oxidation resistance
US6908846B2 (en) * 2002-10-24 2005-06-21 Lam Research Corporation Method and apparatus for detecting endpoint during plasma etching of thin films
US6815332B2 (en) * 2002-10-30 2004-11-09 Asm Japan K.K. Method for forming integrated dielectric layers
US6939800B1 (en) * 2002-12-16 2005-09-06 Lsi Logic Corporation Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures
KR101127240B1 (en) * 2002-12-23 2012-03-29 글로벌파운드리즈 인크. Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric
US20040124420A1 (en) 2002-12-31 2004-07-01 Lin Simon S.H. Etch stop layer
JP3898133B2 (en) 2003-01-14 2007-03-28 Ｎｅｃエレクトロニクス株式会社 A method of forming a SiCHN film.
US7091133B2 (en) * 2003-01-27 2006-08-15 Asm Japan K.K. Two-step formation of etch stop layer
US6943111B2 (en) * 2003-02-10 2005-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier free copper interconnect by multi-layer copper seed
JP2004247675A (en) 2003-02-17 2004-09-02 Renesas Technology Corp Method of manufacturing semiconductor device
JP4454242B2 (en) 2003-03-25 2010-04-21 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
TWI286814B (en) 2003-04-28 2007-09-11 Fujitsu Ltd Fabrication process of a semiconductor device
KR100541185B1 (en) * 2003-07-28 2006-01-11 삼성전자주식회사 Method for forming dielectric layer of including capping layer and Method of Metal wire of the same
US20050064629A1 (en) * 2003-09-22 2005-03-24 Chen-Hua Yu Tungsten-copper interconnect and method for fabricating the same
DE102004036753B4 (en) * 2004-07-29 2008-11-06 Advanced Micro Devices Inc., Sunnyvale Process for the preparation of a nitrogen-free ARC topcoat
DE102004042168B4 (en) * 2004-08-31 2009-08-20 Advanced Micro Devices, Inc., Sunnyvale Semiconductor element having a small-ε metallization layer stack with enhanced electromigration resistance and method of forming the semiconductor element
WO2006044868A1 (en) 2004-10-20 2006-04-27 Nervonix, Inc. An active electrode, bio-impedance based, tissue discrimination system and methods and use
US7361584B2 (en) * 2004-11-04 2008-04-22 International Business Machines Corporation Detection of residual liner materials after polishing in damascene process
WO2006088015A1 (en) 2005-02-18 2006-08-24 Nec Corporation Method for forming organosilicon film, semiconductor device having such organosilicon film and method for manufacturing same
US7265437B2 (en) * 2005-03-08 2007-09-04 International Business Machines Corporation Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties
US7442649B2 (en) * 2005-03-29 2008-10-28 Lam Research Corporation Etch with photoresist mask
JP5096669B2 (en) 2005-07-06 2012-12-12 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
JP4656147B2 (en) 2005-09-13 2011-03-23 日本電気株式会社 Method for forming porous insulating film and semiconductor device
JP5093479B2 (en) 2005-11-24 2012-12-12 日本電気株式会社 Method for forming porous insulating film
KR100720526B1 (en) 2005-12-28 2007-05-22 동부일렉트로닉스 주식회사 Method for forming a metal line in semiconductor device
US8043957B2 (en) 2006-05-17 2011-10-25 Nec Corporation Semiconductor device, method for manufacturing semiconductor device and apparatus for manufacturing semiconductor
US7615427B2 (en) * 2006-06-05 2009-11-10 Chartered Semiconductor Manufacturing, Ltd. Spacer-less low-k dielectric processes
US20070290347A1 (en) * 2006-06-19 2007-12-20 Texas Instruments Incorporated Semiconductive device having resist poison aluminum oxide barrier and method of manufacture
WO2008010591A1 (en) 2006-07-21 2008-01-24 Nec Corporation Method for forming porous insulating film
EP2118003A4 (en) * 2007-03-01 2017-12-27 Plasmatrix Materials AB Method, material and apparatus for enhancing dynamic stiffness
US7964442B2 (en) * 2007-10-09 2011-06-21 Applied Materials, Inc. Methods to obtain low k dielectric barrier with superior etch resistivity
US8987039B2 (en) * 2007-10-12 2015-03-24 Air Products And Chemicals, Inc. Antireflective coatings for photovoltaic applications
KR101225642B1 (en) * 2007-11-15 2013-01-24 삼성전자주식회사 Method for formation of contact plug of semiconductor device using Ｈ2 remote plasma treatment
JP4675393B2 (en) 2008-05-12 2011-04-20 パナソニック株式会社 Semiconductor device and manufacturing method of semiconductor device
JP4891296B2 (en) * 2008-07-03 2012-03-07 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
US8053361B2 (en) * 2008-09-04 2011-11-08 Globalfoundries Singapore Pte. Ltd Interconnects with improved TDDB
WO2012074816A2 (en) 2010-11-30 2012-06-07 Applied Materials, Inc. Method and apparatus for modulating wafer treatment profile in uv chamber
US8994178B2 (en) 2012-03-29 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method for forming the same
CN102623396B (en) * 2012-04-17 2014-05-14 上海华力微电子有限公司 Method for forming connection holes
US9269678B2 (en) 2012-10-25 2016-02-23 United Microelectronics Corp. Bond pad structure and method of manufacturing the same
CN103539122B (en) * 2013-10-12 2015-12-02 台州市一能科技有限公司 A kind of preparation method of silicon carbide
US9196583B1 (en) * 2014-05-09 2015-11-24 Qualcomm Incorporated Via material selection and processing
US9590157B2 (en) 2015-06-04 2017-03-07 The Silanna Group Pty Ltd Efficient dual metal contact formation for a semiconductor device
US10574210B2 (en) 2016-03-31 2020-02-25 Qorvo Us, Inc. BAW devices having top electrode leads with reduced reflectance
CN109427650B (en) * 2017-08-24 2021-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
KR102540963B1 (en) 2017-12-27 2023-06-07 삼성전자주식회사 Method of forming a micropattern and substrate processing apparatus
DE102018107563B4 (en) * 2018-03-29 2022-03-03 Infineon Technologies Austria Ag SEMICONDUCTOR DEVICE WITH COPPER STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
US11171200B2 (en) * 2019-09-26 2021-11-09 Texas Instruments Incorporated Integrated circuits having dielectric layers including an anti-reflective coating
KR20210111017A (en) * 2020-03-02 2021-09-10 주식회사 원익아이피에스 Method for treating substrate and the semiconductor device manufactured by using the same
CN113991092B (en) * 2021-09-27 2023-05-05 杭州电子科技大学 Preparation method of silicon electrode material

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3510369A (en) * 1967-01-27 1970-05-05 Westinghouse Electric Corp Selective diffusion masking process
US4532150A (en) * 1982-12-29 1985-07-30 Shin-Etsu Chemical Co., Ltd. Method for providing a coating layer of silicon carbide on the surface of a substrate
EP0613178A2 (en) * 1993-02-26 1994-08-31 Dow Corning Corporation Integrated circuits protected from the environment by ceramic and barrier metal layers
EP0725440A2 (en) * 1995-02-02 1996-08-07 Dow Corning Corporation Silicon carbide metal diffusion barrier layer
WO1999033102A1 (en) * 1997-12-19 1999-07-01 Applied Materials, Inc. An etch stop layer for dual damascene process

Family Cites Families (264)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI57975C (en) 1979-02-28 1980-11-10 Lohja Ab Oy OVER ANCHORING VIDEO UPDATE FOR AVAILABILITY
US4262631A (en) 1979-10-01 1981-04-21 Kubacki Ronald M Thin film deposition apparatus using an RF glow discharge
US4389973A (en) 1980-03-18 1983-06-28 Oy Lohja Ab Apparatus for performing growth of compound thin films
FI64878C (en) 1982-05-10 1984-01-10 Lohja Ab Oy KOMBINATIONSFILM FOER ISYNNERHET TUNNFILMELEKTROLUMINENSSTRUKTURER
JPH07111957B2 (en) 1984-03-28 1995-11-29 圭弘 浜川 Semiconductor manufacturing method
US4759947A (en) 1984-10-08 1988-07-26 Canon Kabushiki Kaisha Method for forming deposition film using Si compound and active species from carbon and halogen compound
US4872947A (en) * 1986-12-19 1989-10-10 Applied Materials, Inc. CVD of silicon oxide using TEOS decomposition and in-situ planarization process
US4951601A (en) 1986-12-19 1990-08-28 Applied Materials, Inc. Multi-chamber integrated process system
US5000113A (en) 1986-12-19 1991-03-19 Applied Materials, Inc. Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process
US4895734A (en) 1987-03-31 1990-01-23 Hitachi Chemical Company, Ltd. Process for forming insulating film used in thin film electroluminescent device
US5028566A (en) * 1987-04-10 1991-07-02 Air Products And Chemicals, Inc. Method of forming silicon dioxide glass films
IT1226701B (en) * 1988-07-29 1991-02-05 Eniricerche Spa PROCEDURE FOR THE DEPOSITION OF ORGANOSILANS ON SILICON OR SILICON OXIDE SUBSTRATES FOR DEVICES OF THE EOS OR CHEMFET TYPE.
GB8827933D0 (en) 1988-11-30 1989-01-05 Plessey Co Plc Improvements relating to soldering processes
JPH0824191B2 (en) 1989-03-17 1996-03-06 富士通株式会社 Thin film transistor
US5011706A (en) 1989-04-12 1991-04-30 Dow Corning Corporation Method of forming coatings containing amorphous silicon carbide
JPH03105974A (en) 1989-09-19 1991-05-02 Kobe Steel Ltd Manufacture of schottky diode by synthesizing polycrystalline diamond thin film
EP0449117A3 (en) 1990-03-23 1992-05-06 Matsushita Electric Industrial Co., Ltd. Organic polymer and preparation and use thereof
ES2087968T3 (en) * 1990-03-23 1996-08-01 At & T Corp INTEGRATED CIRCUIT INTERCONNECTION.
US5401613A (en) 1990-12-13 1995-03-28 Brewer Science Method of manufacturing microelectronic devices having multifunctional photolithographic layers
US5232871A (en) 1990-12-27 1993-08-03 Intel Corporation Method for forming a titanium nitride barrier layer
EP0519079B1 (en) 1991-01-08 1999-03-03 Fujitsu Limited Process for forming silicon oxide film
US5525550A (en) 1991-05-21 1996-06-11 Fujitsu Limited Process for forming thin films by plasma CVD for use in the production of semiconductor devices
US5238866A (en) 1991-09-11 1993-08-24 GmbH & Co. Ingenieurburo Berlin Biotronik Mess- und Therapiegerate Plasma enhanced chemical vapor deposition process for producing an amorphous semiconductive surface coating
JPH05144811A (en) * 1991-11-22 1993-06-11 Hitachi Ltd Thin film semiconductor device and manufacture thereof
US5472829A (en) 1991-12-30 1995-12-05 Sony Corporation Method of forming a resist pattern by using an anti-reflective layer
JP2953349B2 (en) * 1991-12-30 1999-09-27 ソニー株式会社 Resist pattern forming method, antireflection film forming method, antireflection film, and semiconductor device
US5472827A (en) 1991-12-30 1995-12-05 Sony Corporation Method of forming a resist pattern using an anti-reflective layer
DE69221152T2 (en) 1992-05-15 1998-02-19 Shinetsu Quartz Prod VERTICAL HEAT TREATMENT DEVICE AND HEAT INSULATION MATERIAL
JPH05335299A (en) * 1992-05-29 1993-12-17 Kawasaki Steel Corp Fabrication of semiconductor device
US5739579A (en) 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US5306666A (en) * 1992-07-24 1994-04-26 Nippon Steel Corporation Process for forming a thin metal film by chemical vapor deposition
JP2734915B2 (en) 1992-11-18 1998-04-02 株式会社デンソー Dry etching method for semiconductor
JP2684942B2 (en) 1992-11-30 1997-12-03 日本電気株式会社 Chemical vapor deposition method, chemical vapor deposition apparatus, and method for manufacturing multilayer wiring
US5409543A (en) 1992-12-22 1995-04-25 Sandia Corporation Dry soldering with hot filament produced atomic hydrogen
US5360491A (en) 1993-04-07 1994-11-01 The United States Of America As Represented By The United States Department Of Energy β-silicon carbide protective coating and method for fabricating same
US5627105A (en) 1993-04-08 1997-05-06 Varian Associates, Inc. Plasma etch process and TiSix layers made using the process
US5526244A (en) 1993-05-24 1996-06-11 Bishop; Vernon R. Overhead luminaire
US5465680A (en) 1993-07-01 1995-11-14 Dow Corning Corporation Method of forming crystalline silicon carbide coatings
US5468978A (en) 1993-07-07 1995-11-21 Dowben; Peter A. Forming B1-x Cx semiconductor devices by chemical vapor deposition
US5427621A (en) 1993-10-29 1995-06-27 Applied Materials, Inc. Method for removing particulate contaminants by magnetic field spiking
JP2899600B2 (en) 1994-01-25 1999-06-02 キヤノン販売 株式会社 Film formation method
JP3254875B2 (en) * 1994-02-03 2002-02-12 富士通株式会社 Method for manufacturing semiconductor device
US5451263A (en) 1994-02-03 1995-09-19 Harris Corporation Plasma cleaning method for improved ink brand permanency on IC packages with metallic parts
US5618619A (en) 1994-03-03 1997-04-08 Monsanto Company Highly abrasion-resistant, flexible coatings for soft substrates
JP3326974B2 (en) 1994-07-28 2002-09-24 ソニー株式会社 Method for forming multilayer wiring and method for manufacturing semiconductor device
US5565084A (en) 1994-10-11 1996-10-15 Qnix Computer Co., Ltd. Electropolishing methods for etching substrate in self alignment
FI100409B (en) * 1994-11-28 1997-11-28 Asm Int Method and apparatus for making thin films
FI97731C (en) * 1994-11-28 1997-02-10 Mikrokemia Oy Method and apparatus for making thin films
US5736457A (en) 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
US5710067A (en) 1995-06-07 1998-01-20 Advanced Micro Devices, Inc. Silicon oxime film
KR0167248B1 (en) 1995-07-24 1999-02-01 문정환 Heat treatment of substrate
US5804488A (en) 1995-08-24 1998-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a tungsten silicide capacitor having a high breakdown voltage
DE19531369A1 (en) * 1995-08-25 1997-02-27 Siemens Ag Silicon-based semiconductor device with high-blocking edge termination
US5623160A (en) 1995-09-14 1997-04-22 Liberkowski; Janusz B. Signal-routing or interconnect substrate, structure and apparatus
US5789776A (en) 1995-09-22 1998-08-04 Nvx Corporation Single poly memory cell and array
US6084302A (en) 1995-12-26 2000-07-04 Micron Technologies, Inc. Barrier layer cladding around copper interconnect lines
JP2973905B2 (en) * 1995-12-27 1999-11-08 日本電気株式会社 Method for manufacturing semiconductor device
US5660682A (en) 1996-03-14 1997-08-26 Lsi Logic Corporation Plasma clean with hydrogen gas
US5741626A (en) 1996-04-15 1998-04-21 Motorola, Inc. Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC)
US5780163A (en) 1996-06-05 1998-07-14 Dow Corning Corporation Multilayer coating for microelectronic devices
US6342277B1 (en) * 1996-08-16 2002-01-29 Licensee For Microelectronics: Asm America, Inc. Sequential chemical vapor deposition
US5869396A (en) 1996-07-15 1999-02-09 Chartered Semiconductor Manufacturing Ltd. Method for forming a polycide gate electrode
US5916365A (en) 1996-08-16 1999-06-29 Sherman; Arthur Sequential chemical vapor deposition
US5801098A (en) 1996-09-03 1998-09-01 Motorola, Inc. Method of decreasing resistivity in an electrically conductive layer
US5730792A (en) 1996-10-04 1998-03-24 Dow Corning Corporation Opaque ceramic coatings
US5711987A (en) 1996-10-04 1998-01-27 Dow Corning Corporation Electronic coatings
US5776235A (en) 1996-10-04 1998-07-07 Dow Corning Corporation Thick opaque ceramic coatings
US5923056A (en) 1996-10-10 1999-07-13 Lucent Technologies Inc. Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials
US6136700A (en) * 1996-12-20 2000-10-24 Texas Instruments Incorporated Method for enhancing the performance of a contact
US6335280B1 (en) * 1997-01-13 2002-01-01 Asm America, Inc. Tungsten silicide deposition process
JPH10308283A (en) * 1997-03-04 1998-11-17 Denso Corp El element and its manufacture
US5789316A (en) 1997-03-10 1998-08-04 Vanguard International Semiconductor Corporation Self-aligned method for forming a narrow via
US5817579A (en) 1997-04-09 1998-10-06 Vanguard International Semiconductor Corporation Two step plasma etch method for forming self aligned contact
TW417249B (en) 1997-05-14 2001-01-01 Applied Materials Inc Reliability barrier integration for cu application
KR19990005812A (en) * 1997-06-30 1999-01-25 김영환 Formation method of antireflection film
US5821168A (en) 1997-07-16 1998-10-13 Motorola, Inc. Process for forming a semiconductor device
US6013553A (en) 1997-07-24 2000-01-11 Texas Instruments Incorporated Zirconium and/or hafnium oxynitride gate dielectric
US6287965B1 (en) 1997-07-28 2001-09-11 Samsung Electronics Co, Ltd. Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor
KR100385946B1 (en) * 1999-12-08 2003-06-02 삼성전자주식회사 Method for forming a metal layer by an atomic layer deposition and a semiconductor device with the metal layer as a barrier metal layer, an upper electrode, or a lower electrode of capacitor
US5926740A (en) 1997-10-27 1999-07-20 Micron Technology, Inc. Graded anti-reflective coating for IC lithography
KR100269306B1 (en) 1997-07-31 2000-10-16 윤종용 Integrate circuit device having buffer layer containing metal oxide stabilized by low temperature treatment and fabricating method thereof
KR100261017B1 (en) 1997-08-19 2000-08-01 윤종용 Method for forming metal wiring of semiconductor device
US6348376B2 (en) 1997-09-29 2002-02-19 Samsung Electronics Co., Ltd. Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact and capacitor of semiconductor device using the same
US6197683B1 (en) * 1997-09-29 2001-03-06 Samsung Electronics Co., Ltd. Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact of semiconductor device using the same
KR100274603B1 (en) 1997-10-01 2001-01-15 윤종용 Method and apparatus for fabricating semiconductor device
FI104383B (en) 1997-12-09 2000-01-14 Fortum Oil & Gas Oy Procedure for coating the inside of a plant
US6107192A (en) * 1997-12-30 2000-08-22 Applied Materials, Inc. Reactive preclean prior to metallization for sub-quarter micron application
KR100269328B1 (en) * 1997-12-31 2000-10-16 윤종용 Method for forming conductive layer using atomic layer deposition process
US6140226A (en) 1998-01-16 2000-10-31 International Business Machines Corporation Dual damascene processing for semiconductor chip interconnects
US6015917A (en) 1998-01-23 2000-01-18 Advanced Technology Materials, Inc. Tantalum amide precursors for deposition of tantalum nitride on a substrate
US6413583B1 (en) 1998-02-11 2002-07-02 Applied Materials, Inc. Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound
US6627532B1 (en) 1998-02-11 2003-09-30 Applied Materials, Inc. Method of decreasing the K value in SiOC layer deposited by chemical vapor deposition
US6303523B2 (en) 1998-02-11 2001-10-16 Applied Materials, Inc. Plasma processes for depositing low dielectric constant films
US6287990B1 (en) 1998-02-11 2001-09-11 Applied Materials, Inc. CVD plasma assisted low dielectric constant films
US6054379A (en) 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6660656B2 (en) 1998-02-11 2003-12-09 Applied Materials Inc. Plasma processes for depositing low dielectric constant films
US6159871A (en) * 1998-05-29 2000-12-12 Dow Corning Corporation Method for producing hydrogenated silicon oxycarbide films having low dielectric constant
KR100319888B1 (en) 1998-06-16 2002-01-10 윤종용 Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same
KR100278657B1 (en) 1998-06-24 2001-02-01 윤종용 Metal line structure for semiconductor device & manufacturing method thereof
US6147009A (en) 1998-06-29 2000-11-14 International Business Machines Corporation Hydrogenated oxidized silicon carbon material
US6316167B1 (en) 2000-01-10 2001-11-13 International Business Machines Corporation Tunabale vapor deposited materials as antireflective coatings, hardmasks and as combined antireflective coating/hardmasks and methods of fabrication thereof and application thereof
JP2000031387A (en) 1998-07-14 2000-01-28 Fuji Electric Co Ltd Manufacture of dielectric thin film capacitor
US6103456A (en) 1998-07-22 2000-08-15 Siemens Aktiengesellschaft Prevention of photoresist poisoning from dielectric antireflective coating in semiconductor fabrication
US6245662B1 (en) 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
KR100275738B1 (en) 1998-08-07 2000-12-15 윤종용 Method for producing thin film using atomatic layer deposition
KR20000013654A (en) 1998-08-12 2000-03-06 윤종용 Capacitor having an al2o3/aln mixed dielectric layer by using an atomic layer deposition and a manufacturing method thereof
KR100287180B1 (en) * 1998-09-17 2001-04-16 윤종용 Method for manufacturing semiconductor device including metal interconnection formed using interface control layer
US6071809A (en) * 1998-09-25 2000-06-06 Rockwell Semiconductor Systems, Inc. Methods for forming high-performing dual-damascene interconnect structures
US6974766B1 (en) * 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
KR100327328B1 (en) * 1998-10-13 2002-05-09 윤종용 Method for forming dielectric layer of capacitor having partially different thickness in the layer
US6528426B1 (en) 1998-10-16 2003-03-04 Texas Instruments Incorporated Integrated circuit interconnect and method
KR100297719B1 (en) * 1998-10-16 2001-08-07 윤종용 Method for manufacturing thin film
JP3580159B2 (en) 1998-12-18 2004-10-20 東京エレクトロン株式会社 Method of forming tungsten film
KR100331544B1 (en) 1999-01-18 2002-04-06 윤종용 Method for introducing gases into a reactor chamber and a shower head used therein
US6540838B2 (en) 2000-11-29 2003-04-01 Genus, Inc. Apparatus and concept for minimizing parasitic chemical vapor deposition during atomic layer deposition
US6305314B1 (en) 1999-03-11 2001-10-23 Genvs, Inc. Apparatus and concept for minimizing parasitic chemical vapor deposition during atomic layer deposition
US6200893B1 (en) 1999-03-11 2001-03-13 Genus, Inc Radical-assisted sequential CVD
KR100347379B1 (en) * 1999-05-01 2002-08-07 주식회사 피케이엘 Atomic layer deposition apparatus for depositing multi substrate
FI118342B (en) 1999-05-10 2007-10-15 Asm Int Apparatus for making thin films
US6218298B1 (en) * 1999-05-19 2001-04-17 Infineon Technologies North America Corp. Tungsten-filled deep trenches
US6124158A (en) 1999-06-08 2000-09-26 Lucent Technologies Inc. Method of reducing carbon contamination of a thin dielectric film by using gaseous organic precursors, inert gas, and ozone to react with carbon contaminants
US6114259A (en) 1999-07-27 2000-09-05 Lsi Logic Corporation Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage
KR20010017820A (en) 1999-08-14 2001-03-05 윤종용 Semiconductor device and manufacturing method thereof
US6984415B2 (en) * 1999-08-20 2006-01-10 International Business Machines Corporation Delivery systems for gases for gases via the sublimation of solid precursors
US6391785B1 (en) 1999-08-24 2002-05-21 Interuniversitair Microelektronica Centrum (Imec) Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6511539B1 (en) 1999-09-08 2003-01-28 Asm America, Inc. Apparatus and method for growth of a thin film
US6593653B2 (en) 1999-09-30 2003-07-15 Novellus Systems, Inc. Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications
DE10049257B4 (en) 1999-10-06 2015-05-13 Samsung Electronics Co., Ltd. Process for thin film production by means of atomic layer deposition
FI117942B (en) 1999-10-14 2007-04-30 Asm Int Process for making oxide thin films
US6475276B1 (en) 1999-10-15 2002-11-05 Asm Microchemistry Oy Production of elemental thin films using a boron-containing reducing agent
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
KR100304714B1 (en) 1999-10-20 2001-11-02 윤종용 Method for fabricating metal layer of semiconductor device using metal-halide gas
US6780704B1 (en) 1999-12-03 2004-08-24 Asm International Nv Conformal thin films over textured capacitor electrodes
KR100705926B1 (en) * 1999-12-22 2007-04-11 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device
KR100624903B1 (en) 1999-12-22 2006-09-19 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device
JP4817210B2 (en) 2000-01-06 2011-11-16 東京エレクトロン株式会社 Film forming apparatus and film forming method
FI20000099A0 (en) 2000-01-18 2000-01-18 Asm Microchemistry Ltd A method for growing thin metal films
JP4362919B2 (en) 2000-02-04 2009-11-11 株式会社デンソー Deposition method by atomic layer epitaxial growth method
DE60125338T2 (en) * 2000-03-07 2007-07-05 Asm International N.V. GRADED THIN LAYERS
FI117979B (en) 2000-04-14 2007-05-15 Asm Int Process for making oxide thin films
KR100363088B1 (en) 2000-04-20 2002-12-02 삼성전자 주식회사 Method of manufacturing barrier metal layer using atomic layer deposition method
US6482733B2 (en) * 2000-05-15 2002-11-19 Asm Microchemistry Oy Protective layers prior to alternating layer deposition
US6482740B2 (en) * 2000-05-15 2002-11-19 Asm Microchemistry Oy Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH
US6759325B2 (en) 2000-05-15 2004-07-06 Asm Microchemistry Oy Sealing porous structures
KR100403611B1 (en) 2000-06-07 2003-11-01 삼성전자주식회사 Metal-insulator-metal capacitor and manufacturing method thereof
KR100647442B1 (en) 2000-06-07 2006-11-17 주성엔지니어링(주) Method of forming a thin film using atomic layer deposition
JP3687651B2 (en) * 2000-06-08 2005-08-24 ジニテック インク． Thin film formation method
US7253076B1 (en) * 2000-06-08 2007-08-07 Micron Technologies, Inc. Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
KR100387255B1 (en) * 2000-06-20 2003-06-11 주식회사 하이닉스반도체 Method of forming a metal wiring in a semiconductor device
KR100332313B1 (en) 2000-06-24 2002-04-12 서성기 Apparatus and method for depositing thin film on wafer
US6620723B1 (en) 2000-06-27 2003-09-16 Applied Materials, Inc. Formation of boride barrier layers using chemisorption techniques
US7101795B1 (en) 2000-06-28 2006-09-05 Applied Materials, Inc. Method and apparatus for depositing refractory metal layers employing sequential deposition techniques to form a nucleation layer
US7405158B2 (en) * 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US6936538B2 (en) * 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US6551929B1 (en) * 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US6585823B1 (en) 2000-07-07 2003-07-01 Asm International, N.V. Atomic layer deposition
US6372661B1 (en) 2000-07-14 2002-04-16 Taiwan Semiconductor Manufacturing Company Method to improve the crack resistance of CVD low-k dielectric constant material
KR100444149B1 (en) * 2000-07-22 2004-08-09 주식회사 아이피에스 ALD thin film depositin equipment cleaning method
US6368954B1 (en) * 2000-07-28 2002-04-09 Advanced Micro Devices, Inc. Method of copper interconnect formation using atomic layer copper deposition
KR100630666B1 (en) * 2000-08-09 2006-10-02 삼성전자주식회사 Method of manufacturing semiconductor device including metal contact and capacitor
KR100396879B1 (en) * 2000-08-11 2003-09-02 삼성전자주식회사 Semiconductor memory device having capacitor encapsulated by multi-layer which includes double layeres being made of same material and method of manufacturing thereof
US6903005B1 (en) 2000-08-30 2005-06-07 Micron Technology, Inc. Method for the formation of RuSixOy-containing barrier layers for high-k dielectrics
US6355561B1 (en) * 2000-11-21 2002-03-12 Micron Technology, Inc. ALD method to improve surface coverage
US6613695B2 (en) 2000-11-24 2003-09-02 Asm America, Inc. Surface preparation prior to deposition
KR100869326B1 (en) 2000-11-30 2008-11-18 에이에스엠 인터내셔널 엔.브이. thin films for magnetic devices
US20020104481A1 (en) 2000-12-06 2002-08-08 Chiang Tony P. System and method for modulated ion-induced atomic layer deposition (MII-ALD)
US6949450B2 (en) 2000-12-06 2005-09-27 Novellus Systems, Inc. Method for integrated in-situ cleaning and subsequent atomic layer deposition within a single processing chamber
KR100386034B1 (en) 2000-12-06 2003-06-02 에이에스엠 마이크로케미스트리 리미티드 Method of Fabricating Semiconductor Device Employing Copper Interconnect Structure Having Diffusion Barrier Stuffed with Metal Oxide
US6416822B1 (en) 2000-12-06 2002-07-09 Angstrom Systems, Inc. Continuous method for depositing a film by modulated ion-induced atomic layer deposition (MII-ALD)
US20020197402A1 (en) 2000-12-06 2002-12-26 Chiang Tony P. System for depositing a film by modulated ion-induced atomic layer deposition (MII-ALD)
KR100385947B1 (en) 2000-12-06 2003-06-02 삼성전자주식회사 Method of forming thin film by atomic layer deposition
US6428859B1 (en) 2000-12-06 2002-08-06 Angstron Systems, Inc. Sequential method for depositing a film by modulated ion-induced atomic layer deposition (MII-ALD)
US20020076507A1 (en) 2000-12-15 2002-06-20 Chiang Tony P. Process sequence for atomic layer deposition
US20020073924A1 (en) 2000-12-15 2002-06-20 Chiang Tony P. Gas introduction system for a reactor
US6630201B2 (en) 2001-04-05 2003-10-07 Angstron Systems, Inc. Adsorption process for atomic layer deposition
US20020076481A1 (en) 2000-12-15 2002-06-20 Chiang Tony P. Chamber pressure state-based control for a reactor
US6800173B2 (en) 2000-12-15 2004-10-05 Novellus Systems, Inc. Variable gas conductance control for a process chamber
KR20020049875A (en) 2000-12-20 2002-06-26 윤종용 Ferroelectric capacitor in semiconductor memory device and method for manufacturing the same
JP3963078B2 (en) 2000-12-25 2007-08-22 株式会社高純度化学研究所 Tertiary amylimidotris (dimethylamido) tantalum, method for producing the same, raw material solution for MOCVD using the same, and method for forming a tantalum nitride film using the same
KR20020056260A (en) 2000-12-29 2002-07-10 박종섭 Method for forming metal gate of semiconductor devoie
US20020086111A1 (en) 2001-01-03 2002-07-04 Byun Jeong Soo Method of forming refractory metal nitride layers using chemisorption techniques
KR100400031B1 (en) 2001-01-17 2003-09-29 삼성전자주식회사 Contact plug of semiconductor device and method of forming the same
JP2002222934A (en) 2001-01-29 2002-08-09 Nec Corp Semiconductor device and manufacturing method thereof
US6844604B2 (en) 2001-02-02 2005-01-18 Samsung Electronics Co., Ltd. Dielectric layer for semiconductor device and method of manufacturing the same
US6951804B2 (en) * 2001-02-02 2005-10-04 Applied Materials, Inc. Formation of a tantalum-nitride layer
KR100400033B1 (en) 2001-02-08 2003-09-29 삼성전자주식회사 Semiconductor device having multi-interconnection structure and manufacturing method thereof
KR100395766B1 (en) 2001-02-12 2003-08-25 삼성전자주식회사 Ferroelectric memory device and method of forming the same
KR101050377B1 (en) 2001-02-12 2011-07-20 에이에스엠 아메리카, 인코포레이티드 Improved process for deposition of semiconductor films
US20020117399A1 (en) 2001-02-23 2002-08-29 Applied Materials, Inc. Atomically thin highly resistive barrier layer in a copper via
US6660126B2 (en) 2001-03-02 2003-12-09 Applied Materials, Inc. Lid assembly for a processing system to facilitate sequential deposition techniques
US20020121241A1 (en) 2001-03-02 2002-09-05 Nguyen Anh N. Processing chamber and method of distributing process fluids therein to facilitate sequential deposition of films
FI109770B (en) 2001-03-16 2002-10-15 Asm Microchemistry Oy Growing transition metal nitride thin films by using compound having hydrocarbon, amino or silyl group bound to nitrogen as nitrogen source material
US7348042B2 (en) 2001-03-19 2008-03-25 Novellus Systems, Inc. Continuous method for depositing a film by modulated ion-induced atomic layer deposition (MII-ALD)
JP3730962B2 (en) 2001-04-02 2006-01-05 松下電器産業株式会社 Manufacturing method of semiconductor device
US6369430B1 (en) 2001-04-02 2002-04-09 Motorola, Inc. Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the same
US20020144657A1 (en) 2001-04-05 2002-10-10 Chiang Tony P. ALD reactor employing electrostatic chuck
US20020144655A1 (en) 2001-04-05 2002-10-10 Chiang Tony P. Gas valve system for a reactor
US6420189B1 (en) 2001-04-27 2002-07-16 Advanced Micro Devices, Inc. Superconducting damascene interconnected for integrated circuit
US6447933B1 (en) 2001-04-30 2002-09-10 Advanced Micro Devices, Inc. Formation of alloy material using alternating depositions of alloy doping element and bulk material
US6596643B2 (en) 2001-05-07 2003-07-22 Applied Materials, Inc. CVD TiSiN barrier for copper integration
US6635965B1 (en) 2001-05-22 2003-10-21 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
KR100363332B1 (en) 2001-05-23 2002-12-05 Samsung Electronics Co Ltd Method for forming semiconductor device having gate all-around type transistor
US6828218B2 (en) * 2001-05-31 2004-12-07 Samsung Electronics Co., Ltd. Method of forming a thin film using atomic layer deposition
US6849545B2 (en) * 2001-06-20 2005-02-01 Applied Materials, Inc. System and method to form a composite film stack utilizing sequential deposition techniques
US6673721B1 (en) 2001-07-02 2004-01-06 Lsi Logic Corporation Process for removal of photoresist mask used for making vias in low k carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask
US7211144B2 (en) 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
TW581822B (en) * 2001-07-16 2004-04-01 Applied Materials Inc Formation of composite tungsten films
US20030029715A1 (en) 2001-07-25 2003-02-13 Applied Materials, Inc. An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems
US6806145B2 (en) * 2001-08-31 2004-10-19 Asm International, N.V. Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer
US20030042630A1 (en) * 2001-09-05 2003-03-06 Babcoke Jason E. Bubbler for gas delivery
EP1425435A2 (en) 2001-09-14 2004-06-09 Asm International N.V. Metal nitride deposition by ald using gettering reactant
US6718126B2 (en) * 2001-09-14 2004-04-06 Applied Materials, Inc. Apparatus and method for vaporizing solid precursor for CVD or atomic layer deposition
US20030049931A1 (en) * 2001-09-19 2003-03-13 Applied Materials, Inc. Formation of refractory metal nitrides using chemisorption techniques
US6607976B2 (en) 2001-09-25 2003-08-19 Applied Materials, Inc. Copper interconnect barrier layer structure and formation method
US7049226B2 (en) 2001-09-26 2006-05-23 Applied Materials, Inc. Integration of ALD tantalum nitride for copper metallization
US20030059538A1 (en) * 2001-09-26 2003-03-27 Applied Materials, Inc. Integration of barrier layer and seed layer
US20030057526A1 (en) * 2001-09-26 2003-03-27 Applied Materials, Inc. Integration of barrier layer and seed layer
US6936906B2 (en) * 2001-09-26 2005-08-30 Applied Materials, Inc. Integration of barrier layer and seed layer
US6960537B2 (en) 2001-10-02 2005-11-01 Asm America, Inc. Incorporation of nitrogen into high k dielectric film
TW589684B (en) 2001-10-10 2004-06-01 Applied Materials Inc Method for depositing refractory metal layers employing sequential deposition techniques
US20030072884A1 (en) 2001-10-15 2003-04-17 Applied Materials, Inc. Method of titanium and titanium nitride layer deposition
US6916398B2 (en) 2001-10-26 2005-07-12 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
US7780785B2 (en) 2001-10-26 2010-08-24 Applied Materials, Inc. Gas delivery apparatus for atomic layer deposition
US6423619B1 (en) 2001-11-30 2002-07-23 Motorola, Inc. Transistor metal gate structure that minimizes non-planarity effects and method of formation
US6773507B2 (en) 2001-12-06 2004-08-10 Applied Materials, Inc. Apparatus and method for fast-cycle atomic layer deposition
US7081271B2 (en) 2001-12-07 2006-07-25 Applied Materials, Inc. Cyclical deposition of refractory metal silicon nitride
US6729824B2 (en) 2001-12-14 2004-05-04 Applied Materials, Inc. Dual robot processing system
US6939801B2 (en) 2001-12-21 2005-09-06 Applied Materials, Inc. Selective deposition of a barrier layer on a dielectric material
US6809026B2 (en) 2001-12-21 2004-10-26 Applied Materials, Inc. Selective deposition of a barrier layer on a metal film
US20030116087A1 (en) 2001-12-21 2003-06-26 Nguyen Anh N. Chamber hardware design for titanium nitride atomic layer deposition
US20030123216A1 (en) 2001-12-27 2003-07-03 Yoon Hyungsuk A. Deposition of tungsten for the formation of conformal tungsten silicide
US6674138B1 (en) 2001-12-31 2004-01-06 Advanced Micro Devices, Inc. Use of high-k dielectric materials in modified ONO structure for semiconductor devices
US6998014B2 (en) 2002-01-26 2006-02-14 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
US6911391B2 (en) 2002-01-26 2005-06-28 Applied Materials, Inc. Integration of titanium and titanium nitride layers
US6827978B2 (en) 2002-02-11 2004-12-07 Applied Materials, Inc. Deposition of tungsten films
US20030157760A1 (en) 2002-02-20 2003-08-21 Applied Materials, Inc. Deposition of tungsten films for dynamic random access memory (DRAM) applications
US6833161B2 (en) 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode
US6972267B2 (en) * 2002-03-04 2005-12-06 Applied Materials, Inc. Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor
US6753618B2 (en) 2002-03-11 2004-06-22 Micron Technology, Inc. MIM capacitor with metal nitride electrode materials and method of formation
US6720027B2 (en) 2002-04-08 2004-04-13 Applied Materials, Inc. Cyclical deposition of a variable content titanium silicon nitride layer
US6846516B2 (en) 2002-04-08 2005-01-25 Applied Materials, Inc. Multiple precursor cyclical deposition system
US6875271B2 (en) 2002-04-09 2005-04-05 Applied Materials, Inc. Simultaneous cyclical deposition in different processing regions
US20030194825A1 (en) 2002-04-10 2003-10-16 Kam Law Deposition of gate metallization for active matrix liquid crystal display (AMLCD) applications
US6932871B2 (en) 2002-04-16 2005-08-23 Applied Materials, Inc. Multi-station deposition apparatus and method
US7279432B2 (en) 2002-04-16 2007-10-09 Applied Materials, Inc. System and method for forming an integrated barrier layer
US20030203616A1 (en) 2002-04-24 2003-10-30 Applied Materials, Inc. Atomic layer deposition of tungsten barrier layers using tungsten carbonyls and boranes for copper metallization
US7164165B2 (en) * 2002-05-16 2007-01-16 Micron Technology, Inc. MIS capacitor
US20030224217A1 (en) 2002-05-31 2003-12-04 Applied Materials, Inc. Metal nitride formation
US7041335B2 (en) 2002-06-04 2006-05-09 Applied Materials, Inc. Titanium tantalum nitride silicide layer
US6838125B2 (en) * 2002-07-10 2005-01-04 Applied Materials, Inc. Method of film deposition using activated precursor gases
US20040009336A1 (en) * 2002-07-11 2004-01-15 Applied Materials, Inc. Titanium silicon nitride (TISIN) barrier layer for copper diffusion
US20040013803A1 (en) * 2002-07-16 2004-01-22 Applied Materials, Inc. Formation of titanium nitride films using a cyclical deposition process
US7186385B2 (en) * 2002-07-17 2007-03-06 Applied Materials, Inc. Apparatus for providing gas to a processing chamber
US6955211B2 (en) * 2002-07-17 2005-10-18 Applied Materials, Inc. Method and apparatus for gas temperature control in a semiconductor processing system
KR100468852B1 (en) * 2002-07-20 2005-01-29 삼성전자주식회사 Manufacturing method of Capacitor Structure
US6772072B2 (en) * 2002-07-22 2004-08-03 Applied Materials, Inc. Method and apparatus for monitoring solid precursor delivery
KR100542736B1 (en) * 2002-08-17 2006-01-11 삼성전자주식회사 Method of forming oxide layer using atomic layer deposition method and method of forming capacitor of semiconductor device using the same
US6958300B2 (en) * 2002-08-28 2005-10-25 Micron Technology, Inc. Systems and methods for forming metal oxides using metal organo-amines and metal organo-oxides
JP4188033B2 (en) * 2002-08-30 2008-11-26 本田技研工業株式会社 Hydraulic shock absorber mounting structure
US6784096B2 (en) 2002-09-11 2004-08-31 Applied Materials, Inc. Methods and apparatus for forming barrier layers in high aspect ratio vias
US7262133B2 (en) 2003-01-07 2007-08-28 Applied Materials, Inc. Enhancement of copper line reliability using thin ALD tan film to cap the copper line
WO2004064147A2 (en) 2003-01-07 2004-07-29 Applied Materials, Inc. Integration of ald/cvd barriers with porous low k materials
US7211508B2 (en) * 2003-06-18 2007-05-01 Applied Materials, Inc. Atomic layer deposition of tantalum based barrier materials
US7241686B2 (en) * 2004-07-20 2007-07-10 Applied Materials, Inc. Atomic layer deposition of tantalum-containing materials using the tantalum precursor TAIMATA

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3510369A (en) * 1967-01-27 1970-05-05 Westinghouse Electric Corp Selective diffusion masking process
US4532150A (en) * 1982-12-29 1985-07-30 Shin-Etsu Chemical Co., Ltd. Method for providing a coating layer of silicon carbide on the surface of a substrate
EP0613178A2 (en) * 1993-02-26 1994-08-31 Dow Corning Corporation Integrated circuits protected from the environment by ceramic and barrier metal layers
EP0725440A2 (en) * 1995-02-02 1996-08-07 Dow Corning Corporation Silicon carbide metal diffusion barrier layer
WO1999033102A1 (en) * 1997-12-19 1999-07-01 Applied Materials, Inc. An etch stop layer for dual damascene process

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7001850B2 (en) 2000-07-28 2006-02-21 Applied Materials Inc. Method of depositing dielectric films
EP1176226A1 (en) * 2000-07-28 2002-01-30 Applied Materials, Inc. Method of deposition of silicon carbide film in integrated circuit fabrication
US6764958B1 (en) 2000-07-28 2004-07-20 Applied Materials Inc. Method of depositing dielectric films
KR100801369B1 (en) * 2000-07-28 2008-02-05 어플라이드 머티어리얼스, 인코포레이티드 Method of depositing dielectric films
US7117064B2 (en) 2000-07-28 2006-10-03 Applied Materials, Inc. Method of depositing dielectric films
EP1191123A2 (en) * 2000-09-12 2002-03-27 Applied Materials, Inc. Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers
EP1191123A3 (en) * 2000-09-12 2004-11-17 Applied Materials, Inc. Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers
US6537733B2 (en) 2001-02-23 2003-03-25 Applied Materials, Inc. Method of depositing low dielectric constant silicon carbide layers
US6855484B2 (en) 2001-02-23 2005-02-15 Applied Materials, Inc. Method of depositing low dielectric constant silicon carbide layers
EP1282164A3 (en) * 2001-08-01 2003-07-09 Texas Instruments Incorporated Method to improve the adhesion of dielectric layers to copper
EP1282164A2 (en) * 2001-08-01 2003-02-05 Texas Instruments Incorporated Method to improve the adhesion of dielectric layers to copper
EP1286387A3 (en) * 2001-08-21 2003-07-02 Texas Instruments Incorporated Method to reduce photoresist contamination from silicon carbide films
EP1351290A3 (en) * 2002-03-19 2004-12-15 Texas Instruments Incorporated Methods for forming vias and trenches with controlled SiC etch rate and selectivity
EP1351290A2 (en) * 2002-03-19 2003-10-08 Texas Instruments Incorporated Methods for forming vias and trenches with controlled SiC etch rate and selectivity
US6656840B2 (en) 2002-04-29 2003-12-02 Applied Materials Inc. Method for forming silicon containing layers on a substrate
US7105442B2 (en) 2002-05-22 2006-09-12 Applied Materials, Inc. Ashable layers for reducing critical dimensions of integrated circuit features
JP2006054487A (en) * 2005-10-13 2006-02-23 Fujitsu Ltd Semiconductor integrated circuit device
JP4521349B2 (en) * 2005-10-13 2010-08-11 富士通セミコンダクター株式会社 Semiconductor integrated circuit device
RU2687343C1 (en) * 2018-03-22 2019-05-13 Открытое акционерное общество "Композит" Method of producing composite material

Also Published As

Publication number Publication date
EP1118107A1 (en) 2001-07-25
WO2000020900A2 (en) 2000-04-13
US6974766B1 (en) 2005-12-13
KR100716622B1 (en) 2007-05-09
KR20070005025A (en) 2007-01-09
WO2000019498A1 (en) 2000-04-06
EP1118109A1 (en) 2001-07-25
KR100696034B1 (en) 2007-03-16
US7470611B2 (en) 2008-12-30
TW492138B (en) 2002-06-21
US7670945B2 (en) 2010-03-02
JP2002526649A (en) 2002-08-20
US20090130837A1 (en) 2009-05-21
KR20010075561A (en) 2001-08-09
KR100650226B1 (en) 2006-11-24
JP2002526916A (en) 2002-08-20
KR20010075563A (en) 2001-08-09
US20060089007A1 (en) 2006-04-27
KR20010079973A (en) 2001-08-22
WO2000020900A3 (en) 2000-09-08
TW432476B (en) 2001-05-01
TW523803B (en) 2003-03-11
EP1118025A2 (en) 2001-07-25

Similar Documents

Publication Publication Date Title
WO2000019508A1 (en) Silicon carbide deposition method and use as a barrier layer and passivation layer
US20030089992A1 (en) Silicon carbide deposition for use as a barrier layer and an etch stop
US6410462B1 (en) Method of making low-K carbon doped silicon oxide
US6951826B2 (en) Silicon carbide deposition for use as a low dielectric constant anti-reflective coating
KR100743775B1 (en) Method and apparatus for treating l0w k dielectric layers to reduce diffusion
US6699784B2 (en) Method for depositing a low k dielectric film (K>3.5) for hard mask application
US7242098B2 (en) Barrier film integrity on porous low k dielectrics by application of a hydrocarbon plasma treatment
US6656840B2 (en) Method for forming silicon containing layers on a substrate
US6911405B2 (en) Semiconductor device and method of manufacturing the same
US20070042610A1 (en) Method of depositing low k barrier layers
US20030148223A1 (en) Method of depositing low dielectric constant silicon carbide layers
JP2001326224A (en) Semiconductor device and its manufacturing method
KR20040068586A (en) A method of depositing dielectric materials in damascene applications
US6472333B2 (en) Silicon carbide cap layers for low dielectric constant silicon oxide layers
US7144803B2 (en) Methods of forming boron carbo-nitride layers for integrated circuit devices
US6753258B1 (en) Integration scheme for dual damascene structure
JP3532830B2 (en) Semiconductor device and manufacturing method thereof
JP4034227B2 (en) Manufacturing method of semiconductor device
JP2005045058A (en) Copper diffused barrier insulating film and method for forming the same
JP2006024668A (en) Process for fabricating semiconductor device
JP2001196365A (en) Method and device for film formation and producing method for semiconductor device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
ENP Entry into the national phase

Ref country code: JP

Ref document number: 2000 572917

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 1020017004234

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 1999949929

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1999949929

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020017004234

Country of ref document: KR

WWR Wipo information: refused in national office

Ref document number: 1020017004234

Country of ref document: KR