WO2000021027A1 - Method for producing a supporting element for an integrated circuit module for placement in chip cards - Google Patents
Method for producing a supporting element for an integrated circuit module for placement in chip cards Download PDFInfo
- Publication number
- WO2000021027A1 WO2000021027A1 PCT/DE1999/003150 DE9903150W WO0021027A1 WO 2000021027 A1 WO2000021027 A1 WO 2000021027A1 DE 9903150 W DE9903150 W DE 9903150W WO 0021027 A1 WO0021027 A1 WO 0021027A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- plastic substrate
- connection points
- module
- contact surfaces
- carrier element
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Definitions
- the invention relates to methods for producing a carrier element for an IC chip for installation in chip cards.
- Chip cards usually have a separate carrier element in which the IC component (semiconductor chip) is accommodated.
- This carrier element also called chip module
- This carrier element on which there are electrically conductive contact surfaces, is inserted into a blind hole-like cavity of the card body.
- the contact surfaces located on the carrier element which are connected to connection points of the IC module, serve for energy supply and communication with corresponding data exchange devices (chip card reader).
- Such a carrier element is known from DE 30 29 667 C2.
- a plastic substrate is used, on which metal coatings serving as contact surfaces are arranged on one side, which are applied galvanically.
- the IC chip is fixed on the plastic substrate or in a window of the plastic substrate directly on the metal coating; with the side that does not have the connection points, ie the connection points are arranged facing away from the plastic substrate and the contact surfaces.
- the electrically conductive connection between the contact surfaces and the connection points is made using fine gold wires in the so-called wirebonding process.
- the plastic substrate has access windows so that the rear sides of the metallic contact surfaces for contacting the gold wires are partially exposed. To protect the fragile gold wire and the IC chip, it and the gold wire are then surrounded with a protective casting compound.
- Such carrier element according to DE 30 29 667 C2 have some disadvantages.
- the metal coating must first be applied to the plastic substrate in several deposition and etching steps.
- the electroplating baths used represent a major environmental problem in their disposal.
- the height of such support elements is relatively large due to the design, because the gold wires between the connection points of the IC module and the contact surfaces are guided in a large loop since a certain radius of curvature must not be undercut.
- a carrier element with a large overall height requires a correspondingly deep cavity in the card body, which in turn has the consequence that the remaining thickness of the card body in the region of the cavity is very thin.
- a thin remaining card thickness in the area of the cavity again leads to problems when printing on the card body, since these are easily deformable in the area of the blind hole-like cavity.
- the object of the invention is to provide a method with which carrier elements for IC components for use in chip cards can be produced simply and inexpensively, with this method also intended to achieve a low overall height of the carrier element.
- a plastic substrate without metal coating is provided, which has cutouts that correspond to the connection points of the IC chip.
- the IC module is then fixed with its side having the connection points on the plastic substrate in such a way that the connection points are arranged precisely in relation to the cutouts in the plastic substrate.
- the electrically conductive contact surfaces are then formed using a mask by depositing a metal from the gas phase (vapor deposition) on the areas of the plastic substrate that are not covered by the mask. At the same time through the recesses in the Plastic substrate through it also made the conductive connections to the connection points of the IC chip (claim 1).
- the methods according to the invention for producing a carrier element for IC components for use in chip cards have the advantage, on the one hand, that the production of the contact areas and the production of the conductive connection between them and the connection points of the IC component take place in one step.
- the expensive and environmentally damaging electroplating for producing the contact surfaces on the plastic substrate is no longer necessary.
- the complex wirebonding is not necessary.
- the conductive connection produced in this way according to the invention between the contact surfaces and the connection points of the IC module is very much less sensitive to mechanical loads than the gold wires previously used.
- 1 is a plan view of a chip card
- Fig. 7 shows a schematic representation of the plastic substrate with IC- fixed on it
- FIG. 8 a section through a carrier element
- FIG 9 shows a section through a carrier element, which is additionally provided with a protective
- Cast housing is surrounded, Figure 10 shows a section through a further support element.
- FIG. 1 shows a top view of a chip card (1).
- the electrical contact surfaces (5) of the carrier element (4) can be seen.
- the chip card readers have corresponding contacting units via which the contact surfaces (5) are electrically connected to the electronics in the chip card reader.
- FIG. 2 shows a section through the chip card (1) in the region of the carrier element (4).
- the carrier element (4) which is only shown schematically, is located in a two-stage blind hole-like cavity (3) of the card body (2).
- the schematically illustrated carrier element (4) consists of only two parts for those who implant it into a card body: a first part on which the contact surfaces (5) are arranged and a second part in the form of a cast housing (6) which the IC module (7) is housed.
- FIG. 3 shows a top view of an IC module (monolithic semiconductor module, 7) with its connection points (8).
- the connection points (8) are mostly flat elements made of aluminum or copper.
- connection points (8) can be flush with the dielectric protective layer (9) - cf. Fig. 5 - or protrude beyond it - cf. Fig. 6 - or lower than the dielectric protective layer
- FIG. 4 shows the plastic substrate (10) on which the contact surfaces (6) are to be applied according to the invention.
- the plastic substrate (10) has cutouts (11) which correspond to the connection points (8) of the IC module (7), i.e. the number and arrangement of the cutouts (11) in the plastic substrate (10) corresponds to the number and arrangement of the connection points (8) on the IC module (7).
- the diameter of the recesses (11) and the geometry can correspond to the diameter and the geometry of the connection points (8). However, it is also provided that the diameter of the recesses (11) is larger or smaller than the diameter of the connection points (8). Both circular and rectangular cutouts (11) can be considered.
- These recesses (11) are preferably produced by stamping the plastic substrate (10).
- the mask (12) for applying the contact surfaces (5) to the plastic substrate (10) is located on the plastic substrate
- the carrier elements (4) it is preferable not to use a single, separate plastic substrate (10) with cutouts (11), but rather to use a plastic substrate tape on which there are cutouts (11) for a large number of carrier elements (4). After the carrier elements (4) have been produced, there is a carrier element band from which the individual carrier elements (4) are then separated by punching out.
- the IC component (7) is preferably fixed on the plastic substrate (10) by means of an adhesive (14) in such a way that the connection points (8) are positioned exactly in relation to the cutouts (11) in the Plastic substrate (10) are arranged.
- the adhesive (14) for example in the form of an adhesive drop - is previously applied to the IC module (7) and / or to the plastic substrate (10).
- the amount of adhesive is dosed so that a thin adhesive film forms when the IC module (7) is fixed on the plastic substrate (10), but does not reach the connection points (8) on the IC module (7).
- the IC module (7) is fixed precisely on the plastic substrate (10) with the aid of an optical detection system, for example a digital camera.
- the IC component (7) is then fixed only when the cutouts (11) in the plastic substrate (10) and the connection points (8) lie one on top of the other.
- individual plastic substrates (10) are not used in production, but rather a plastic substrate tape that is unwound from a roll by motor.
- the IC components (7) are preferably fed to the plastic substrate strip via a vacuum suction device which engages on the side of the IC component (7) facing away from the connection points (8).
- the mechanical transport of the plastic substrate tape and the mechanical feeding of the IC module (7) are monitored and controlled by the optical detection station in order to fix the IC module (7) precisely in position.
- the intermediate product (15) obtained is a plastic substrate tape on which a multiplicity of IC components (7) are each fixed with their connection points (8) to the recesses (11) of the plastic substrate (12).
- a vapor deposition system (16) is shown in which the intermediate product (15) for forming the contact surfaces (5) and the conductive connection (20) between them and the connection points (8) of the IC chip (7) by metal deposition is introduced from the gas phase.
- a correspondingly high vapor pressure of the metal to be applied (here gold, Au) is generated in the vacuum evaporation system by heating the metal. This can be done directly or indirectly in a known manner, e.g. by electron bombardment of the material to be deposited.
- the metal deposition from the gas phase can also take place in a so-called sputtering system, where the metal to be deposited on the plastic substrate (10) is better bombarded with ions in order to knock out material in the direction of the plastic substrate (10), which can then be deposited.
- sputtering are physical deposition processes for metals from the gas phase. Both methods are summarized under the English technical term "Physical Vapor Deposition" (PVD).
- a continuous metal coating is obtained as an electrically conductive connection (20) from the contact surfaces (5, 19) via the inner wall of the cutouts (11) in the plastic substrate (10) to the connection points (8) of the IC component (7).
- the cutouts (11) in the plastic substrate (10) can also be completely filled with the deposited metal.
- the gaseous metal particles can also pass through the cutouts (11) into areas adjacent to the connection points (8) and be deposited there. This advantageously ensures that the connection points (8) are at least completely covered with the “contacting metal”.
- the plastic substrate can, for example, be subjected to a surface treatment beforehand in a plasma furnace. It is also provided that this surface treatment is carried out in the vapor deposition or sputtering system itself before the actual metal deposition.
- FIG. 8 shows the finished carrier element (4) produced according to the invention using the PVD method.
- the area (21) - a wafer-thin layer - between the plastic substrate (10) and the IC component (7) is filled with a curable dielectric liquid (17) - a so-called underfiller - which, due to capillary forces, is uniform in the area (21) between the plastic substrate (10) and the IC component (7 ) distributed.
- the IC component (7) is additionally mechanically fixed on the plastic substrate (10). In addition, this seals the surface of the IC chip.
- it is preferably coated with a casting compound to form a cast housing (6).
- the invention provides for the intermediate product (15) consisting of the plastic substrate tape with the IC components (7) fixed thereon to be further processed to form the electrical contact surfaces (5) on the plastic substrate (10) so that an electrical Conductive paste or liquid (18) is applied to the areas (13) of the plastic substrate (10) that are not covered by the cover film (12).
- an electrical Conductive paste or liquid (18) is applied to the areas (13) of the plastic substrate (10) that are not covered by the cover film (12).
- this can be done with a squeegee.
- the electrically conductive paste or liquid (18) penetrates into the recesses (11) of the plastic substrate (10) and through them to the connection points (8) of the IC module (7) to form the conductive connection (20).
- the recesses (11) are completely filled with the conductive paste or liquid (18).
- a thermally curable paste or liquid (18) is preferably used.
- the area (21) between the plastic substrate (10) and the IC module (7) is then filled with a curable dielectric liquid (17) for sealing.
- a combination of PVD processes and the application of a conductive paste or liquid is also provided (not shown).
- a thin metal layer is deposited in the PVD process to form the contact areas and to connect these contact areas to the connection points, and then the conductive paste / liquid is applied to the metal layer thus deposited.
- a cover mask is dispensed with.
- the plastic substrate is coated over its entire surface with metal, the insulating spaces between the contact surfaces then being created by local removal of the metal by means of laser radiation (independent claim 4).
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000575078A JP2002526869A (en) | 1998-10-05 | 1999-09-30 | Method of manufacturing a transport element for an IC module for mounting in a chip card |
AU12624/00A AU1262400A (en) | 1998-10-05 | 1999-09-30 | Method for producing a supporting element for an integrated circuit module for placement in chip cards |
EP99955820A EP1034510A1 (en) | 1998-10-05 | 1999-09-30 | Method for producing a supporting element for an integrated circuit module for placement in chip cards |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19845665.4 | 1998-10-05 | ||
DE19845665A DE19845665C2 (en) | 1998-10-05 | 1998-10-05 | Method for producing a carrier element for an IC chip for installation in chip cards |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000021027A1 true WO2000021027A1 (en) | 2000-04-13 |
Family
ID=7883345
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/003150 WO2000021027A1 (en) | 1998-10-05 | 1999-09-30 | Method for producing a supporting element for an integrated circuit module for placement in chip cards |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1034510A1 (en) |
JP (1) | JP2002526869A (en) |
AU (1) | AU1262400A (en) |
DE (1) | DE19845665C2 (en) |
WO (1) | WO2000021027A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002334312A (en) * | 2001-05-11 | 2002-11-22 | Dainippon Printing Co Ltd | Contact/non-contact combination type ic module and its manufacturing method |
US6745163B1 (en) | 2000-09-27 | 2004-06-01 | International Business Machines Corporation | Method and system for synchronizing audio and visual presentation in a multi-modal content renderer |
DE10345257A1 (en) * | 2003-09-29 | 2005-04-28 | Infineon Technologies Ag | Chip card with contact fields and method for producing such contact fields |
EP1755162A3 (en) * | 2005-08-17 | 2007-10-17 | General Electric Company | Power semiconductor packaging method and structure |
US7575173B2 (en) | 2003-07-28 | 2009-08-18 | Infineon Technologies, Ag | Smart card, smart card module, and a method for production of a smart card module |
US7829386B2 (en) | 2005-08-17 | 2010-11-09 | General Electric Company | Power semiconductor packaging method and structure |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10311696A1 (en) * | 2003-03-17 | 2004-10-07 | Infineon Technologies Ag | smart card |
DE102007054692A1 (en) * | 2007-11-12 | 2009-05-20 | Mühlbauer Ag | Method for producing a transponder on a substrate |
FI125526B (en) | 2008-08-25 | 2015-11-13 | Ge Embedded Electronics Oy | Packaged Circuit Board Structure with Electronic Components and Method for Manufacture of Packaged Circuit Board Structure with Electronic Components |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3029667A1 (en) * | 1980-08-05 | 1982-03-11 | GAO Gesellschaft für Automation und Organisation mbH, 8000 München | CARRIER ELEMENT FOR AN IC COMPONENT |
US4731645A (en) * | 1982-05-14 | 1988-03-15 | U.S. Philips Corporation | Connection of a semiconductor to elements of a support, especially of a portable card |
US4889980A (en) * | 1985-07-10 | 1989-12-26 | Casio Computer Co., Ltd. | Electronic memory card and method of manufacturing same |
US5672542A (en) * | 1994-08-08 | 1997-09-30 | Hewlett Packard Company | Method of making solder balls by contained paste deposition |
US5740606A (en) * | 1995-11-03 | 1998-04-21 | Schlumberger Industries | Method of manufacturing a set of electronic modules for electronic memory cards |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2671416B1 (en) * | 1991-01-04 | 1993-04-23 | Solaic Sa | PROCESS FOR THE MANUFACTURE OF A MEMORY CARD AND MEMORY CARD THUS OBTAINED. |
DE19632113C1 (en) * | 1996-08-08 | 1998-02-19 | Siemens Ag | Chip card, method for producing a chip card and semiconductor chip for use in a chip card |
-
1998
- 1998-10-05 DE DE19845665A patent/DE19845665C2/en not_active Revoked
-
1999
- 1999-09-30 WO PCT/DE1999/003150 patent/WO2000021027A1/en active Application Filing
- 1999-09-30 JP JP2000575078A patent/JP2002526869A/en active Pending
- 1999-09-30 EP EP99955820A patent/EP1034510A1/en not_active Withdrawn
- 1999-09-30 AU AU12624/00A patent/AU1262400A/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3029667A1 (en) * | 1980-08-05 | 1982-03-11 | GAO Gesellschaft für Automation und Organisation mbH, 8000 München | CARRIER ELEMENT FOR AN IC COMPONENT |
US4731645A (en) * | 1982-05-14 | 1988-03-15 | U.S. Philips Corporation | Connection of a semiconductor to elements of a support, especially of a portable card |
US4889980A (en) * | 1985-07-10 | 1989-12-26 | Casio Computer Co., Ltd. | Electronic memory card and method of manufacturing same |
US5672542A (en) * | 1994-08-08 | 1997-09-30 | Hewlett Packard Company | Method of making solder balls by contained paste deposition |
US5740606A (en) * | 1995-11-03 | 1998-04-21 | Schlumberger Industries | Method of manufacturing a set of electronic modules for electronic memory cards |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6745163B1 (en) | 2000-09-27 | 2004-06-01 | International Business Machines Corporation | Method and system for synchronizing audio and visual presentation in a multi-modal content renderer |
JP2002334312A (en) * | 2001-05-11 | 2002-11-22 | Dainippon Printing Co Ltd | Contact/non-contact combination type ic module and its manufacturing method |
US7575173B2 (en) | 2003-07-28 | 2009-08-18 | Infineon Technologies, Ag | Smart card, smart card module, and a method for production of a smart card module |
DE10345257A1 (en) * | 2003-09-29 | 2005-04-28 | Infineon Technologies Ag | Chip card with contact fields and method for producing such contact fields |
DE10345257B4 (en) * | 2003-09-29 | 2008-10-02 | Infineon Technologies Ag | Chip card with contact fields and method for producing such contact fields |
US7579679B2 (en) | 2003-09-29 | 2009-08-25 | Infineon Technologies Ag | Chipcard with contact areas and method for producing contact areas |
EP1755162A3 (en) * | 2005-08-17 | 2007-10-17 | General Electric Company | Power semiconductor packaging method and structure |
US7829386B2 (en) | 2005-08-17 | 2010-11-09 | General Electric Company | Power semiconductor packaging method and structure |
Also Published As
Publication number | Publication date |
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AU1262400A (en) | 2000-04-26 |
DE19845665A1 (en) | 2000-04-20 |
JP2002526869A (en) | 2002-08-20 |
DE19845665C2 (en) | 2000-08-17 |
EP1034510A1 (en) | 2000-09-13 |
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