WO2000024054A1 - Structure comprising a semiconductor layer and/or electronic elements on an insulating support and method for making same - Google Patents

Structure comprising a semiconductor layer and/or electronic elements on an insulating support and method for making same Download PDF

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Publication number
WO2000024054A1
WO2000024054A1 PCT/FR1999/002529 FR9902529W WO0024054A1 WO 2000024054 A1 WO2000024054 A1 WO 2000024054A1 FR 9902529 W FR9902529 W FR 9902529W WO 0024054 A1 WO0024054 A1 WO 0024054A1
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wafer
semiconductor layer
layer
semiconductor
complementary
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PCT/FR1999/002529
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French (fr)
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Jean-Pierre Joly
Michel Bruel
Claude Jaussaud
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Commissariat A L'energie Atomique
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/7602—Making of isolation regions between components between components manufactured in an active substrate comprising SiC compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01063—Europium [Eu]
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    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]

Definitions

  • the present invention relates to a structure comprising a semiconductor layer and / or electronic elements on an insulating support and its manufacturing process.
  • Gallium arsenide (AsGa) electronic devices can be produced on Structures made up of a semi-insulating AsGa plate, serving as support, covered with a epitaxial layer of AsGa suitable - to make the desired devices there.
  • the use of an AsGa plate as a support has several drawbacks which are: their high cost, their size limitation (diameter of 150 mm maximum), their poor adaptation to the production of complex integrated circuits and their poor thermal conductivity .
  • the silicon has a thermal conductivity which can be considered satisfactory.
  • the zone fusion manufacturing method makes it possible to obtain silicon having satisfactory electrical insulation.
  • this method is expensive to implement and it cannot provide large inserts (that is to say with a diameter greater than 150 mm).
  • the inventors of the present invention had the idea of using the phenomenon of increase in the resistivity of semiconductor materials subjected to irradiation to obtain satisfactory supports. They have therefore taken advantage of a phenomenon hitherto considered a disadvantage.
  • the defects thus created in the silicon, and even more in the carbide of silicon are very stable in .temperature, which allows to keep the insulating character even after annealing.
  • the silicon carbide that has become insulating can remain so until high operating temperatures of the devices developed in the surface semiconductor layer (for example 200 to 300 ° C or more) or more generally electronic devices.
  • the present invention thus makes it possible to provide structures comprising a semiconductor layer and / or electronic elements resting on a support which is both electrically insulating and good thermal conductor.
  • electrostatic elements is understood to mean all the active and / or passive elements possibly grouped together in the form of chips and reported for example by “Flip Chip” techniques on an insulating support.
  • Another advantage of the present invention is that the support and the surface semiconductor layer being able to be produced from the same base material, there is no problem due to differences in coefficient of thermal expansion between these structural parts.
  • the subject of the invention is therefore a method of manufacturing a structure comprising a semiconductor layer and / or at least one electronic element on an electrically insulating support, comprising a step of irradiating a wafer of semiconductor material with particles susceptible to make this semiconductor material electrically insulating by creating defects, said irradiated plate thus providing the electrically insulating support, characterized in that the layer semiconductor and / or the electronic element are attached to the irradiated wafer.
  • the irradiation step can be implemented on a wafer of semiconductor material having a thermal conductivity considered to be satisfactory.
  • the semiconductor material of the wafer can be subjected to irradiation of neutrons, electrons, ions, ⁇ particles, etc.
  • the energy of these particles is chosen so that the entire volume of the wafer, or a significant proportion of it, either irradiated.
  • the irradiation dose is chosen so that the final resistivity of the support is high enough for the desired application.
  • the semiconductor layer can be obtained from a complementary wafer of semiconductor material bonded to the irradiated wafer, said complementary wafer being thinned to provide said added layer. It can also be obtained from a complementary wafer of semiconductor material in which the semiconductor layer has been defined by a layer of microcavities generated by ion implantation, the complementary wafer being glued to the irradiated wafer and then cleaved at the layer of microcavities to keep only the semiconductor layer on the irradiated wafer.
  • the cleavage of the complementary wafer is obtained by the coalescence of the microcavities resulting from a heat treatment.
  • the added layer can also be obtained from a complementary wafer of semiconductor material in which an intermediate layer has been defined making it possible to separate the semiconductor layer from the rest of the wafer complementary, this .intermediate layer being selectively attackable with respect to said semiconductor layer and to the rest of the complementary wafer or capable of being torn off mechanically from the rest of the complementary wafer after it has been bonded to the irradiated wafer.
  • This intermediate layer is obtained for example by anodic attack of an initial wafer intended to constitute the complementary wafer, this anodic attack producing a porous layer forming the intermediate layer, the semiconductor layer being formed by epitaxy carried out on the intermediate layer.
  • the bonding of said complementary wafer to said irradiated wafer is obtained by molecular adhesion.
  • the surfaces to be bonded have undergone a preparation making it possible to promote their bonding by molecular adhesion.
  • the method can also include the interposition of an intermediate layer between the irradiated wafer and the complementary wafer in order to improve bonding.
  • the semiconductor layer When the semiconductor layer is a layer added to the irradiated wafer, it may have been previously at least partially treated to develop at least one electronic component therein.
  • the invention also relates to a structure comprising a semiconductor layer and / or at least one electronic element on an electrically insulating support, the insulating support comprising a semiconductor material whose resistivity has been increased by irradiation by means of particles, characterized in that that the semiconductor layer and / or one electronic element are elements added to the irradiated wafer.
  • the semiconductor material of the insulating support can be chosen to have a thermal conductivity - considered satisfactory.
  • the semiconductor layer may comprise at least one electronic component produced totally or partially.
  • the structure may further comprise an intermediate layer between the electrically insulating support and the semiconductor layer.
  • the semiconductor layer can be made of a material chosen from silicon, gallium arsenide, silicon carbide and indium phosphide.
  • the electrically insulating support can be made of a material chosen from silicon and silicon carbide.
  • FIG. 1 shows, in transverse view, a wafer of semiconductor material during the irradiation step of the process according to the invention
  • FIG. 2 shows, in transverse view, a structure comprising a semiconductor layer on a support electrically insulating according to the present invention
  • FIG. 3 illustrates an embodiment of the present invention
  • FIG. 4 represents, in transverse view, the structure obtained after having implemented the method illustrated by FIG. 3,
  • FIG. 5 illustrates an embodiment of the present invention for which electronic components were produced in the semiconductor layer before it was transferred to the irradiated support
  • FIG. 6 represents, in transverse view, the structure obtained after having implemented the method illustrated by FIG. 5,
  • FIG. 7 shows, in transverse view, a structure according to the invention comprising electronic elements on an electrically insulating support.
  • the wafer is irradiated with a flow of particles so as to create defects in the crystal lattice.
  • Figure 1 shows a wafer of semiconductor material 1 subjected to particle irradiation represented by the arrows 2.
  • the crystal defects created have the effect of greatly increasing the electrical resistivity of the semiconductor material.
  • the irradiation is of p-reference carried out by means of a neutron flux comprising a high proportion of energetic neutrons which are effective for the creation of the desired defects.
  • energy neutrons are meant those which go from epithermal neutrons to fast neutrons, that is to say a range of energy going from a few eV to a few MeV, as opposed to thermal neutrons (from a few eV to a few eV) which are less efficient for creation of faults and which generate transmutations.
  • the irradiation is carried out under conditions very different from those used in the technique called "neutron transmutation doping" where the reverse ratio is favored since it is sought to avoid the creation of defects and to maximize transmutations to, for example, transform the isotope 30 of silicon into phosphorus.
  • the irradiation can be carried out in a nuclear reactor, of the pool type for example, or by means of a neutron generator using the nuclear reactions of a beam of charged particles with a target.
  • a nuclear reactor of the pool type for example, or by means of a neutron generator using the nuclear reactions of a beam of charged particles with a target.
  • the irradiation of the conductive wafer with a sufficient integrated flux of energetic neutrons creates enough defects that it is very difficult to anneal them during subsequent heat treatments that the structure can undergo during its use. It can be noted that the irradiation can also be carried out on the ingot, the cutting of the ingot and its packaging in the form of plates being carried out thereafter.
  • a dose of energetic neutrons of 10 17 neutrons / cm 2 makes it possible to obtain a resistivity greater than 10 4 ⁇ .cm in the silicon carbide whatever the initial resistivity.
  • a dose of 10 15 neutrons / cm 2 makes it possible to obtain a resistivity greater than 10 5 ⁇ .cm, which makes it possible to use as semiconductor material silicon ' obtained by the Czochralski method.
  • the entire wafer After irradiation, the entire wafer is in a state of high resistivity and, as it is, is unsuitable for the production of electronic devices.
  • the wafer of irradiated semiconductor material is for example made of silicon carbide
  • the semiconductor layer intended for producing electronic components is attached to the irradiated wafer. This gives structure 3, shown in FIG. 2, consisting of an insulating support 1 to which the semiconductor layer 4 adheres.
  • the semiconductor layer can be made adherent to the insulating support by bonding.
  • FIG. 3 shows the adherent contact of the insulating support 1 (for example in silicon or in SiC) with a semiconductor wafer 10 (for example in Si, AsGa, SiC) intended to supply the semiconductor layer.
  • Adherent contacting can be done by means of an adhesive substance. It can also be done by the molecular adhesion technique.
  • an intermediate layer 11 can be used to ensure better quality of bonding and / or better interface properties between the insulating support and the surface semiconductor layer of the future structure.
  • the thickness of the semiconductor layer of the structure must be a fraction of the thickness of the semiconductor wafer 10.
  • the future semiconductor layer is delimited by the dashed line 12.
  • the unwanted part of the semiconductor wafer 10 is eliminated.
  • Different methods can be used to achieve this result. We can use grinding, etching, polishing.
  • FIG. 4 a structure 13 formed of an insulating support 1, an intermediate layer 11 and a layer surface semiconductor 14.
  • This structure may for example comprise a support 1 made of electrically insulating silicon supporting a layer 11 of silicon oxide which itself supports a surface layer 14 of silicon suitable for the production of electronic components.
  • a final polishing optionally makes it possible to perfect the surface condition of the surface layer 14.
  • Bonding can allow the establishment on the insulating support of a semiconductor layer in which electronic components have been produced, partially or completely. This is shown in Figure 5 which shows the adhesive contact of the insulating support 1 with a semiconductor wafer 20 via a intermediate bonding layer 11.
  • the reference 21 represents electronic components which have been produced from the face 22 of the semiconductor wafer 20.
  • the future semiconductor layer of the structure is delimited by the line in dashed lines 23.
  • the unwanted part of the semiconductor wafer 20 is eliminated, for example by one of the methods mentioned above.
  • the structure shown in FIG. 6 is then obtained, that is to say a structure 24 formed of an insulating support 1, an intermediate layer 11 and a surface semiconductor layer 25 containing electronic components 21.
  • FIG. 7 represents a structure 30 according to the invention this time comprising the insulating support 1 on one face of which electronic elements 31, for example electronic chips have been transferred directly

Abstract

The invention concerns a structure (3) comprising a semiconductor layer (4) directly mounted on an electrically insulating support (1). The support (1) is made of semiconductor material electrically insulated following irradiation with particles.

Description

STRUCTURE COMPORTANT UNE COUCHE SEMICONDUCTRICE ET/OU STRUCTURE COMPRISING A SEMICONDUCTOR LAYER AND / OR
DES ELEMENTS ELECTRONIQUES SUR UN SUPPORT ISOLANT ETELECTRONIC ELEMENTS ON AN INSULATING MEDIUM AND
SON PROCEDE DE FABRICATIONITS MANUFACTURING PROCESS
Domaine techniqueTechnical area
La présente invention concerne une structure comportant une couche semiconductrice et/ou des éléments électroniques sur un support isolant et son procédé de fabrication.The present invention relates to a structure comprising a semiconductor layer and / or electronic elements on an insulating support and its manufacturing process.
Etat de la technique antérieureState of the art
Le besoin d'intégration dans un même circuit intégré de fonction logiques, analogiques, de composants passifs et actifs radiofréquences , impose de porter une attention particulière aux pertes électriques liées à la nature du support sur lequel sont réalisés les circuits. Il est en particulier important que, à l'exception des zones de la couche superficielle de la structure où sont réalisés les dispositifs électroniques et des éléments électroniques, le reste de la structure soit hautement résistif ou isolant électrique. De plus, il est important d'éviter 1 ' auto-échauffement des dispositifs électroniques et, plus généralement, l'élévation de température de cette couche superficielle. Pour cela, il est important d'éviter la présence sous cette couche superficielle d'un matériau qui soit mauvais conducteur thermique ou isolant thermique.The need for integration in a single integrated circuit of logic, analog, passive and active radio frequency components, requires special attention to be paid to the electrical losses linked to the nature of the support on which the circuits are made. It is in particular important that, with the exception of the areas of the surface layer of the structure where the electronic devices and electronic elements are made, the rest of the structure is highly resistive or electrically insulating. In addition, it is important to avoid self-heating of electronic devices and, more generally, the rise in temperature of this surface layer. For this, it is important to avoid the presence under this surface layer of a material which is a poor thermal conductor or thermal insulator.
Les dispositifs électroniques en arséniure de gallium (AsGa) peuvent être réalisés sur des Structures constitués d'une plaquette d'AsGa dit semi-isolant, servant de support, recouverte d'une couche épitaxiée d'AsGa apte - à y réaliser les dispositifs désirés. L'utilisation d'une plaquette d'AsGa comme support présente plusieurs inconvénients qui sont : leur coût élevé, leur limitation de taille (diamètre de 150 mm au maximum) , leur mauvaise adaptation à la réalisation de circuits intégrés complexes et leur mauvaise conductibilité thermique.Gallium arsenide (AsGa) electronic devices can be produced on Structures made up of a semi-insulating AsGa plate, serving as support, covered with a epitaxial layer of AsGa suitable - to make the desired devices there. The use of an AsGa plate as a support has several drawbacks which are: their high cost, their size limitation (diameter of 150 mm maximum), their poor adaptation to the production of complex integrated circuits and their poor thermal conductivity .
Le silicium présente une conductibilité thermique qui peut être considérée comme satisfaisante. Cependant, pour rendre le silicium électriquement isolant, il faudrait pouvoir l'élaborer avec une pureté extrême, ce qui est souvent difficile.. Le procédé de fabrication par fusion de zone permet d'obtenir du silicium présentant une isolation électrique satisfaisante. Cependant, ce procédé est coûteux à mettre en œuvre et il ne peut fournir de plaquettes de grande dimension (c'est-à-dire de diamètre supérieur à 150 mm) .The silicon has a thermal conductivity which can be considered satisfactory. However, to make the silicon electrically insulating, it would be necessary to be able to develop it with extreme purity, which is often difficult. The zone fusion manufacturing method makes it possible to obtain silicon having satisfactory electrical insulation. However, this method is expensive to implement and it cannot provide large inserts (that is to say with a diameter greater than 150 mm).
Il est connu par ailleurs que la résistivité d'un matériau semiconducteur augmente lorsque ce matériau a été soumis à un flux de particules énergétiques. On peut se reporter à ce sujet aux articles suivants :It is also known that the resistivity of a semiconductor material increases when this material has been subjected to a flow of energetic particles. We can refer to this subject in the following articles:
- "Neutron Transmutation Doping" de H. HERZER, paru dans Proceedings of the Third- "Neutron Transmutation Doping" by H. HERZER, published in Proceedings of the Third
International Symposium on Silicon Materials Science and Technology. Semiconductor Silicon 1977, édité par H.R. HUFF et E. SIRTL, The Electrochemical Society Inc., P.O. Box 2071, Princeton, N.J. 08540, Vol. 77-2, pages 106-115.International Symposium on Silicon Materials Science and Technology. Semiconductor Silicon 1977, edited by H.R. HUFF and E. SIRTL, The Electrochemical Society Inc., P.O. Box 2071, Princeton, N.J. 08540, Vol. 77-2, pages 106-115.
- "The Effect of Fast Neutron Bombardment on the Electrical Properties of p-and n-Type Silicon Carbide" de P. NAGELS et M. DENAYER, 7th. International Conférence on the Physics of Semiconductors . Radiation Damage in Semiconductors, Paris-Royaumont, France, 1964, édité par Dunod, Paris, 1965, pages 225-233.- "The Effect of Fast Neutron Bombardment on the Electrical Properties of p-and n-Type Silicon Carbide" by P. NAGELS and M. DENAYER, 7th. International Conference on the Physics of Semiconductors. Radiation Damage in Semiconductors, Paris-Royaumont, France, 1964, edited by Dunod, Paris, 1965, pages 225-233.
L'augmentation de la résistivité des matériaux semiconducteurs soumis à un flux de particules résulte de la création de défauts (déplacements atomiques) qui se traduisent par des niveaux profonds (pièges) dans la bande interdite de semiconducteur. Lorsque la densité de ces centres est plus élevée que la densité de dopants (niveaux peu profonds) , le niveau de Fer i se retrouve figé à une valeur proche de celle des niveaux profonds résultant de l'irradiation et rendant ainsi le matériau isolant.The increase in the resistivity of semiconductor materials subjected to a flow of particles results from the creation of defects (atomic displacements) which result in deep levels (traps) in the forbidden semiconductor band. When the density of these centers is higher than the density of dopants (shallow levels), the level of Iron i is frozen at a value close to that of the deep levels resulting from irradiation and thus rendering the material insulating.
Ce phénomène d'augmentation de la résistivité des matériaux semiconducteurs soumis à irradiation a été étudié pour la raison qu'il est gênant pour la tenue des composants aux radiations . Les défauts créés perturbent en effet notablement les caractéristiques de ces composants (résistivités , piégeage des porteurs, dégradation de la mobilité des porteurs) .This phenomenon of increasing the resistivity of semiconductor materials subjected to irradiation has been studied for the reason that it is troublesome for the resistance of the components to radiation. The faults created significantly disturb the characteristics of these components (resistivity, trapping of the carriers, degradation of the mobility of the carriers).
Exposé de 1 ' inventionStatement of the invention
Afin de résoudre les problèmes liés aux structures de l'art antérieur formées d'une couche semiconductrice ou d'éléments électroniques tels que des puces sur un support isolant, les inventeurs de la présente invention ont eu l'idée d'utiliser le phénomène d'augmentation de la résistivité des matériaux semiconducteurs soumis à irradiation pour obtenir des supports satisfaisants. Ils ont donc mis à profit un phénomène considéré jusqu'à présent comme un inconvénient .In order to solve the problems associated with the structures of the prior art formed of a semiconductor layer or of electronic elements such as chips on an insulating support, the inventors of the present invention had the idea of using the phenomenon of increase in the resistivity of semiconductor materials subjected to irradiation to obtain satisfactory supports. They have therefore taken advantage of a phenomenon hitherto considered a disadvantage.
Il est à noter que les défauts ainsi créés dans le silicium, et plus encore dans le carbure de silicium, sont très stables en .température, ce qui permet de garder le caractère isolant même après recuit. De plus, en raison de sa large bande interdite et de la profondeur des niveaux de pièges créés, le carbure de silicium devenu isolant peut le rester jusqu'à des températures élevées de fonctionnement des dispositifs élaborés dans la couche semiconductrice superficielle (par exemple 200 à 300°C, voire plus) ou plus généralement des dispositifs électroniques. La présente invention permet ainsi de fournir des structures comportant une couche semiconductrice et/ou des éléments électroniques reposant sur un support qui est à la fois électriquement isolant et bon conducteur thermique. On entend par éléments électroniques tous les éléments actifs et/ou passifs éventuellement regroupés sous forme de puces et rapportés par exemple par les techniques de "Flip Chip" sur un support isolant . Un autre avantage de la présente invention est que le support et la couche semiconductrice superficielle pouvant être réalisés à partir du même matériau de base, il ne se pose pas de problème dû à des différences de coefficient de dilatation thermique entre ces parties de structure.It should be noted that the defects thus created in the silicon, and even more in the carbide of silicon, are very stable in .temperature, which allows to keep the insulating character even after annealing. In addition, because of its wide forbidden band and the depth of the trap levels created, the silicon carbide that has become insulating can remain so until high operating temperatures of the devices developed in the surface semiconductor layer (for example 200 to 300 ° C or more) or more generally electronic devices. The present invention thus makes it possible to provide structures comprising a semiconductor layer and / or electronic elements resting on a support which is both electrically insulating and good thermal conductor. The term “electronic elements” is understood to mean all the active and / or passive elements possibly grouped together in the form of chips and reported for example by “Flip Chip” techniques on an insulating support. Another advantage of the present invention is that the support and the surface semiconductor layer being able to be produced from the same base material, there is no problem due to differences in coefficient of thermal expansion between these structural parts.
L'invention a donc pour objet un procédé de fabrication d'une structure comportant une couche semiconductrice et/ou au moins un élément électronique sur un support électriquement isolant, comprenant une étape d'irradiation d'une plaquette de matériau semiconducteur par des particules susceptibles de rendre électriquement isolant ce matériau semiconducteur par création de défauts, ladite plaquette irradiée procurant ainsi le support électriquement isolant, caractérisé en ce que la couche semiconductrice et/ou l'élément électronique sont rapportés sur la plaquette irradiée.The subject of the invention is therefore a method of manufacturing a structure comprising a semiconductor layer and / or at least one electronic element on an electrically insulating support, comprising a step of irradiating a wafer of semiconductor material with particles susceptible to make this semiconductor material electrically insulating by creating defects, said irradiated plate thus providing the electrically insulating support, characterized in that the layer semiconductor and / or the electronic element are attached to the irradiated wafer.
L'étape d'irradiation peut être mise en œuvre sur une plaquette de matériau semiconducteur possédant une conductibilité thermique considérée comme satisfaisante .The irradiation step can be implemented on a wafer of semiconductor material having a thermal conductivity considered to be satisfactory.
Le matériau semiconducteur de la plaquette peut être soumis à une irradiation de neutrons, d'électrons, d'ions, de particules α, etc.. L'énergie de ces particules est choisie de façon que l'ensemble du volume de la plaquette, ou une proportion significative de celui-ci, soit irradié. La dose d'irradiation est choisie de façon que la résistivité finale du support soit suffisamment élevée pour l'application désirée.The semiconductor material of the wafer can be subjected to irradiation of neutrons, electrons, ions, α particles, etc. The energy of these particles is chosen so that the entire volume of the wafer, or a significant proportion of it, either irradiated. The irradiation dose is chosen so that the final resistivity of the support is high enough for the desired application.
La couche semiconductrice peut être obtenue à partir d'une plaquette complémentaire de matériau semiconducteur collée sur la plaquette irradiée, ladite plaquette complémentaire étant amincie pour fournir ladite couche rapportée. Elle peut aussi être obtenue à partir d'une plaquette complémentaire de matériau semiconducteur dans laquelle la couche semiconductrice a été définie par une couche de microcavités générées par implantation ionique, la plaquette complémentaire étant collée sur la plaquette irradiée puis clivée au niveau de la couche de microcavités pour ne conserver que la couche semiconductrice sur la plaquette irradiée. De préférence, le clivage de la plaquette complémentaire est obtenu par la coalescence des microcavités résultant d'un traitement thermique. La couche rapportée peut également être obtenue à partir d'une plaquette complémentaire de matériau semiconducteur dans laquelle a été définie une couche intermédiaire permettant de séparer la couche semiconductrice du reste de la plaquette complémentaire, cette couche .intermédiaire étant attaquable sélectivement par rapport à ladite couche semiconductrice et au reste de la plaquette complémentaire ou apte à être arrachée mécaniquement du reste de la plaquette complémentaire après que celle-ci ait été collée sur la plaquette irradiée. Cette couche intermédiaire est obtenue par exemple par attaque anodique d'une plaquette initiale destinée à constituer la plaquette complémentaire, cette attaque anodique produisant une couche poreuse formant la couche intermédiaire, la couche semicondouctrice étant constituée par épitaxie réalisée sur la couche intermédiaire. Avantageusement, le collage de ladite plaquette complémentaire sur ladite plaquette irradiée est obtenu par adhésion moléculaire. Avantageusement, les surfaces à coller ont subi une préparation permettant de favoriser leur collage par adhésion moléculaire. Le procédé peut comprendre aussi l'interposition d'une couche intermédiaire entre la plaquette irradiée et la plaquette complémentaire afin d'améliorer le collage.The semiconductor layer can be obtained from a complementary wafer of semiconductor material bonded to the irradiated wafer, said complementary wafer being thinned to provide said added layer. It can also be obtained from a complementary wafer of semiconductor material in which the semiconductor layer has been defined by a layer of microcavities generated by ion implantation, the complementary wafer being glued to the irradiated wafer and then cleaved at the layer of microcavities to keep only the semiconductor layer on the irradiated wafer. Preferably, the cleavage of the complementary wafer is obtained by the coalescence of the microcavities resulting from a heat treatment. The added layer can also be obtained from a complementary wafer of semiconductor material in which an intermediate layer has been defined making it possible to separate the semiconductor layer from the rest of the wafer complementary, this .intermediate layer being selectively attackable with respect to said semiconductor layer and to the rest of the complementary wafer or capable of being torn off mechanically from the rest of the complementary wafer after it has been bonded to the irradiated wafer. This intermediate layer is obtained for example by anodic attack of an initial wafer intended to constitute the complementary wafer, this anodic attack producing a porous layer forming the intermediate layer, the semiconductor layer being formed by epitaxy carried out on the intermediate layer. Advantageously, the bonding of said complementary wafer to said irradiated wafer is obtained by molecular adhesion. Advantageously, the surfaces to be bonded have undergone a preparation making it possible to promote their bonding by molecular adhesion. The method can also include the interposition of an intermediate layer between the irradiated wafer and the complementary wafer in order to improve bonding.
Lorsque la couche semiconductrice est une couche rapportée sur la plaquette irradiée, elle peut avoir été au préalable au moins partiellement traitée pour y élaborer au moins un composant électronique.When the semiconductor layer is a layer added to the irradiated wafer, it may have been previously at least partially treated to develop at least one electronic component therein.
L'invention a aussi pour objet une structure comportant une couche semiconductrice et/ou au moins un élément électronique sur un support électriquement isolant, le support isolant comportant un matériau semiconducteur dont la résistivité a été augmentée par irradiation au moyen de particules, caractérisée en ce que la couche semiconductrice et/ou 1 ' élément électronique sont des éléments rapportés sur la plaquette irradiée. Le matériau semiconducteur du support isolant peut être choisi pour posséder une conductibilité thermique - considérée comme satisfaisante .The invention also relates to a structure comprising a semiconductor layer and / or at least one electronic element on an electrically insulating support, the insulating support comprising a semiconductor material whose resistivity has been increased by irradiation by means of particles, characterized in that that the semiconductor layer and / or one electronic element are elements added to the irradiated wafer. The semiconductor material of the insulating support can be chosen to have a thermal conductivity - considered satisfactory.
La couche semiconductrice peut comporter au moins un composant électronique réalisé totalement ou partiellement. La structure peut comprendre en outre une couche intermédiaire entre le support électriquement isolant et la couche semiconductrice. La couche semiconductrice peut être en un matériau choisi parmi le silicium, 1 ' arseniure de gallium, le carbure de silicium et le phosphure d'indium. Le support électriquement isolant peut être en un matériau choisi parmi le silicium et le carbure de silicium.The semiconductor layer may comprise at least one electronic component produced totally or partially. The structure may further comprise an intermediate layer between the electrically insulating support and the semiconductor layer. The semiconductor layer can be made of a material chosen from silicon, gallium arsenide, silicon carbide and indium phosphide. The electrically insulating support can be made of a material chosen from silicon and silicon carbide.
Brève description des dessinsBrief description of the drawings
L'invention sera mieux comprise et d'autres avantages et particularités apparaîtront à la lecture de la description qui va suivre, donnée à titre d'exemple non limitatif, accompagnée des dessins annexés parmi lesquels :The invention will be better understood and other advantages and features will appear on reading the description which follows, given by way of nonlimiting example, accompanied by the appended drawings among which:
- la figure 1 représente, en vue transversale, une plaquette de matériau semiconducteur au cours de l'étape d'irradiation du procédé selon 1 ' invention, - la figure 2 représente, en vue transversale, une structure comportant une couche semiconductrice sur un support électriquement isolant selon la présente invention,- Figure 1 shows, in transverse view, a wafer of semiconductor material during the irradiation step of the process according to the invention, - Figure 2 shows, in transverse view, a structure comprising a semiconductor layer on a support electrically insulating according to the present invention,
- la figure 3 illustre un mode de mise en œuvre de la présente invention,FIG. 3 illustrates an embodiment of the present invention,
- la figure 4 représente, en vue transversale, la structure obtenue après avoir mis en œuvre le procédé illustré par la figure 3,FIG. 4 represents, in transverse view, the structure obtained after having implemented the method illustrated by FIG. 3,
- la figure 5 illustre un mode de mise en œuvre de la présente invention pour lequel des composants électroniques ont été réalisés dans la couche semiconductrice avant son report sur le support irradié,- Figure 5 illustrates an embodiment of the present invention for which electronic components were produced in the semiconductor layer before it was transferred to the irradiated support,
- la figure 6 représente, en vue transversale, la structure obtenue après avoir mis en œuvre le procédé illustré par la figure 5,FIG. 6 represents, in transverse view, the structure obtained after having implemented the method illustrated by FIG. 5,
- la figure 7 représente, en vue transversale, une structure selon l'invention comportant des éléments électroniques sur un support électriquement isolant.- Figure 7 shows, in transverse view, a structure according to the invention comprising electronic elements on an electrically insulating support.
Description détaillée de modes de réalisation de 1 ' inventionDetailed description of embodiments of the invention
Pour réaliser le support électriquement isolant et pour certaines applications de conductibilité thermique satisfaisante, on peut partir d'une plaquette de matériau semiconducteur classique, disponible selon les tailles et la qualité voulues et de résistivité usuelle. A titre d'exemple, on peut citer le silicium qui possède une conductibilité thermique de 1,5 W/cm.K, le carbure de silicium soit monocristallin soit polycristallin possédant une conductibilité thermique de 4,5 et 3 W/cm.K respectivement.To produce the electrically insulating support and for certain applications of satisfactory thermal conductivity, it is possible to start from a plate of conventional semiconductor material, available according to the desired sizes and quality and of usual resistivity. By way of example, mention may be made of silicon which has a thermal conductivity of 1.5 W / cm.K, the silicon carbide either monocrystalline or polycrystalline having a thermal conductivity of 4.5 and 3 W / cm.K respectively .
Pour rendre la plaquette isolante électriquement on l'irradie avec un flux de particules de façon à créer des défauts dans le réseau cristallin. C'est ce que représente la figure 1 qui montre une plaquette de matériau semiconducteur 1 soumise à une irradiation de particules représentée par les flèches 2. Les défauts cristallins créés ont pour effet d'augmenter très fortement la résistivité électrique du matériau semiconducteur. L'irradiation est de p-référence réalisée au moyen d'un flux de neutrons comportant une proportion élevée de neutrons énergétiques qui sont efficaces pour la création des défauts voulus. On entend par neutrons énergétiques ceux qui vont des neutrons épithermiques jusqu'aux neutrons rapides, soit une gamme d'énergie allant de quelques eV à quelques MeV, par opposition aux neutrons thermiques (de quelques eV à quelques eV) qui sont moins efficaces pour la création de défauts et qui génèrent des transmutations. Selon l'invention, l'irradiation est faite dans des conditions très différentes de celles utilisées dans la technique dite de "neutron transmutation doping" où l'on favorise le rapport inverse puisque l'on cherche à éviter la création de défauts et à maximaliser les transmutations pour, par exemple, transformer l'isotope 30 du silicium en phosphore. L'irradiation peut être réalisée dans un réacteur nucléaire, de type piscine par exemple, ou au moyen d'un générateur de neutrons utilisant les réactions nucléaires d'un faisceau de particules chargées avec une cible. On peut utiliser dans, ce cas un faisceau d'ions deutériu bombardant une cible tritiée.To make the wafer electrically insulating, it is irradiated with a flow of particles so as to create defects in the crystal lattice. This is shown in Figure 1 which shows a wafer of semiconductor material 1 subjected to particle irradiation represented by the arrows 2. The crystal defects created have the effect of greatly increasing the electrical resistivity of the semiconductor material. The irradiation is of p-reference carried out by means of a neutron flux comprising a high proportion of energetic neutrons which are effective for the creation of the desired defects. By energy neutrons is meant those which go from epithermal neutrons to fast neutrons, that is to say a range of energy going from a few eV to a few MeV, as opposed to thermal neutrons (from a few eV to a few eV) which are less efficient for creation of faults and which generate transmutations. According to the invention, the irradiation is carried out under conditions very different from those used in the technique called "neutron transmutation doping" where the reverse ratio is favored since it is sought to avoid the creation of defects and to maximize transmutations to, for example, transform the isotope 30 of silicon into phosphorus. The irradiation can be carried out in a nuclear reactor, of the pool type for example, or by means of a neutron generator using the nuclear reactions of a beam of charged particles with a target. One can use in this case a beam of deuterium ions bombarding a tritiated target.
L'irradiation de la plaquette serai- conductrice avec un flux intégré suffisant de neutrons énergétiques, de l'ordre de 2.1015 à 5.1016 neutrons/cm2, crée suffisamment de défauts pour qu'il soit très difficile de les recuire au cours des traitements thermiques postérieurs que la structure peut subir au cours de son utilisation. On peut noter que l'irradiation peut aussi être réalisée sur le lingot, la découpe du lingot et son conditionnement sous forme de plaquettes étant réalisés par la suite.The irradiation of the conductive wafer with a sufficient integrated flux of energetic neutrons, of the order of 2.10 15 to 5.10 16 neutrons / cm 2 , creates enough defects that it is very difficult to anneal them during subsequent heat treatments that the structure can undergo during its use. It can be noted that the irradiation can also be carried out on the ingot, the cutting of the ingot and its packaging in the form of plates being carried out thereafter.
Une dose de neutrons énergétiques de 1017 neutrons/cm2 permet d'obtenir une résistivité supérieure à 104 Ω.cm dans le -carbure de silicium quelle que soit la résistivité de départ. Pour "le silicium, une dose de 1015 neutrons/cm2 permet d'obtenir une résistivité supérieure à 105 Ω.cm, ce qui permet d'utiliser comme matériau semiconducteur du silicium ' obtenu par la méthode de Czochralski.A dose of energetic neutrons of 10 17 neutrons / cm 2 makes it possible to obtain a resistivity greater than 10 4 Ω.cm in the silicon carbide whatever the initial resistivity. For " silicon, a dose of 10 15 neutrons / cm 2 makes it possible to obtain a resistivity greater than 10 5 Ω.cm, which makes it possible to use as semiconductor material silicon ' obtained by the Czochralski method.
Après irradiation, l'ensemble de la plaquette est dans un état de forte résistivité et, telle quelle, est impropre à la réalisation de dispositifs électroniques.After irradiation, the entire wafer is in a state of high resistivity and, as it is, is unsuitable for the production of electronic devices.
Si la plaquette de matériau semiconducteur irradiée est par exemple en carbure de silicium, la couche semiconductrice destinée à 1 ' élaboration de composants électroniques est rapportée sur la plaquette irradiée. On obtient la structure 3, représentée à la figure 2, constitué d'un support isolant 1 auquel adhère la couche semiconductrice 4.If the wafer of irradiated semiconductor material is for example made of silicon carbide, the semiconductor layer intended for producing electronic components is attached to the irradiated wafer. This gives structure 3, shown in FIG. 2, consisting of an insulating support 1 to which the semiconductor layer 4 adheres.
La couche semiconductrice peut être rendue adhérente au support isolant par collage. Ce mode de mise en œuvre est illustré par la figure 3 qui montre la mise en contact adhérent du support isolant 1 (par exemple en silicium ou en SiC) avec une plaquette semiconductrice 10 (par exemple en Si, AsGa, SiC) destinée à fournir la couche semiconductrice. La mise en contact adhérent peut se faire au moyen d'une substance adhésive. Elle peut également se faire par la technique d'adhésion moléculaire. Dans ce cas, on peut utiliser une couche intermédiaire 11 pour assurer une meilleure qualité du collage et/ou de meilleures propriétés d'interface entre le support isolant et la couche semiconductrice superficielle de la future structure.The semiconductor layer can be made adherent to the insulating support by bonding. This mode of implementation is illustrated by FIG. 3 which shows the adherent contact of the insulating support 1 (for example in silicon or in SiC) with a semiconductor wafer 10 (for example in Si, AsGa, SiC) intended to supply the semiconductor layer. Adherent contacting can be done by means of an adhesive substance. It can also be done by the molecular adhesion technique. In this case, an intermediate layer 11 can be used to ensure better quality of bonding and / or better interface properties between the insulating support and the surface semiconductor layer of the future structure.
L'épaisseur de la couche semiconductrice de la structure doit être une fraction de l'épaisseur de la plaquette semiconductrice 10. Sur la figure 3, la future couche semiconductrice est délimitée par la ligne en traits interrompus 12.The thickness of the semiconductor layer of the structure must be a fraction of the thickness of the semiconductor wafer 10. In Figure 3, the future semiconductor layer is delimited by the dashed line 12.
Une fois le collage réalisé, la partie non désirée de la plaquette semiconductrice 10 est éliminée. Différentes méthodes peuvent être utilisées pour parvenir à ce résultat. On peut utiliser la rectification, l'attaque chimique, le polissage. On peut aussi utiliser le procédé de clivage divulgué par le document FR-A-2 681 472 et qui présente l'avantage de conserver la partie non désirée de la plaquette 10 sous une forme réutilisable. Ce procédé implique que la plaquette 10 a subi au préalable une implantation ionique qui a permis de générer une couche de microcavités le long de la ligne 12. Une fois le collage des plaquettes 1 et 10 réalisé, le clivage est obtenu par un traitement thermique approprié.Once bonding has been carried out, the unwanted part of the semiconductor wafer 10 is eliminated. Different methods can be used to achieve this result. We can use grinding, etching, polishing. One can also use the cleavage process disclosed in document FR-A-2 681 472 and which has the advantage of preserving the unwanted part of the wafer 10 in a reusable form. This process implies that the wafer 10 has previously undergone an ion implantation which has made it possible to generate a layer of microcavities along the line 12. Once the bonding of the wafers 1 and 10 has been carried out, the cleavage is obtained by an appropriate heat treatment. .
Une fois éliminée la partie non désirée de la plaquette 10 on obtient la structure représentée à la figure 4, c'est-à-dire une structure 13 formée d'un support isolant 1, d'une couche intermédiaire 11 et d'une couche semiconductrice superficielle 14. Cette structure peut par exemple comprendre un support 1 en silicium rendu électriquement isolant supportant une couche 11 d'oxyde de silicium qui supporte elle-même une couche superficielle 14 de silicium apte à l'élaboration de composants électroniques. Un polissage final permet éventuellement de parfaire l'état de surface de la couche superficielle 14.Once the unwanted part of the plate 10 has been eliminated, the structure shown in FIG. 4 is obtained, that is to say a structure 13 formed of an insulating support 1, an intermediate layer 11 and a layer surface semiconductor 14. This structure may for example comprise a support 1 made of electrically insulating silicon supporting a layer 11 of silicon oxide which itself supports a surface layer 14 of silicon suitable for the production of electronic components. A final polishing optionally makes it possible to perfect the surface condition of the surface layer 14.
Le collage peut permettre la mise en place sur le support isolant d'une couche semiconductrice dans laquelle on a réalisé, partiellement ou complètement, des composants électroniques. C'est ce que représente la figure 5 qui montre la mise en contact adhérent du support isolant 1 avec une plaquette semiconductrice 20 par l'intermédiaire d'une couche intermédiaire 11 de collage. La référence 21 représente des composants électroniques qui ont été réalisés à partir de la face 22 de la plaquette semiconductrice 20. La future couche semiconductrice de la structure est délimitée par la ligne en traits interrompus 23.Bonding can allow the establishment on the insulating support of a semiconductor layer in which electronic components have been produced, partially or completely. This is shown in Figure 5 which shows the adhesive contact of the insulating support 1 with a semiconductor wafer 20 via a intermediate bonding layer 11. The reference 21 represents electronic components which have been produced from the face 22 of the semiconductor wafer 20. The future semiconductor layer of the structure is delimited by the line in dashed lines 23.
Une fois le collage réalisé, la partie non désirée de la plaquette semiconductrice 20 est éliminée, par exemple par l'une des méthodes mentionnées plus haut. On obtient alors la structure représentée à la figure 6, c'est-à-dire une structure 24 formée d'un support isolant 1, d'une couche intermédiaire 11 et d'une couche semiconductrice superficielle 25 contenant des composants électroniques 21.Once bonding has been carried out, the unwanted part of the semiconductor wafer 20 is eliminated, for example by one of the methods mentioned above. The structure shown in FIG. 6 is then obtained, that is to say a structure 24 formed of an insulating support 1, an intermediate layer 11 and a surface semiconductor layer 25 containing electronic components 21.
La figure 7 représente une structure 30 selon 1 ' invention comportant cette fois le support isolant 1 sur une face duquel ont été reportés directement des éléments électroniques 31, par exemple des puces électroniques FIG. 7 represents a structure 30 according to the invention this time comprising the insulating support 1 on one face of which electronic elements 31, for example electronic chips have been transferred directly

Claims

REVENDICATIONS
1. Procédé de fabrication d'une structure (13,24,30) comportant une couche semiconductrice1. Method for manufacturing a structure (13,24,30) comprising a semiconductor layer
(14,25) et/ou au moins un élément électronique (21,31) sur un support électriquement isolant (1) , comprenant une étape d'irradiation d'une plaquette de matériau semiconducteur par des particules susceptibles de rendre électriquement isolant ce matériau semiconducteur par création de défauts, ladite plaquette irradiée procurant ainsi le support électriquement isolant (1) , caractérisé en ce que la couche semiconductrice (14,25) et/ou l'élément électronique (21,31) sont rapportés sur la plaquette irradiée .(14,25) and / or at least one electronic element (21,31) on an electrically insulating support (1), comprising a step of irradiating a wafer of semiconductor material with particles capable of making this material electrically insulating semiconductor by creation of defects, said irradiated wafer thus providing the electrically insulating support (1), characterized in that the semiconductor layer (14,25) and / or the electronic element (21,31) are attached to the irradiated wafer.
2. Procédé selon la revendication 1, caractérisé en ce que l'étape d'irradiation est mise en oeuvre sur une plaquette de matériau semiconducteur possédant une conductibilité thermique considérée comme satisfaisante .2. Method according to claim 1, characterized in that the irradiation step is implemented on a wafer of semiconductor material having a thermal conductivity considered to be satisfactory.
3. Procédé selon l'une des revendications 1 ou 2, caractérisé en ce que les particules de l'étape d'irradiation sont choisies parmi un ou plusieurs types de particules parmi les neutrons, les électrons, les ions, les particules α.3. Method according to one of claims 1 or 2, characterized in that the particles of the irradiation step are chosen from one or more types of particles from neutrons, electrons, ions, α particles.
4. Procédé selon la revendication 1, caractérisé en ce que la couche semiconductrice (14,25) est obtenue à partir d'une plaquette complémentaire de matériau semiconducteur (10,20) collée sur la plaquette irradiée (1) , ladite plaquette complémentaire étant amincie pour fournir ladite couche rapportée.4. Method according to claim 1, characterized in that the semiconductor layer (14,25) is obtained from a complementary wafer of semiconductor material (10,20) bonded to the irradiated wafer (1), said complementary wafer being thinned to provide said added layer.
5. Procédé selon la revendication 4, caractérisé en ce que la couche semiconductrice (14,25) est obtenue à partir d'une plaquette complémentaire de matériau semiconducteur (10,20) dans laquelle la couche semiconductrice a été définie par une couche de microcavités générées par implantation ionique, la plaquette complémentaire étant collée sur la plaquette irradiée (1) puis clivée au niveau de la couche de microcavités pour ne conserver que la couche semiconductrice sur la plaquette irradiée.5. Method according to claim 4, characterized in that the semiconductor layer (14,25) is obtained from a complementary wafer of semiconductor material (10,20) in which the semiconductor layer has been defined by a layer of microcavities generated by ion implantation, the additional wafer being glued to the irradiated wafer (1) and then cleaved at the level of the microcavity layer to keep only the semiconductor layer on the irradiated wafer.
6. Procédé selon la revendication 5, caractérisé en ce que le clivage de la plaquette complémentaire (10,20) est obtenu par la coalescence des microcavités résultant d'un traitement thermique.6. Method according to claim 5, characterized in that the cleavage of the complementary plate (10,20) is obtained by the coalescence of the microcavities resulting from a heat treatment.
7. Procédé selon la revendication 1, caractérisé en ce que la couche semiconductrice est obtenue à partir d'une plaquette complémentaire de matériau semiconducteur dans laquelle a été définie une couche intermédiaire permettant de séparer la couche semiconductrice du reste de la plaquette complémentaire, cette couche intermédiaire étant attaquable sélectivement par rapport à ladite couche semiconductrice et au reste de la plaquette complémentaire ou étant apte à être arrachée mécaniquement du reste de la plaquette complémentaire après que celle-ci ait été collée sur la plaquette irradiée . 7. Method according to claim 1, characterized in that the semiconductor layer is obtained from a complementary wafer of semiconductor material in which an intermediate layer has been defined making it possible to separate the semiconductor layer from the rest of the complementary wafer, this layer intermediate being selectively attackable with respect to said semiconductor layer and to the rest of the complementary wafer or being able to be mechanically torn from the rest of the complementary wafer after it has been glued to the irradiated wafer.
8. Procédé selon la revendication 7, caractérisé en ce que la couche intermédiaire est obtenue par attaque anodique d'une plaquette initiale destinée à constituer la plaquette complémentaire, cette attaque anodique produisant une couche poreuse formant ladite couche intermédiaire, ladite couche semiconductrice étant constituée par épitaxie réalisée sur la couche intermédiaire.8. Method according to claim 7, characterized in that the intermediate layer is obtained by anodic attack of an initial wafer intended to constitute the complementary wafer, this anodic attack producing a porous layer forming said intermediate layer, said semiconductor layer being constituted by epitaxy performed on the intermediate layer.
9. Procédé selon l'une quelconque des revendications 4 à 8, caractérisé en ce que le collage de ladite plaquette complémentaire (10,20) sur ladite plaquette irradiée est obtenu par adhésion moléculaire.9. Method according to any one of claims 4 to 8, characterized in that the bonding of said complementary wafer (10,20) on said irradiated wafer is obtained by molecular adhesion.
10. Procédé selon la revendication 9, caractérisé en ce que les surfaces à coller ont subi une préparation permettant de favoriser leur collage' par adhésion moléculaire.10. Method according to claim 9, characterized in that the surfaces to be bonded have undergone a preparation making it possible to promote their bonding ' by molecular adhesion.
11. Procédé selon la revendication 9, caractérisé en ce qu'il comprend l'interposition d'une couche intermédiaire (11) entre la plaquette irradiée (1) et la plaquette complémentaire (10,20) afin d'améliorer le collage.11. Method according to claim 9, characterized in that it comprises the interposition of an intermediate layer (11) between the irradiated plate (1) and the complementary plate (10,20) in order to improve bonding.
12. Procédé selon l'une quelconque des revendications 1 à 11, caractérisé en ce que la couche semiconductrice a été, avant d'être rapportée sur la plaquette irradiée, au moins partiellement traitée pour y élaborer au moins un composant électronique (21) .12. Method according to any one of claims 1 to 11, characterized in that the semiconductor layer has been, before being attached to the irradiated wafer, at least partially treated to develop therein at least one electronic component (21).
13. Structure (13,24,30) comportant une couche semiconductrice (14,25) et/ou au moins un élément électronique (21,31) sur un support électriquement isolant (1) , le support isolant (1) comportant un matériau semiconducteur dont la résistivité a été augmentée par irradiation au moyen de particules, caractérisée en ce que la couche semiconductrice (14,25) et/ou l'élément électronique (21,31) sont des éléments rapportés sur la plaquette irradiée .13. Structure (13,24,30) comprising a semiconductor layer (14,25) and / or at least one electronic element (21,31) on an electrically insulating support (1), the insulating support (1) comprising a material semiconductor whose resistivity has been increased by irradiation by means of particles, characterized in that the semiconductor layer (14,25) and / or the electronic element (21,31) are elements added to the irradiated wafer.
14. Structure selon la revendication 13, caractérisée en ce que le matériau semiconducteur du support isolant possède une conductibilité thermique considérée comme satisfaisante.14. Structure according to claim 13, characterized in that the semiconductor material of the insulating support has a thermal conductivity considered to be satisfactory.
15. Structure selon la revendication 13, caractérisée en ce que la couche semiconductrice (25) est une couche rapportée comportant au moins un composant électronique (21) réalisé totalement ou partiellement. 15. Structure according to claim 13, characterized in that the semiconductor layer (25) is an added layer comprising at least one electronic component (21) produced totally or partially.
16. Structure selon l'une quelconque des revendications 13 à 15, caractérisée en ce qu'elle comprend en outre une couche intermédiaire (11) entre le support électriquement isolant (1) et la couche semiconductrice (14, 25) .16. Structure according to any one of claims 13 to 15, characterized in that it further comprises an intermediate layer (11) between the electrically insulating support (1) and the semiconductor layer (14, 25).
17. Structure selon l'une quelconque des revendications 13 à 16, caractérisée en ce que la couche semiconductrice (4, 14, 25) est en un matériau choisi parmi le silicium, 1 ' arseniure de gallium, le carbure de silicium et le phosphure d'indium.17. Structure according to any one of claims 13 to 16, characterized in that the semiconductor layer (4, 14, 25) is made of a material chosen from silicon, gallium arsenide, silicon carbide and phosphide indium.
18. Structure selon l'une quelconque des revendications 13 à 17 , caractérisée en ce que le support électriquement isolant (1) est en un matériau choisi parmi le silicium et le carbure de silicium. 18. Structure according to any one of claims 13 to 17, characterized in that the electrically insulating support (1) is made of a material chosen from silicon and silicon carbide.
PCT/FR1999/002529 1998-10-20 1999-10-18 Structure comprising a semiconductor layer and/or electronic elements on an insulating support and method for making same WO2000024054A1 (en)

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FR9813135A FR2784794A1 (en) 1998-10-20 1998-10-20 Electronic structure, especially an IC chip, has an insulating support formed by particle irradiation of a semiconductor wafer
FR98/13135 1998-10-20

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