WO2000026916A1 - Device and method in an integrated circuit (ic) module for buffering clocks and other input signals - Google Patents

Device and method in an integrated circuit (ic) module for buffering clocks and other input signals Download PDF

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Publication number
WO2000026916A1
WO2000026916A1 PCT/US1999/025837 US9925837W WO0026916A1 WO 2000026916 A1 WO2000026916 A1 WO 2000026916A1 US 9925837 W US9925837 W US 9925837W WO 0026916 A1 WO0026916 A1 WO 0026916A1
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WO
WIPO (PCT)
Prior art keywords
buffering
module
signal
circuit
receiving
Prior art date
Application number
PCT/US1999/025837
Other languages
French (fr)
Inventor
Roland Ochoa
Joe B. Olson
Original Assignee
Micron Electronics, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Electronics, Inc. filed Critical Micron Electronics, Inc.
Publication of WO2000026916A1 publication Critical patent/WO2000026916A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Definitions

  • TECHNICAL FIELD This invention relates in general to integrated circuit (IC) modules, such as multi-chip modules (MCMs), Single In-Line Memory Modules (SIMMs), and Dual In- Line Memory Modules (DIMMs). More specifically, this invention relates to a device and method for buffering clocks and other input signals received by IC modules.
  • MCMs multi-chip modules
  • SIMMs Single In-Line Memory Modules
  • DIMMs Dual In- Line Memory Modules
  • a typical IC module 10 includes a set of IC devices 12 that communicate with external electronic devices (not shown) through a set of input/output (I/O) pins 14.
  • Each of the IC devices 12 has characteristic high and low voltage "trip" points V IH and V IL at which each device 12 will register, respectively, high and low states in an input signal.
  • each of the IC devices 12 has characteristic minimum “setup” and “hold” times that characterize required minimum timing relationships between certain input signals.
  • amplitude fluctuations during high-to-low or low-to-high transitions in input signals received by the IC module 10 e.g., clock signals, Row
  • An integrated circuit (IC) module in accordance with this invention includes a module terminal (e.g., an input/output (I/O) pin) that receives a signal (e.g., a clock).
  • a buffering circuit in a buffering IC of IC module then buffers the signal, and an IC device (e.g., a DRAM) in the IC module then receives and uses the buffered signal.
  • the signal may, for example, be delayed slightly, have improved rise and fall times, and have reduced amplitude fluctuations, all of which may contribute to improved setup and hold times when the buffered signal is received and used by the IC device.
  • the improved setup and hold times may, in turn, lead to improved yields (because more IC modules pass testing), and reduced manufacturing costs.
  • the IC module described above is embodied in a SIMM, DIMM, an MCM, or an electronic system.
  • a signal in an IC module is prepared for use by an IC device of the IC module.
  • the signal is initially received at the IC module (e.g., at an I/O pin of the IC module).
  • a buffering circuit in a buffering IC provided in the IC module then buffers the signal, and the buffered signal is then conducted to the IC device for its use.
  • an IC module is manufactured using an IC module substrate that has multiple module terminals (e.g., I/O pins) on its surface. Multiple IC devices are mounted on the surface of the IC module substrate, along with a buffering IC that includes a buffering circuit. The buffering circuit is then electrically interposed between one of the module terminals and one of the IC devices so a signal received at the module terminal is buffered by the buffering circuit before reaching the IC device.
  • module terminals e.g., I/O pins
  • FIG. 1 is an isometric top view of a conventional integrated circuit (IC) module
  • FIG. 2 is an isometric top view of an IC module in accordance with this invention
  • FIG. 3 is a circuit schematic illustrating a buffer circuit of the IC module of
  • FIG. 4 is a timing diagram illustrating an input clock signal buffered by the buffer circuit of FIG. 3;
  • FIG. 5 is a block diagram illustrating an electronic system incorporating the IC module of FIG. 2.
  • an integrated circuit (IC) module 20 in accordance with this invention includes a group of IC devices 22 mounted on a module substrate 23 that receive and output signals through a set of input/output (I/O) pins 24.
  • I/O input/output
  • the IC module 20 is illustrated in FIG. 2 as comprising a Dual In-Line Memory Module (DIMM), it may, instead, comprise a Single In-Line Memory Module (SIMM), a Multi- Chip Module (MCM), or any other type of IC module.
  • DIMM Dual In-Line Memory Module
  • SIMM Single In-Line Memory Module
  • MCM Multi- Chip Module
  • each of the IC devices may comprise any type of IC device including, for example, a Dynamic Random Access Memory (DRAM), a Static RAM (SRAM), a Synchronous DRAM (SDRAM), a Video RAM (VRAM), a Synch-Link DRAM (SLDRAM), or a RAMbus-type DRAM.
  • DRAM Dynamic Random Access Memory
  • SRAM Static RAM
  • SDRAM Synchronous DRAM
  • VRAM Video RAM
  • SLDRAM Synch-Link DRAM
  • RAMbus-type DRAM RAMbus-type DRAM.
  • a buffering IC 26 is electrically interposed between the IC devices 22 and the I/O pins 24 in order to buffer various input signals (e.g., clock, RAS, CAS, OE, WE, and DQ signals) received at the I/O pins 24 before those signals are conducted to the IC devices 22.
  • various input signals e.g., clock, RAS, CAS, OE, WE, and DQ signals
  • the buffering IC 26 may be packaged in a variety of ways, and that this invention is not limited to a buffering IC 26 packaged in the manner illustrated in FIG. 2.
  • a buffering circuit 30 of the buffering IC 26 receives an input clock CLK, buffers the input clock CLK through buffers 32 and 34 as a result of a "jumper" laser fuse 36 having previously been blown during manufacturing of the IC 26, and outputs a buffered clock CLK' through another jumper laser fuse 38 (which has not been blown), thereby bypassing another buffer 40.
  • the buffering IC 26 may contain multiple buffering circuits 30, one for each of a plurality of input signals.
  • the buffers 32, 34, and 40 may be implemented using a wide variety of circuitry including, for example, a chain of inverters.
  • non- volatile elements other than the jumper laser fuses 36 and 38 may be used in connection with this invention including, for example, zero-ohm resistors, antifuse circuits, and flash EEPROM cells.
  • the buffering circuit 30 may comprise any number of buffers and non-volatile elements in series, and that these non- volatile elements may be programmed in a wide variety of ways to achieve the buffering desired.
  • buffering generally denotes a process by which the rise and/or fall times of the edges of a signal are reduced, amplitude fluctuations in the signal are reduced or eliminated, and/or some delay is introduced into the signal.
  • buffering generally denotes a process by which the rise and/or fall times of the edges of a signal are reduced, amplitude fluctuations in the signal are reduced or eliminated, and/or some delay is introduced into the signal.
  • other common meanings may be attributed to the term “buffering,” and are intended to be included within the scope of this invention.
  • the unbuffered input clock CLK provides a Row Address to Clock setup time t ASC that may not meet minimum setup time specifications of the IC devices 22 (FIG. 2).
  • the delay afforded by buffering the input clock CLK through both of the buffers 32 and 34 provides an increased setup time t ASC ' that is more likely to meet the minimum setup time specifications of the IC devices 22 (FIG. 2).
  • the unbuffered input clock CLK fluctuates before settling below the trip point V IL , and therefore provides a Clock to Row Address hold time T RAH that may not meet minimum hold time specifications of the IC devices 22 (FIG. 2).
  • the sharp falling edge provided by the buffered clock CLK' provides a Clock to Row Address hold time T, ⁇ ' that is more likely to meet the minimum hold time specifications of the IC devices 22 (FIG. 2).
  • the present invention is applicable to any input signal, and is not limited to clock signals. It will also be understood that multiple buffering circuits 30 (FIG.
  • an electronic system 50 of this invention includes an input device 52, an output device 54, a processor device 56, and a memory device 58 that incorporates the IC module 20 of FIG. 2. It will be understood, of course, that any one of the input, output, and processor devices 52, 54, and 56 may also incorporate the IC module 20 of FIG. 2.
  • the input device 52 may be, for example, a keyboard, a mouse, a trackball, a touch pad, a transducer, a musical instrument, or any other input device.
  • the output device 54 may be, for example, a display screen or monitor, a television screen, a printer, a speaker, a musical instrument, a transducer, an actuator, or any other output device.
  • the processor device 56 may be, for example, any conventional general purpose single- or multi-chip microprocessor such as a Pentium ® processor, a Pentium ® Pro processor, a Pentium ® II processor, an 8051 processor, a MIPS ® processor, a Power PC ® processor, an ALPHA ® processor, or any of the AMD ® or Cyrix ® lines of processors.
  • the processor device 56 may be, for example, any conventional special purpose microprocessor such as a digital signal processor or a graphics processor.

Abstract

An integrated circuit (IC) module, such as a Single In-Line Memory Module (SIMM), Dual In-Line Memory Module (DIMM), or Multi-Chip Module (MCM), includes a buffering IC that buffers clocks and other input signals received by the IC module. As a result of the buffering, the setup and hold times associated with these input signals are improved, thereby improving yields.

Description

DEVICE AND METHOD IN AN INTEGRATED CIRCUIT (IC) MODULE FOR BUFFERING CLOCKS AND OTHER INPUT SIGNALS
TECHNICAL FIELD This invention relates in general to integrated circuit (IC) modules, such as multi-chip modules (MCMs), Single In-Line Memory Modules (SIMMs), and Dual In- Line Memory Modules (DIMMs). More specifically, this invention relates to a device and method for buffering clocks and other input signals received by IC modules.
BACKGROUND As shown in FIG. 1, a typical IC module 10 includes a set of IC devices 12 that communicate with external electronic devices (not shown) through a set of input/output (I/O) pins 14. Each of the IC devices 12 has characteristic high and low voltage "trip" points VIH and VIL at which each device 12 will register, respectively, high and low states in an input signal. In addition, each of the IC devices 12 has characteristic minimum "setup" and "hold" times that characterize required minimum timing relationships between certain input signals.
In some instances, amplitude fluctuations during high-to-low or low-to-high transitions in input signals received by the IC module 10 (e.g., clock signals, Row
Address Strobe (RAS), Column Address Strobe (CAS), Output Enable (OE), and Write Enable (WE)), in combination with a relatively high trip point VIH or a relatively low trip point VIL in an IC device 12, can cause the IC module 10 to fail during testing as a result of a failure of the device 12 to register a transition in one of these input signals. In other instances, the same fluctuations experienced by an IC device 12 that has a relatively large minimum setup or hold time can vary the timing relationships between certain input signals enough to also cause the IC module 10 to fail during testing. In both instances, the failing IC module 10 is typically repaired or scrapped, thereby reducing the yield and increasing the overall costs associated with manufacturing modules such as the IC module 10.
Accordingly, it would be desirable to have a device and method for IC modules that reduce or eliminate these amplitude fluctuations in input signals provided to the modules in order to improve their yield and reduce manufacturing costs. DISCLOSURE OF INVENTION An integrated circuit (IC) module in accordance with this invention includes a module terminal (e.g., an input/output (I/O) pin) that receives a signal (e.g., a clock). A buffering circuit in a buffering IC of IC module then buffers the signal, and an IC device (e.g., a DRAM) in the IC module then receives and uses the buffered signal. As a result of the buffering, the signal may, for example, be delayed slightly, have improved rise and fall times, and have reduced amplitude fluctuations, all of which may contribute to improved setup and hold times when the buffered signal is received and used by the IC device. The improved setup and hold times may, in turn, lead to improved yields (because more IC modules pass testing), and reduced manufacturing costs.
In other embodiments of this invention, the IC module described above is embodied in a SIMM, DIMM, an MCM, or an electronic system.
In a further embodiment of this invention, a signal in an IC module is prepared for use by an IC device of the IC module. The signal is initially received at the IC module (e.g., at an I/O pin of the IC module). A buffering circuit in a buffering IC provided in the IC module then buffers the signal, and the buffered signal is then conducted to the IC device for its use.
In still another embodiment, an IC module is manufactured using an IC module substrate that has multiple module terminals (e.g., I/O pins) on its surface. Multiple IC devices are mounted on the surface of the IC module substrate, along with a buffering IC that includes a buffering circuit. The buffering circuit is then electrically interposed between one of the module terminals and one of the IC devices so a signal received at the module terminal is buffered by the buffering circuit before reaching the IC device.
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is an isometric top view of a conventional integrated circuit (IC) module; FIG. 2 is an isometric top view of an IC module in accordance with this invention; FIG. 3 is a circuit schematic illustrating a buffer circuit of the IC module of
FIG. 2; FIG. 4 is a timing diagram illustrating an input clock signal buffered by the buffer circuit of FIG. 3; and
FIG. 5 is a block diagram illustrating an electronic system incorporating the IC module of FIG. 2.
BEST MODES FOR CARRYING OUT THE INVENTION As shown in FIG. 2, an integrated circuit (IC) module 20 in accordance with this invention includes a group of IC devices 22 mounted on a module substrate 23 that receive and output signals through a set of input/output (I/O) pins 24. It will be understood by those having skill in the technical field of this invention that while the IC module 20 is illustrated in FIG. 2 as comprising a Dual In-Line Memory Module (DIMM), it may, instead, comprise a Single In-Line Memory Module (SIMM), a Multi- Chip Module (MCM), or any other type of IC module. Also, it will be understood that each of the IC devices may comprise any type of IC device including, for example, a Dynamic Random Access Memory (DRAM), a Static RAM (SRAM), a Synchronous DRAM (SDRAM), a Video RAM (VRAM), a Synch-Link DRAM (SLDRAM), or a RAMbus-type DRAM.
A buffering IC 26 is electrically interposed between the IC devices 22 and the I/O pins 24 in order to buffer various input signals (e.g., clock, RAS, CAS, OE, WE, and DQ signals) received at the I/O pins 24 before those signals are conducted to the IC devices 22. It will be understood that the buffering IC 26 may be packaged in a variety of ways, and that this invention is not limited to a buffering IC 26 packaged in the manner illustrated in FIG. 2.
As shown in FIG. 3, a buffering circuit 30 of the buffering IC 26 (FIG. 2) receives an input clock CLK, buffers the input clock CLK through buffers 32 and 34 as a result of a "jumper" laser fuse 36 having previously been blown during manufacturing of the IC 26, and outputs a buffered clock CLK' through another jumper laser fuse 38 (which has not been blown), thereby bypassing another buffer 40. It will be understood, of course, that the buffering IC 26 (FIG. 2) may contain multiple buffering circuits 30, one for each of a plurality of input signals. It will also be understood that the buffers 32, 34, and 40 may be implemented using a wide variety of circuitry including, for example, a chain of inverters. Further, it will be understood that non- volatile elements other than the jumper laser fuses 36 and 38 may be used in connection with this invention including, for example, zero-ohm resistors, antifuse circuits, and flash EEPROM cells. In addition, it will be understood that while three buffers and two nonvolatile elements are illustrated in FIG. 3, the buffering circuit 30 may comprise any number of buffers and non-volatile elements in series, and that these non- volatile elements may be programmed in a wide variety of ways to achieve the buffering desired.
Furthermore, it should be understood that the term "buffering" generally denotes a process by which the rise and/or fall times of the edges of a signal are reduced, amplitude fluctuations in the signal are reduced or eliminated, and/or some delay is introduced into the signal. Of course, other common meanings may be attributed to the term "buffering," and are intended to be included within the scope of this invention.
As shown in FIG. 4, the unbuffered input clock CLK provides a Row Address to Clock setup time tASC that may not meet minimum setup time specifications of the IC devices 22 (FIG. 2). In contrast, the delay afforded by buffering the input clock CLK through both of the buffers 32 and 34 (FIG. 3) provides an increased setup time tASC' that is more likely to meet the minimum setup time specifications of the IC devices 22 (FIG. 2).
Similarly, the unbuffered input clock CLK fluctuates before settling below the trip point VIL, and therefore provides a Clock to Row Address hold time TRAH that may not meet minimum hold time specifications of the IC devices 22 (FIG. 2). In contrast, the sharp falling edge provided by the buffered clock CLK' provides a Clock to Row Address hold time T,^' that is more likely to meet the minimum hold time specifications of the IC devices 22 (FIG. 2). Of course, it will be understood that the present invention is applicable to any input signal, and is not limited to clock signals. It will also be understood that multiple buffering circuits 30 (FIG. 3) in the buffering IC 26 may be used to provide varying degrees of buffering, as necessary, for multiple input signals by programming the nonvolatile elements in the individual buffering circuit 30 associated with each such signal. As shown in FIG. 5, an electronic system 50 of this invention includes an input device 52, an output device 54, a processor device 56, and a memory device 58 that incorporates the IC module 20 of FIG. 2. It will be understood, of course, that any one of the input, output, and processor devices 52, 54, and 56 may also incorporate the IC module 20 of FIG. 2.
The input device 52 may be, for example, a keyboard, a mouse, a trackball, a touch pad, a transducer, a musical instrument, or any other input device. The output device 54 may be, for example, a display screen or monitor, a television screen, a printer, a speaker, a musical instrument, a transducer, an actuator, or any other output device. Also, the processor device 56 may be, for example, any conventional general purpose single- or multi-chip microprocessor such as a Pentium® processor, a Pentium® Pro processor, a Pentium® II processor, an 8051 processor, a MIPS® processor, a Power PC® processor, an ALPHA® processor, or any of the AMD® or Cyrix® lines of processors. In addition, the processor device 56 may be, for example, any conventional special purpose microprocessor such as a digital signal processor or a graphics processor.
Although this invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods that operate according to the principles of the invention as described.

Claims

1. An integrated circuit (IC) module comprising: a module terminal for receiving a signal; a buffering IC having a buffering circuit coupled to the module terminal for buffering the signal; and an IC device coupled to the buffering circuit for receiving the buffered signal.
2. The IC module of claim 1 , wherein the module terminal comprises an input/output (I/O) pin.
3. The IC module of claim 2, wherein the I/O pin receives a clock signal.
4. The IC module of claim 1, wherein the buffering circuit of the buffering IC includes a plurality of series-connected buffers.
5. The IC module of claim 4, wherein the buffering circuit of the buffering IC further includes a plurality of series-connected non-volatile elements, each coupled in parallel with one of the buffers.
6. The IC module of claim 5, wherein the non-volatile elements comprise laser fuses.
7. A Single In-Line Memory Module (SIMM) comprising: at least one module terminal for receiving a signal; a buffering IC having at least one buffering circuit coupled to the module terminal for buffering the signal; and a plurality of IC memory devices, each coupled to the buffering circuit for receiving the buffered input signal.
8. A Dual In-Line Memory Module (DIMM) comprising: at least one module terminal for receiving a signal; a buffering IC having at least one buffering circuit coupled to the module terminal for buffering the signal; and a plurality of IC memory devices, each coupled to the buffering circuit for receiving the buffered input signal.
9. A Multi-Chip Module (MCM) comprising: at least one module terminal for receiving a signal; a buffering IC having at least one buffering circuit coupled to the module terminal for buffering the signal; and a plurality of IC devices, each coupled to the buffering circuit for receiving the buffered input signal.
10. An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, memory, and processor devices including an integrated circuit (IC) module comprising: a module terminal for receiving a signal; a buffering IC having a buffering circuit coupled to the module terminal for buffering the signal; and an IC device coupled to the buffering circuit for receiving the buffered signal.
11. A method of preparing a signal in an integrated circuit (IC) module for use by an IC device of the IC module, the method comprising: receiving the signal at the IC module; providing a buffering IC in the IC module that includes a buffering circuit for buffering the signal; buffering the signal using the buffering circuit of the buffering IC; and conducting the buffered signal to the IC device.
12. The method of claim 11 , wherein the act of receiving the signal at the IC module comprises receiving the signal at an input/output (I/O) pin of the IC module.
13. The method of claim 11, further comprising the act of programming the buffering circuit to buffer the signal in a selected manner.
14. The method of claim 13, wherein the act of programming the buffering circuit comprises programming a plurality of non- volatile elements of the buffering circuit.
15. The method of claim 14, wherein the act of programming the plurality of non-volatile elements comprises blowing one or more laser fuses of the buffering circuit.
16. The method of claim 11 , wherein the act of buffering the signal comprises: reducing rise and fall times of edges of the signal; delaying the signal; and reducing fluctuations in the amplitude of the signal.
17. A method of manufacturing an integrated circuit (IC) module, the method comprising: providing an IC module substrate with a plurality of module terminals thereon; mounting a plurality of IC devices on a surface of the IC module substrate; mounting a buffering IC that includes a buffering circuit on the surface of the IC module substrate; and electrically interposing the buffering circuit of the buffering IC between at least one of the module terminals and at least one of the IC devices such that a signal received at the at least one module terminal is buffered by the buffering circuit before reaching the at least one IC device.
18. The method of claim 17, further comprising the act of programming the buffering circuit to buffer the signal in a selected manner.
19. The method of claim 18, wherein the act of programming the buffering circuit comprises programming a plurality of non- volatile elements of the buffering circuit.
20. The method of claim 19, wherein the act of programming the plurality of non-volatile elements comprises programming one or more laser fuses of the buffering circuit.
PCT/US1999/025837 1998-11-04 1999-11-03 Device and method in an integrated circuit (ic) module for buffering clocks and other input signals WO2000026916A1 (en)

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US09/185,880 US6347394B1 (en) 1998-11-04 1998-11-04 Buffering circuit embedded in an integrated circuit device module used for buffering clocks and other input signals
US09/185,880 1998-11-04

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Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
JP3914651B2 (en) * 1999-02-26 2007-05-16 エルピーダメモリ株式会社 Memory module and manufacturing method thereof
KR100403342B1 (en) * 2001-09-13 2003-11-01 주식회사 하이닉스반도체 A timing control circuit of a semiconductor device
KR100418524B1 (en) * 2001-10-06 2004-02-11 삼성전자주식회사 digitally controllable internal clock generating circuit in semiconductor memory device and method therefore
US7026708B2 (en) * 2001-10-26 2006-04-11 Staktek Group L.P. Low profile chip scale stacking system and method
US7656678B2 (en) * 2001-10-26 2010-02-02 Entorian Technologies, Lp Stacked module systems
US7202555B2 (en) * 2001-10-26 2007-04-10 Staktek Group L.P. Pitch change and chip scale stacking system and method
US6956284B2 (en) * 2001-10-26 2005-10-18 Staktek Group L.P. Integrated circuit stacking system and method
US7485951B2 (en) * 2001-10-26 2009-02-03 Entorian Technologies, Lp Modularized die stacking system and method
US6576992B1 (en) * 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
US7371609B2 (en) * 2001-10-26 2008-05-13 Staktek Group L.P. Stacked module systems and methods
US6797998B2 (en) * 2002-07-16 2004-09-28 Nvidia Corporation Multi-configuration GPU interface device
US7234099B2 (en) * 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US7646649B2 (en) * 2003-11-18 2010-01-12 International Business Machines Corporation Memory device with programmable receivers to improve performance
US7182634B2 (en) * 2004-06-29 2007-02-27 Intel Corporation Connector cell having a supported conductive extension
US7547213B2 (en) * 2004-08-26 2009-06-16 Micron Technology, Inc. Memory modules and methods for manufacturing memory modules
US20060261449A1 (en) * 2005-05-18 2006-11-23 Staktek Group L.P. Memory module system and method
US7511968B2 (en) * 2004-09-03 2009-03-31 Entorian Technologies, Lp Buffered thin module system and method
US7468893B2 (en) * 2004-09-03 2008-12-23 Entorian Technologies, Lp Thin module system and method
US20060050492A1 (en) * 2004-09-03 2006-03-09 Staktek Group, L.P. Thin module system and method
US7443023B2 (en) * 2004-09-03 2008-10-28 Entorian Technologies, Lp High capacity thin module system
US7760513B2 (en) * 2004-09-03 2010-07-20 Entorian Technologies Lp Modified core for circuit module system and method
US7324352B2 (en) * 2004-09-03 2008-01-29 Staktek Group L.P. High capacity thin module system and method
US7606050B2 (en) * 2004-09-03 2009-10-20 Entorian Technologies, Lp Compact module system and method
US20060049513A1 (en) * 2004-09-03 2006-03-09 Staktek Group L.P. Thin module system and method with thermal management
US7606040B2 (en) * 2004-09-03 2009-10-20 Entorian Technologies, Lp Memory module system and method
US7606049B2 (en) * 2004-09-03 2009-10-20 Entorian Technologies, Lp Module thermal management system and method
US7289327B2 (en) * 2006-02-27 2007-10-30 Stakick Group L.P. Active cooling methods and apparatus for modules
US7423885B2 (en) * 2004-09-03 2008-09-09 Entorian Technologies, Lp Die module system
US20060055024A1 (en) * 2004-09-14 2006-03-16 Staktek Group, L.P. Adapted leaded integrated circuit module
US20060072297A1 (en) * 2004-10-01 2006-04-06 Staktek Group L.P. Circuit Module Access System and Method
US20060118936A1 (en) * 2004-12-03 2006-06-08 Staktek Group L.P. Circuit module component mounting system and method
US7200021B2 (en) * 2004-12-10 2007-04-03 Infineon Technologies Ag Stacked DRAM memory chip for a dual inline memory module (DIMM)
KR100697270B1 (en) * 2004-12-10 2007-03-21 삼성전자주식회사 Low power multiple chip semiconductor memory device and chip enable method thereof
US20060175693A1 (en) * 2005-02-04 2006-08-10 Staktek Group, L.P. Systems, methods, and apparatus for generating ball-out matrix configuration output for a flex circuit
US20060244114A1 (en) * 2005-04-28 2006-11-02 Staktek Group L.P. Systems, methods, and apparatus for connecting a set of contacts on an integrated circuit to a flex circuit via a contact beam
US20060250780A1 (en) * 2005-05-06 2006-11-09 Staktek Group L.P. System component interposer
US7511969B2 (en) * 2006-02-02 2009-03-31 Entorian Technologies, Lp Composite core circuit module system and method
JP1528936S (en) * 2015-01-14 2015-07-13
JP1528485S (en) * 2015-01-14 2015-07-13
JP1528484S (en) * 2015-01-14 2015-07-13

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0571099A1 (en) * 1992-05-19 1993-11-24 Sun Microsystems, Inc. Bus architecture for integrated data and video memory
US5532954A (en) * 1992-05-19 1996-07-02 Sun Microsystems, Inc. Single in-line memory module
US5539349A (en) * 1994-03-24 1996-07-23 Hitachi Microsystems, Inc. Method and apparatus for post-fabrication ascertaining and providing programmable precision timing for sense amplifiers and other circuits
EP0744748A2 (en) * 1995-05-15 1996-11-27 Silicon Graphics, Inc. High memory capacity DIMM with data and state memory
US5680342A (en) * 1996-04-10 1997-10-21 International Business Machines Corporation Memory module package with address bus buffering
EP0840448A2 (en) * 1996-10-29 1998-05-06 Texas Instruments Incorporated A setup/hold time delay network

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459846A (en) 1988-12-02 1995-10-17 Hyatt; Gilbert P. Computer architecture system having an imporved memory
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
JP2715009B2 (en) 1991-05-16 1998-02-16 三菱電機株式会社 Dynamic random access memory device
JP2695078B2 (en) * 1991-06-10 1997-12-24 株式会社東芝 Data processing device clock signal distribution method
US5566127A (en) 1992-01-15 1996-10-15 Motorola, Inc. Method for building a compiled static RAM
US5615355A (en) 1992-10-22 1997-03-25 Ampex Corporation Method and apparatus for buffering a user application from the timing requirements of a DRAM
US5600802A (en) 1994-03-14 1997-02-04 Apple Computer, Inc. Methods and apparatus for translating incompatible bus transactions
AU1989395A (en) 1994-03-14 1995-10-03 Apple Computer, Inc. A peripheral processor card for upgrading a computer
JP3177094B2 (en) 1994-05-31 2001-06-18 富士通株式会社 Semiconductor storage device
US5572482A (en) 1994-11-28 1996-11-05 Motorola, Inc. Block architected static RAM configurable for different word widths and associated method for forming a physical layout of the static RAM
US5666321A (en) 1995-09-01 1997-09-09 Micron Technology, Inc. Synchronous DRAM memory with asynchronous column decode
US5909375A (en) * 1996-04-10 1999-06-01 Altera Corporation Buffer for identification of pin contentions in circuit design and simulation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0571099A1 (en) * 1992-05-19 1993-11-24 Sun Microsystems, Inc. Bus architecture for integrated data and video memory
US5532954A (en) * 1992-05-19 1996-07-02 Sun Microsystems, Inc. Single in-line memory module
US5539349A (en) * 1994-03-24 1996-07-23 Hitachi Microsystems, Inc. Method and apparatus for post-fabrication ascertaining and providing programmable precision timing for sense amplifiers and other circuits
EP0744748A2 (en) * 1995-05-15 1996-11-27 Silicon Graphics, Inc. High memory capacity DIMM with data and state memory
US5680342A (en) * 1996-04-10 1997-10-21 International Business Machines Corporation Memory module package with address bus buffering
EP0840448A2 (en) * 1996-10-29 1998-05-06 Texas Instruments Incorporated A setup/hold time delay network

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