WO2000035020A1 - Lateral high-voltage semiconductor component with reduced specific closing resistor - Google Patents

Lateral high-voltage semiconductor component with reduced specific closing resistor Download PDF

Info

Publication number
WO2000035020A1
WO2000035020A1 PCT/DE1999/003823 DE9903823W WO0035020A1 WO 2000035020 A1 WO2000035020 A1 WO 2000035020A1 DE 9903823 W DE9903823 W DE 9903823W WO 0035020 A1 WO0035020 A1 WO 0035020A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
semiconductor
lateral high
zone
semiconductor regions
Prior art date
Application number
PCT/DE1999/003823
Other languages
German (de)
French (fr)
Inventor
Peter Nelle
Wolfgang Werner
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2000035020A1 publication Critical patent/WO2000035020A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Definitions

  • the present invention relates to a lateral high-voltage semiconductor component with reduced specific on-resistance, with a semiconductor substrate of the first conductivity type, on which an at least one active zone semiconductor layer of the second conductivity type opposite to the first conductivity type is provided, and in particular a lateral high-voltage MOS transistor with a drain zone of the second conductivity type, a source zone of the second conductivity type and a body zone of the first conductivity type surrounding the source zone, the drain zone, the source zone and the body zone being provided in the semiconductor layer, and with a gate electrode in the region above the body zone, a drain electrode and a source electrode, and preferably with a surface zone of the first conductivity type, which is provided in the region between the drain zone and the body zone in the semiconductor layer.
  • n- or p-type layer has a doping dose that is below the breakdown charge. In silicon, the doping dose is therefore less than 10 12 charge carriers cm "2 (see also JA Appels et al. IEDM Tech. Dig. 1979, p. 238).
  • the n- or p-type layer can be a trough of one type of conduction or an epitaxial layer of the same type of conduction.
  • the trough is in a semiconductor region of the other, for one type of conduction opposite conductivity type, while the epitaxial layer is on a semiconductor substrate of the other conductivity type.
  • a typical lateral high-voltage n-channel DMOS transistor is described below with reference to FIG. 8 as an example of such an existing lateral high-voltage MOS transistor.
  • the specified line types can - as in the entire description below - also be reversed.
  • n-type epitaxial layer 2 On a p-type silicon substrate 1 there is an n-type epitaxial layer 2 (or an n-type trough), the doping dose of which is 10 12 charge carriers cm -2 .
  • a suitable dopant is, for example, phosphorus.
  • An n + -conducting drain zone 3 and an n + -conducting source zone 4 are introduced into the epitaxial layer 2 at a distance from one another, the source zone 4 being surrounded by a p-type body or semiconductor body zone 5.
  • the p-type semiconductor regions are hatched, while the n-type semiconductor regions are shown as unshaded for better clarity, as are insulating layers.
  • the drain zone 3 is connected to a drain electrode 6, while a source electrode 7 is adjacent to the surfaces of the source zone 4 and the body zone 5.
  • a gate electrode 10 made of, for example, doped polycrystalline silicon.
  • Suitable materials for the drain electrode 6 and the source electrode 7 are, for example, aluminum or likewise polycrystalline doped silicon. Are 500 V on the drain electrode 6, for example
  • the on-resistance Ron of such a lateral high-voltage field-effect transistor is now decisively determined by the distance between source 4 and drain 3 and the layer resistance of epitaxial layer 2. For example, if the source-drain distance is approximately 65 ⁇ m and the epitaxial layer 2 has a doping dose of 1 ⁇ 10 12 charge carriers cm -2 , the values of the on-resistance Ron are approximately 27 ohm mm “2 .
  • This on-resistance Ron can be reduced by a maximum of one
  • the surface layer 12 can float, that is to say be floating. However, it is also possible to connect this surface layer 12 (not shown in FIG. 9) to the body zone 5. Lateral high-voltage MOS transistors, as shown in FIGS. 8 and 9, can be integrated in bipolar technology or in MOS technology (cf. also US Pat. No. 5,432,370).
  • This object is achieved according to the invention in a lateral high-voltage semiconductor component of the type mentioned at the outset in that semiconductor regions of the second conductivity type and of the first conductivity type are alternately provided in the semiconductor layer between the surface thereof and the semiconductor substrate, the semiconductor regions with the exception of those adjacent to the semiconductor substrate.
  • a surface zone of the first or second conductivity type in the semiconductor layer is doped with a dose of about ax 10 12 charge carriers cm "2 .
  • an additional zone in the form of a surface zone is therefore not only provided in the semiconductor layer formed, for example, by an epitaxial layer or a tub, as in the prior art; Rather, according to the invention, several semiconductor regions consisting of sequences of n- and p-conducting layers with doses of, for example, 2 ⁇ 10 12 or also 4 ⁇ 10 12 charge carriers cm "2 are installed in the semiconductor layer. These semiconductor regions are cleared up for example, a MOS transistor with a high applied source-drain reverse voltage with respect to their charge carriers.
  • the semiconductor regions are preferably implemented by high-voltage ion implantations of, for example, boron and phosphorus at different acceleration voltages.
  • Such high-voltage ion implantations allow penetration depths of the semiconductor regions of approximately 1 to 20 ⁇ m, preferably 2 to 5 ⁇ m, with relatively high doping doses.
  • the semiconductor regions are produced as thin n- and p-conducting layers, each with a dose of approximately 2a x 10 12 charge carriers cm "2 , the uppermost semiconductor region directly below an insulating layer having a dose of approximately ax 10 12 charge carriers cm -2 has (0.5 ⁇ a ⁇ 50).
  • the top layer can be either n- or p-doped. With boron implantation, for example, the formation of three p-conductive regions is readily possible.
  • the lowermost, n-conducting layer made of the semiconductor substrate has a doping concentration which is so low that the maximum drain voltage can be absorbed.
  • this dose is less than (a to 2a) x 10 12 and, for example, 1 x 10 12 charge carriers cm -2 .
  • the exact values of the respective doping doses can be determined, for example, by simulation.
  • the semiconductor regions can of course form lateral npn and pnp structures.
  • the semiconductor regions of the first conduction type are preferably connected via the body zone to the source body region, in order in this way to rapidly switch from a blocking state in which the space charge zone in the semiconductor regions alternately has different conduction types is to enable a live state. Because of this connection between the p-type regions and the body zone, the original hole concentration and thus charge neutrality of the p-type regions is not restored via thermal generation, but rather quickly through hole conduction from the source body region.
  • the layouts of the lateral high-voltage semiconductor component according to the invention can be carried out in a wide variety of forms.
  • a single transistor is possible in which drains are oval in an elongated shape and are surrounded by the semiconductor regions and source.
  • Meandering or comb structures for drain or source are also possible.
  • Other conceivable structures consist of hexagonal honeycombs, in the center of which there is a drain, while source is provided in a star shape between three adjacent "honeycombs".
  • doping / or damage implantation which reduces the charge carrier life, for example with platinum or gold or molybdenum or damage implantation by means of helium or electrons or protons, can advantageously be carried out in the region of these semiconductor regions be made.
  • This doping / age which reduces the charge carrier life, not only promotes the recombination of the charge carriers, but also the charge carrier generation in the semiconductor regions, which leads to an acceleration of the switching times of the lateral high-voltage MOS transistor.
  • the specific on-resistance Ron is generally inversely proportional to the number of semiconductor regions lying on top of one another and alternately of different conductivity types.
  • a Ron win of, for example, a factor of 3 to 5 can easily be achieved.
  • the source zone, drain zone, optionally isolation zones and the semiconductor regions of a MOS transistor as a semiconductor component are alternately produced using alternately different types of conduction solely by masked high-voltage ion implantations and subsequent RTA, then additional epitaxial layers, for example by low-temperature epitaxy, with layer thicknesses of approximately 4 ⁇ m and above are deposited, which in turn is followed by the generation of the regions of alternately different conduction types by high-voltage ion implantation and RTA. In this way it is possible to reduce the layer thickness of the semiconductor regions. alternately different types of cables to increase significantly beyond the specified about 6 microns and to realize much greater layer thicknesses that reduce the on-resistance Ron by a multiple.
  • the insulating layers would have to be composed of a thin, low-temperature furnace oxide and deposited silicon dioxide or other dielectric layers of high quality.
  • a particularly advantageous development of the lateral high-voltage semiconductor component according to the invention consists in that the dose in the semiconductor regions is alternately staggered laterally, which has a stabilizing influence on the breakdown strength of the component.
  • This lateral dose graduation can be achieved by using different implantation masks and different implantation energies.
  • V-MOS structures cf. US Pat. No. 4,754,310 and US Pat. No. 5,216,275.
  • the RTA need not be applied. Rather, it is possible to use conventional high-temperature furnace processes and then only to provide one implantation mask. The desired annoyance of the individual areas according to n or p can then be achieved by means of lateral diffusion through various cutouts. The invention is explained in more detail below with reference to the drawings. Show it:
  • FIG. 1 shows a section through a first exemplary embodiment of a lateral high-voltage MOS
  • FIG. 2 shows a section through a second exemplary embodiment of a lateral high-voltage MOS transistor with a body connection
  • FIGS. 3a to 3c different layouts for a lateral high-voltage MOS transistor according to the invention
  • FIG. 4 shows a sectional view to explain an ion implantation with different implantation masks
  • FIG. 6 shows a section through a V-MOS transistor with laterally varying dopings
  • FIG. 7 implantation profiles of boron and phosphorus in silicon with different implantation energies
  • Figure 9 shows a section through another existing lateral high-voltage MOS transistor.
  • FIG. 1 shows a sectional view through a lateral high-voltage MOS transistor according to a first exemplary embodiment of the invention. To clarify the illustration, not all cut parts are shown hatched, as in the following sectional views.
  • the lateral high-voltage MOS transistor differs from the existing lateral high-voltage MOS transistor essentially in that additional p-conducting semiconductor regions 14, which alternate with n-conducting semiconductor regions 13, in the region between drain 3 and source 4 are provided. These semiconductor regions 13, 14, which together with the surface zone 12 form a pn layer sequence, have a dose of approximately 2a ⁇ 10 12, for example
  • the technical implementation of the layer sequences from the semiconductor regions 13, 14 and the surface zone 12 is preferably carried out by high-voltage ion implantation of for example, boron and phosphor made with different acceleration voltages.
  • high-voltage ion implantation of for example, boron and phosphor made with different acceleration voltages.
  • FIG. 7 in which on the abscissa the penetration depth x in ⁇ m of the individual ion implantations and on the ordinate the doping concentration in charge carriers cm "3 for different acceleration voltages between 300 keV and 2000 keV for boron (B) and phosphorus ( P)
  • a dose of ax 10 12 cm "2 is preferred, while the bottom layer, that is to say the semiconductor region 13 adjacent to the silicon substrate 1, is doped so low that the maximum drain voltage can be absorbed.
  • a suitable one for this Dose is (a to 2a) x 10 12 cm '2 .
  • the semiconductor layer 2 can have a doping of less than 1 xx 1100 1122 LLaadduunnggsstträäggeerrnn ccmm --22. However, significantly higher dopings are also possible,
  • FIG. 1 shows an embodiment of a lateral high-voltage MOS transistor according to the invention, in which the p-type semiconductor regions 14 and the surface zone 12 float, these semiconductor regions can also be connected to the source body region, as is done by a p-type tendency semiconductor region 15 in the embodiment of FIG. 2 is shown.
  • this semiconductor region 15 which lies between the p-conducting semiconductor regions 14 or the surface zone 12 and the body zone 5
  • the original hole concentration for charge neutrality in the semiconductor regions 14 or the surface zone 12 is not through thermal generation of charge carriers, but through Hole line restored from the source side, which enables a quick switch from a blocking state to a current-carrying state.
  • the semiconductor regions 13, 14 and the surface zone 12 are floating freely, as is provided in the exemplary embodiment of FIG. 1, it is advantageous in these regions or this zone to have a doping of platinum, gold or, for example, reducing the charge carrier life Molybdenum or a damage implantation by means of helium, electrons or protrons in the area of the np layer sequence, which not only accelerates the recombination of the charge carriers, but also the generation of the charge carriers and thus the switching times of the transistor.
  • the specific switch-on resistance Ron of the lateral high-voltage semiconductor component according to the invention is reduced in proportion to the number of n- and p-type semiconductor regions 13 and 14 used. That is, the more such semiconductor regions 13, 14 are provided with alternately different conductivity types, the lower the specific on-resistance of the lateral high-voltage semiconductor component.
  • 3a to 3c show different layouts for a lateral high-voltage MOS transistor according to the invention.
  • These can NEN provide an elongated drain structure 3, 6, which of the
  • FIG. 3b Other possible structures consist of meandering or comb-shaped structures, as shown in FIG. 3b, or honeycomb-like structures corresponding to the example of FIG. 3c.
  • Different implantation masks 16, 17, 18 are used here, so that, for example, four high-voltage ion implants with implantation energies of, for example, 0.1 or 0.3 or 1 or 2 MeV for four semiconductor regions from the three semiconductor regions 14 and 14 Guide surface zone 12 which have a doping falling from left to right in the lateral direction - corresponding to the schematically illustrated implantation masks 16 to 18.
  • areas 19 there is a dose of the ion implantation without a mask, while in areas 20 this dose is reduced by the shielding effect of the mask 18 and in areas 21 there is a further reduction in the dose corresponding to the shielding effect of the masks 17 and 18.
  • a conventional furnace process can be used instead of the RTA.
  • the desired n or p load can be achieved here by means of lateral diffusion into the recesses 23, as is illustrated in FIG. 5b.
  • the above-explained principle of increasing and decreasing doping in the semiconductor regions 13, 14 can also be used with a VMOS transistor, as is illustrated schematically in FIG. 6.
  • the electron flow is indicated here by arrows 24.
  • n- and p-type semiconductor regions are provided which have cans which mutually clear out the Allow semiconductor regions with regard to their charge carriers when a high reverse voltage is present.
  • the decisive criterion for the doping dose is that the critical field strength at the interfaces between n- and p-conducting semiconductor regions is not exceeded, i.e. that the ionization integral remains less than 1.
  • n- and p-type layered semiconductor regions can be produced over a depth of about 3 to 4 ⁇ m, each with a dose below the critical value mentioned.
  • the uppermost n- or p-type semiconductor region contains only half of the n- or p-dose of the remaining, middle semiconductor regions, since it is only cleared from one side of charge carriers, it being expressly noted that these Dose without further ado - as explained in detail above, can also be larger than 2 x 10 12 charge carriers cm "2 .
  • the lowest semiconductor region, which adjoins the semiconductor substrate, is to be doped so low that it can take up the maximum voltage, for example at the drain.
  • the higher doping dose results in a reduction in the on-resistance Ron with the same blocking properties, for example of a transistor, since this on-resistance decreases in proportion to the higher doping dose.
  • the semiconductor layer can optionally have a doping dose which is significantly higher than 2 x 10 12 charge carriers cm “2 and is, for example, 1 x 10 13 charge carriers cm " 2 . It is only important that the semiconductor regions 13, 14 produced by high-energy implantation mutually compensate each other in their charge and that the critical field strength (cf. above) is not exceeded. If necessary, it is possible, for example, to implant only p-type semiconductor regions and to determine the doping dose of the n-type semiconductor regions by doping the semiconductor layer 2.
  • connection region 15 is doped higher.
  • the invention is advantageously e.g. for MOS transistors, npn or pnp transistors, diodes, J-FETs and IGBTs (bipolar transistor with insulated gate).

Abstract

The invention relates to a lateral high-voltage semiconductor component which is provided with p-conducting and n-conducting layers (13, 14) which extend in a lateral direction. The dose of said layers amounts to 2a x 1012 charge carrier cm-2. Said layers can be provided with a lateral doping concentration profile (a = 0,5 ... 50). The topmost layer is provided with a dose of a x 1012 charge carrier cm-2 while the lowest layer has a dose of (a to 2a) x 1012 charge carrier cm-2. Said semiconductor layers (13, 14) can be floating or can be linked with, e.g. a body source region (5, 4).

Description

Beschreibungdescription
Laterales Hochvolt-Halbleiterbauelement mit reduziertem spezifischem EinschaltwiderstandLateral high-voltage semiconductor component with reduced specific on-resistance
Die vorliegende Erfindung betrifft ein laterales Hochvolt- Halbleiterbauelement mit reduziertem spezifischen Einschaltwiderstand, mit einem Halbleitersubstrat des ersten Leitungstyps, auf dem eine wenigstens eine aktive Zone aufweisende Halbleiterschicht des zweiten, zum ersten Leitungstyp entgegengesetzten Leitungstyps vorgesehen ist, und insbesondere einen lateralen Hochvolt-MOS-Transistor mit einer Drainzone des zweiten Leitungstyps, einer Sourcezone des zweiten Leitungstyps und einer die Sourcezone umgebenden Bodyzone des ersten Leitungstyps, wobei die Drainzone, die Sourcezone und die Bodyzone in der Halbleiterschicht vorgesehen sind, und mit einer Gateelektrode im Bereich oberhalb der Bodyzone, einer Drainelektrode und einer Sourceelektrode, und vorzugsweise mit einer Oberflächenzone des ersten Leitungstyps, die im Bereich zwischen der Drainzone und der Bodyzone in der Halbleiterschicht vorgesehen ist.The present invention relates to a lateral high-voltage semiconductor component with reduced specific on-resistance, with a semiconductor substrate of the first conductivity type, on which an at least one active zone semiconductor layer of the second conductivity type opposite to the first conductivity type is provided, and in particular a lateral high-voltage MOS transistor with a drain zone of the second conductivity type, a source zone of the second conductivity type and a body zone of the first conductivity type surrounding the source zone, the drain zone, the source zone and the body zone being provided in the semiconductor layer, and with a gate electrode in the region above the body zone, a drain electrode and a source electrode, and preferably with a surface zone of the first conductivity type, which is provided in the region between the drain zone and the body zone in the semiconductor layer.
Bestehende laterale Hochvolt-MOS-Transistoren nutzen bekanntlich das sogenannte Resurf-Prinzip aus, bei dem ein lateraler Spannungsabbau längs einer n- oder p-leitenden Schicht zwischen Drain und Source erfolgt. Diese n- oder p-leitende Schicht hat dabei eine Dotierungsdosis, die unterhalb der Durchbruchsladung liegt. In Silizium ist die Dotierungsdosis also kleiner als 1012 Ladungsträger cm"2 (vgl. hierzu auch J. A. Appels et al . IEDM Tech. Dig. 1979, S. 238).Existing lateral high-voltage MOS transistors are known to use the so-called resurf principle, in which a lateral voltage reduction takes place along an n- or p-type layer between drain and source. This n- or p-type layer has a doping dose that is below the breakdown charge. In silicon, the doping dose is therefore less than 10 12 charge carriers cm "2 (see also JA Appels et al. IEDM Tech. Dig. 1979, p. 238).
Bei der n- oder p-leitenden Schicht kann es sich um eine Wanne des einen Leitungstyps oder um eine Epitaxieschicht ebenfalls des einen Leitungstyps handeln. Die Wanne ist dabei in einem Halbleiterbereich des anderen, zum einen Leitungstyp entgegengesetzten Leitungstyps angeordnet, während die Epitaxieschicht sich auf einem Halbleitersubstrat des anderen Leitungstyps befindet.The n- or p-type layer can be a trough of one type of conduction or an epitaxial layer of the same type of conduction. The trough is in a semiconductor region of the other, for one type of conduction opposite conductivity type, while the epitaxial layer is on a semiconductor substrate of the other conductivity type.
Als ein Beispiel eines derartigen bestehenden lateralen Hoch- volt-MOS-Transistors sei im folgenden anhand der Fig. 8 ein üblicher lateraler Hochvolt-n-Kanal-DMOS-Transistor beschrieben. Die angegebenen Leitungstypen können dabei - wie in der folgenden gesamten Beschreibung - auch jeweils umgekehrt sein.A typical lateral high-voltage n-channel DMOS transistor is described below with reference to FIG. 8 as an example of such an existing lateral high-voltage MOS transistor. The specified line types can - as in the entire description below - also be reversed.
Auf einem p-leitenden Siliziu substrat 1 befindet sich eine n-leitende Epitaxieschicht 2 (oder eine n-leitende Wanne) , deren Dotierungsdosis 1012 Ladungsträger cm-2 beträgt. Ein ge- eigneter Dotierstoff ist beispielsweise Phosphor. In die Epitaxieschicht 2 sind im Abstand voneinander eine n+-leitende Drainzone 3 und eine n+-leitende Sourcezone 4 eingebracht, wobei die Sourcezone 4 von einer p-leitenden Body- bzw. Halbleiterkörperzone 5 umgeben ist. In den Figuren sind dabei die p-leitenden Halbleiterbereiche schraffiert, während die n- leitenden Halbleiterbereiche zur besseren Übersichtlichkeit ebenso wie Isolierschichten unschraffiert dargestellt sind.On a p-type silicon substrate 1 there is an n-type epitaxial layer 2 (or an n-type trough), the doping dose of which is 10 12 charge carriers cm -2 . A suitable dopant is, for example, phosphorus. An n + -conducting drain zone 3 and an n + -conducting source zone 4 are introduced into the epitaxial layer 2 at a distance from one another, the source zone 4 being surrounded by a p-type body or semiconductor body zone 5. In the figures, the p-type semiconductor regions are hatched, while the n-type semiconductor regions are shown as unshaded for better clarity, as are insulating layers.
Die Drainzone 3 ist mit einer Drainelektrode 6 verbunden, während an die Oberflächen der Sourcezone 4 und der Bodyzone 5 eine Sourceelektrode 7 angrenzt. Zwischen zwei Isolierschichten 8, 9 aus beispielsweise Siliziumdioxid und/oder Si- liziu nitrid befindet sich oberhalb der Bodyzone 5 und im Abstand von dieser noch eine Gateelektrode 10 aus beispielswei- se dotiertem polykristallinem Silizium. Geeignete Materialien für die Drainelektrode 6 und die Sourceelektrode 7 sind beispielsweise Aluminium oder ebenfalls polykristallines dotiertes Silizium. Liegen an der Drainelektrode 6 beispielsweise 500 V, an derThe drain zone 3 is connected to a drain electrode 6, while a source electrode 7 is adjacent to the surfaces of the source zone 4 and the body zone 5. Between two insulating layers 8, 9 made of silicon dioxide and / or silicon nitride, for example, is located above and at a distance from the body zone 5 a gate electrode 10 made of, for example, doped polycrystalline silicon. Suitable materials for the drain electrode 6 and the source electrode 7 are, for example, aluminum or likewise polycrystalline doped silicon. Are 500 V on the drain electrode 6, for example
Sourceelektrode 0 V und an dem Substrat 1 ebenfalls 0 V, so stellt sich eine Verteilung des elektrischen Feldes ein, wie diese durch Äquipotentiallinien 11 angedeutet ist.Source electrode 0 V and on the substrate 1 also 0 V, a distribution of the electric field is established, as indicated by equipotential lines 11.
Der Einschaltwiderstand Ron eines solchen lateralen Hochvolt- Feldeffekttransistors wird nun maßgeblich durch den Abstand zwischen Source 4 und Drain 3 sowie den Schichtwiderstand der Epitaxieschicht 2 bestimmt. Liegt beispielsweise der Source- Drain-Abstand bei etwa 65 μm und weist die Epitaxieschicht 2 eine Dotierungsdosis von 1 x 1012 Ladungsträger cm-2 auf, so liegen die Werte des Einschaltwiderstandes Ron bei etwa 27 Ohm mm"2.The on-resistance Ron of such a lateral high-voltage field-effect transistor is now decisively determined by the distance between source 4 and drain 3 and the layer resistance of epitaxial layer 2. For example, if the source-drain distance is approximately 65 μm and the epitaxial layer 2 has a doping dose of 1 × 10 12 charge carriers cm -2 , the values of the on-resistance Ron are approximately 27 ohm mm “2 .
Dieser Einschaltwiderstand Ron läßt sich um maximal einenThis on-resistance Ron can be reduced by a maximum of one
Faktor 2 reduzieren, wenn, wie in Fig. 9 gezeigt ist, zusätzlich in der Epitaxieschicht 2 im Bereich zwischen der Sourcezone 4 und der Drainzone 3 noch eine p-leitende Oberflächenschicht 12 vorgesehen wird. Damit wird die Epitaxieschicht 2 nicht nur von der Seite des Siliziumsubstrates 1 aus an Ladungsträgern ausgeräumt. Vielmehr erfolgt ein solches Ausräumen an Ladungsträgern auch von der Oberflächenschicht 12 aus, die unterhalb der Isolierschicht 8 vorgesehen und beispielsweise durch Diffusion in die Halbleiterschicht 2 eingebracht ist. Durch dieses doppelseitige Ausräumen an Ladungsträgern ist es möglich, bei gleicher Spannungsfestigkeit die Dotierungsdosis der Halbleiterschicht 2 von etwa 1 x 1012 Ladungsträger cm"2 (Beispiel von Fig. 8) auf den doppelten Wert, also 2 x 1012 Ladungsträger cm"2, zu erhöhen, was die erwähnte Reduzierung des ..Einschaltwiderstandes Ron mit sich bringt.Reduce factor 2 if, as shown in FIG. 9, a p-conducting surface layer 12 is additionally provided in the epitaxial layer 2 in the region between the source zone 4 and the drain zone 3. The epitaxial layer 2 is thus not only cleared of charge carriers from the side of the silicon substrate 1. Rather, such a removal of charge carriers also takes place from the surface layer 12, which is provided below the insulating layer 8 and is introduced into the semiconductor layer 2, for example by diffusion. This double-sided removal of charge carriers makes it possible, with the same dielectric strength, to increase the doping dose of the semiconductor layer 2 from approximately 1 x 10 12 charge carriers cm "2 (example from FIG. 8) to twice the value, ie 2 x 10 12 charge carriers cm " 2 , to increase what the mentioned reduction in the ON resistance Ron entails.
Die Oberflächenschicht 12 kann floaten, also potentialfrei sein. Es ist aber auch möglich, diese Oberflächenschicht 12 (in Fig. 9 nicht dargestellt) an die Bodyzone 5 anzuschlie- ßen. Laterale Hochvolt-MOS-Transistoren, wie diese in den Fig. 8 und 9 gezeigt sind, können in Bipolar-Technologie oder in MOS-Technologie integriert werden (vgl. hierzu auch US 5 432 370) .The surface layer 12 can float, that is to say be floating. However, it is also possible to connect this surface layer 12 (not shown in FIG. 9) to the body zone 5. Lateral high-voltage MOS transistors, as shown in FIGS. 8 and 9, can be integrated in bipolar technology or in MOS technology (cf. also US Pat. No. 5,432,370).
Es ist Aufgabe der vorliegenden Erfindung, ein laterales Hochvolt-Halbleiterbauelement anzugeben, das sich bei großer Spannungsfestigkeit durch einen niedrigen Einschaltwiderstand auszeichnet.It is an object of the present invention to provide a lateral high-voltage semiconductor component which is distinguished by a low on-resistance with a high dielectric strength.
Diese Aufgabe wird bei einem lateralen Hochvolt-Halbleiterbauelement der eingangs genannten Art erfindungsgemäß dadurch gelöst, daß in der Halbleiterschicht zwischen deren Oberflä- ehe und dem Halbleitersubstrat abwechselnd Halbleitergebiete des zweiten Leitungstyps und des ersten Leitungstyps vorgesehen sind, die Halbleitergebiete mit Ausnahme des an das Halbleitersubstrat angrenzenden Halbleitergebiets des zweiten Leitungstyps mit einer Dosis von etwa 2a x 1012 Ladungsträ- gern cm-2 dotiert sind mit a = 0,5 ... 50, das an das Halbleitersubstrat angrenzende Halbleitergebiet des zweiten Leitungstyps mit einer Dosis von (a bis 2a) x 1012 Ladungsträgern cm-2 dotiert ist, und eine Oberflächenzone des ersten oder zweiten Leitungstyps in der Halbleiterschicht mit einer Dosis von etwa a x 1012 Ladungsträgern cm"2 dotiert ist.This object is achieved according to the invention in a lateral high-voltage semiconductor component of the type mentioned at the outset in that semiconductor regions of the second conductivity type and of the first conductivity type are alternately provided in the semiconductor layer between the surface thereof and the semiconductor substrate, the semiconductor regions with the exception of those adjacent to the semiconductor substrate Semiconductor regions of the second conductivity type with a dose of about 2a x 10 12 charge carriers cm -2 are doped with a = 0.5 ... 50, the semiconductor region of the second conductivity type adjacent to the semiconductor substrate with a dose of (a to 2a) x 10 12 charge carriers cm -2 , and a surface zone of the first or second conductivity type in the semiconductor layer is doped with a dose of about ax 10 12 charge carriers cm "2 .
Bei dem erfindungsgemäßen lateralen Hochvolt-Halbleiterbauelement wird also in der beispielsweise durch eine Epitaxieschicht oder eine Wanne gebildeten Halbleiterschicht nicht nur, wie beim Stand der Technik, eine zusätzliche Zone in der Gestalt einer Oberflächenzone vorgesehen; vielmehr werden erfindungsgemäß mehrere Halbleitergebiete aus Folgen von n- und p-leitenden Schichten mit Dosen von beispielsweise 2 x 1012 oder auch 4 x 1012 Ladungsträgern cm"2 in die Halbleiter- schicht eingebaut. Diese Halbleitergebiete räumen sich bei beispielsweise einem MOS-Transistor bei einer hohen anliegenden Source-Drain-Sperrspannung hinsichtlich ihrer Ladungsträger gegenseitig aus.In the case of the lateral high-voltage semiconductor component according to the invention, an additional zone in the form of a surface zone is therefore not only provided in the semiconductor layer formed, for example, by an epitaxial layer or a tub, as in the prior art; Rather, according to the invention, several semiconductor regions consisting of sequences of n- and p-conducting layers with doses of, for example, 2 × 10 12 or also 4 × 10 12 charge carriers cm "2 are installed in the semiconductor layer. These semiconductor regions are cleared up for example, a MOS transistor with a high applied source-drain reverse voltage with respect to their charge carriers.
In bevorzugter Weise werden die Halbleitergebiete durch Hoch- volt-Ioneni plantationen von beispielsweise Bor und Phosphor bei unterschiedlicher Beschleunigungsspannung realisiert. Durch solche Hochvolt-Ionenimplantationen lassen sich Eindringtiefen der Halbleitergebiete von etwa 1 - 20 μm, vor- zugsweise 2 - 5 μm bei relativ hohen Dotierungsdosen erzielen. Innerhalb dieser Eindringtiefen sind dabei die Halbleitergebiete als dünne n- und p-leitende Schichten mit jeweils einer Dosis von etwa 2a x 1012 Ladungsträger cm"2 erzeugt, wobei das oberste Halbleitergebiet direkt unterhalb einer Iso- lierschicht eine Dosis von etwa a x 1012 Ladungsträger cm-2 hat (0,5 < a < 50) . Die oberste Schicht kann sowohl n- als auch p-dotiert sein. Bei Implantation von Bor ist beispielsweise ohne weiteres die Bildung von drei p-leitenden Gebieten möglich.The semiconductor regions are preferably implemented by high-voltage ion implantations of, for example, boron and phosphorus at different acceleration voltages. Such high-voltage ion implantations allow penetration depths of the semiconductor regions of approximately 1 to 20 μm, preferably 2 to 5 μm, with relatively high doping doses. Within these penetration depths, the semiconductor regions are produced as thin n- and p-conducting layers, each with a dose of approximately 2a x 10 12 charge carriers cm "2 , the uppermost semiconductor region directly below an insulating layer having a dose of approximately ax 10 12 charge carriers cm -2 has (0.5 <a <50). The top layer can be either n- or p-doped. With boron implantation, for example, the formation of three p-conductive regions is readily possible.
Bei der so entstehenden Schichtenfolge hat die unterste, n- leitende Schicht aus dem Halbleitersubstrat eine Dotierungskonzentration, die so niedrig ist, daß die maximale Drainspannung aufgenommen werden kann. Für die Halbleiterschicht aus der Epitaxieschicht oder der Wanne beträgt diese Dosis weniger als (a bis 2a) x 1012 und beispielsweise 1 x 1012 Ladungsträger cm-2.In the case of the layer sequence thus created, the lowermost, n-conducting layer made of the semiconductor substrate has a doping concentration which is so low that the maximum drain voltage can be absorbed. For the semiconductor layer from the epitaxial layer or the tub, this dose is less than (a to 2a) x 10 12 and, for example, 1 x 10 12 charge carriers cm -2 .
Die genauen Werte der jeweiligen Dotierungsdosen können bei- spielsweise durch Simulation ermittelt werden.The exact values of the respective doping doses can be determined, for example, by simulation.
Werden nur wenige Halbleitergebiete als Schichten unterschiedlich abwechselnden Leitungstyps vorgesehen, so kann deren elektrische Aktivierung mittels üblicher Ofenprozesse er- reicht werden. Ist die Anzahl der Halbleitergebiete jedoch größer, liegen also beispielsweise 4 oder 5 Halbleitergebiete vor, so muß ein "Ineinanderlaufen" der jeweiligen Dotierungen verhindert werden, was dadurch geschehen kann, daß die elektrische Aktivierung durch schnelles thermisches Glühen ("Rapid-Thermal-Annealing" bzw. RTA) erfolgt.If only a few semiconductor regions are provided as layers of differently alternating conduction types, their electrical activation can be achieved by means of conventional furnace processes. However, the number of semiconductor areas Larger, for example if there are 4 or 5 semiconductor regions, the respective dopings must be prevented from "running into one another", which can be done by the electrical activation being carried out by rapid thermal annealing ("rapid thermal annealing" or RTA).
Die Halbleitergebiete können selbstverständlich laterale npn- und pnp-Strukturen bilden.The semiconductor regions can of course form lateral npn and pnp structures.
In bevorzugter Weise sind die Halbleitergebiete des ersten Leitungstyps, im vorliegenden Fall des p-Leitungstyps, über die Bodyzone an den Source-Body-Bereich angeschlossen, um so ein schnelles Umschalten von einem sperrenden Zustand, bei dem die Raumladungszone in den Halbleitergebieten abwechselnd unterschiedlichen Leitungstyps liegt, auf einen stromführenden Zustand zu ermöglichen. Durch diese Verbindung zwischen den p-leitenden Gebieten und der Bodyzone wird nämlich die ursprüngliche Löcherkonzentration und damit Ladungsneutralität der p-leitenden Gebiete nicht über thermische Generation, sondern schnell durch Löcherleitung aus dem Source-Body-Bereich wiederhergestellt.The semiconductor regions of the first conduction type, in the present case of the p-conduction type, are preferably connected via the body zone to the source body region, in order in this way to rapidly switch from a blocking state in which the space charge zone in the semiconductor regions alternately has different conduction types is to enable a live state. Because of this connection between the p-type regions and the body zone, the original hole concentration and thus charge neutrality of the p-type regions is not restored via thermal generation, but rather quickly through hole conduction from the source body region.
Die Layouts des erfindungsgemäßen lateralen Hochvolt-Halbleiterbauelements können in den verschiedensten Formen vorge- nommen werden. Beispielsweise ist bei einem MOS-Transistor als Halbleiterbauelement ein Einzeltransistor möglich, bei dem Drains in länglicher Gestalt oval von den Halbleitergebieten und Source umgeben ist. Ebenso sind auch Mäander- oder Kammstrukturen für Drain bzw. Source möglich. Andere denkbare Strukturen bestehen in sechseckförmigen Waben, in deren Mittelpunkt jeweils Drain liegt, während Source sternförmig zwischen jeweils drei aneinandergrenzenden "Waben" vorgesehen ist. Wenn die Halbleitergebiete abwechselnd unterschiedlichen Leitungstyps frei floatend sind, kann in vorteilhafter Weise eine die Ladungsträger-Lebensdauer reduzierende Dotierung/oder Damage-Implantation, beispielsweise mit Platin oder Gold oder Molybdän oder eine Damage-Implantation mittels Helium oder Elektronen oder Protronen, im Bereich dieser Halbleitergebiete vorgenommen werden. Durch diese die Ladungsträger-Lebensdauer reduzierende Dotierung/Da age wird nicht nur die Rekombination der Ladungsträger, sondern auch die Ladungsträgerge- neration in den Halbleitergebieten gefördert, was zu einer Beschleunigung der Schaltzeiten des lateralen Hochvolt-MOS- Transistors führt.The layouts of the lateral high-voltage semiconductor component according to the invention can be carried out in a wide variety of forms. For example, in the case of a MOS transistor as a semiconductor component, a single transistor is possible in which drains are oval in an elongated shape and are surrounded by the semiconductor regions and source. Meandering or comb structures for drain or source are also possible. Other conceivable structures consist of hexagonal honeycombs, in the center of which there is a drain, while source is provided in a star shape between three adjacent "honeycombs". If the semiconductor regions are alternately of different conductivity types floating freely, doping / or damage implantation which reduces the charge carrier life, for example with platinum or gold or molybdenum or damage implantation by means of helium or electrons or protons, can advantageously be carried out in the region of these semiconductor regions be made. This doping / age, which reduces the charge carrier life, not only promotes the recombination of the charge carriers, but also the charge carrier generation in the semiconductor regions, which leads to an acceleration of the switching times of the lateral high-voltage MOS transistor.
Bei dem erfindungsgemäßen lateralen Hochvolt-Halbleiterbau- element ist allgemein der spezifische Einschaltwiderstand Ron umgekehrt proportional zu der Anzahl der übereinanderliegen- den Halbleitergebiete abwechselnd unterschiedlichen Leitungstyps. Ein Ron-Gewinn von beispielsweise einem Faktor 3 bis 5 läßt sich ohne weiteres erzielen.In the case of the lateral high-voltage semiconductor component according to the invention, the specific on-resistance Ron is generally inversely proportional to the number of semiconductor regions lying on top of one another and alternately of different conductivity types. A Ron win of, for example, a factor of 3 to 5 can easily be achieved.
Der Bereich dieser Gebiete abwechselnd unterschiedlichen Leitungstyps läßt sich über die bereits oben angegebenen 1 bis 20 um hinaus noch erweitern:The range of these areas of alternately different line types can be expanded beyond the 1 to 20 already specified above:
Werden bei einem MOS-Transistor als Halbleiterbauelement Sourcezone, Drainzone, gegebenenfalls Isolierzonen und die Halbleitergebiete abwechselnd unterschiedlichen Leitungstyps allein durch maskierte Hochvolt-Ionenimplantationen und anschließendes RTA hergestellt, so können ohne weiteres zusätz- liehe Epitaxieschichten, beispielsweise durch Niedertemperatur-Epitaxie, mit Schichtdicken von etwa 4 μm und darüber abgeschieden werden, worauf sich wiederum die Erzeugung der Gebiete abwechselnd unterschiedlichen Leitungstyps durch Hoch- volt-Ionenimplantation und RTA anschließt. Auf diese Weise ist es möglich, die Schichtdicke der Halbleitergebiete ab- wechselnd unterschiedlichen Leitungstyps über die angegebenen etwa 6 μm hinaus erheblich zu steigern und wesentlich größere Schichtdicken zu realisieren, die den Einschaltwiderstand Ron noch um ein Mehrfaches reduzieren.If the source zone, drain zone, optionally isolation zones and the semiconductor regions of a MOS transistor as a semiconductor component are alternately produced using alternately different types of conduction solely by masked high-voltage ion implantations and subsequent RTA, then additional epitaxial layers, for example by low-temperature epitaxy, with layer thicknesses of approximately 4 μm and above are deposited, which in turn is followed by the generation of the regions of alternately different conduction types by high-voltage ion implantation and RTA. In this way it is possible to reduce the layer thickness of the semiconductor regions. alternately different types of cables to increase significantly beyond the specified about 6 microns and to realize much greater layer thicknesses that reduce the on-resistance Ron by a multiple.
Ein derartiges Vorgehen ist allerdings mit dem Wegfall herkömmlicher Hochtemperatur-Ofenprozesse für Diffusionen und für das Aufwachsen von Siliziumoxidschichten als Isolierschichten erkauft. Die Isolierschichten müßten hier aus einem dünnen Niedertemperaturofenoxid und abgeschiedenen Siliziumdioxid- oder sonstigen dielektrischen Schichten hoher Qualität zusammengesetzt werden.Such a procedure is, however, paid for with the elimination of conventional high-temperature furnace processes for diffusions and for the growth of silicon oxide layers as insulating layers. The insulating layers would have to be composed of a thin, low-temperature furnace oxide and deposited silicon dioxide or other dielectric layers of high quality.
Eine besonders vorteilhafte Weiterbildung des erfindungsgemä- ßen lateralen Hochvolt-Halbleiterbauelements besteht darin, daß die Dosis in den Halbleitergebieten abwechselnd unterschiedlichen Leitungstyps lateral gestaffelt ist, was einen stabilisierenden Einfluß auf die Durchbruchsfestigkeit des Bauelements hat. Diese laterale Dosis-Staffelung läßt sich durch Verwendung verschiedener Implantationsmasken und unterschiedliche Implantationsenergien erreichen.A particularly advantageous development of the lateral high-voltage semiconductor component according to the invention consists in that the dose in the semiconductor regions is alternately staggered laterally, which has a stabilizing influence on the breakdown strength of the component. This lateral dose graduation can be achieved by using different implantation masks and different implantation energies.
Vorteilhaft ist die Verwendung einer lateralen Dosis-Staffelung auch bei V-MOS-Strukturen (vgl. hierzu US 4 754 310 und US 5 216 275) .The use of a lateral dose graduation is also advantageous with V-MOS structures (cf. US Pat. No. 4,754,310 and US Pat. No. 5,216,275).
Werden nur wenige Halbleitergebiete abwechselnd unterschiedlichen Leitungstyps vorgesehen, so braucht das RTA nicht angewandt zu werden. Vielmehr ist es möglich, herkömmliche Hochtemperatur-Ofenprozesse einzusetzen und dann nur eine Implantationsmaske vorzusehen. Die gewünschte Lästigkeit der einzelnen Gebiete nach n bzw. p kann dann mittels lateraler Diffusion über verschiedene Aussparungen erreicht werden. Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:If only a few semiconductor regions are alternately provided with different conduction types, the RTA need not be applied. Rather, it is possible to use conventional high-temperature furnace processes and then only to provide one implantation mask. The desired annoyance of the individual areas according to n or p can then be achieved by means of lateral diffusion through various cutouts. The invention is explained in more detail below with reference to the drawings. Show it:
Figur 1 einen Schnitt durch ein erstes Ausführungsbeispiel eines erfindungsgemäßen lateralen Hochvolt-MOS-FIG. 1 shows a section through a first exemplary embodiment of a lateral high-voltage MOS
Transistors,Transistor,
Figur 2 einen Schnitt durch ein zweites Ausführungsbeispiel eines erfindungsgemäßen lateralen Hochvolt-MOS- Transistors mit einem Body-Anschluß,FIG. 2 shows a section through a second exemplary embodiment of a lateral high-voltage MOS transistor with a body connection,
Figuren 3a bis 3c verschiedene Layouts für einen erfindungsgemäßen lateralen Hochvolt-MOS-Transistor,FIGS. 3a to 3c different layouts for a lateral high-voltage MOS transistor according to the invention,
Figur 4 ein Schnittbild zur Erläuterung einer Ionenimplantation mit verschiedenen Implantationsmasken,FIG. 4 shows a sectional view to explain an ion implantation with different implantation masks,
Figur 5a und 5b Darstellungen zur Erläuterung einer lateralen Ausdiffusion nach einer Hochvolt-Ionenimplantation,5a and 5b representations to explain a lateral out-diffusion after a high-voltage ion implantation,
Figur 6 einen Schnitt durch einen V-MOS-Transistor mit lateral variierenden Dotierungen,FIG. 6 shows a section through a V-MOS transistor with laterally varying dopings,
Figur 7 Implantationsprofile von Bor und Phosphor in Silizium mit unterschiedlichen Implantationsenergien,FIG. 7 implantation profiles of boron and phosphorus in silicon with different implantation energies,
Figur 8 einen Schnitt durch einen ersten bestehenden lateralen Hochvolt-MOS-Transistor und8 shows a section through a first existing lateral high-voltage MOS transistor and
Figur 9 einen Schnitt durch einen weiteren bestehenden lateralen Hochvolt-MOS-Transistor.Figure 9 shows a section through another existing lateral high-voltage MOS transistor.
Die Fig. 8 und 9 sind bereits eingangs erläutert worden. In den Fig. 1 bis 7 werden für einander entsprechende Bauteile die gleichen Bezugszeichen wie in den Fig. 8 und 9 verwendet und nicht nochmals näher beschrieben.8 and 9 have already been explained at the beginning. 1 to 7 are corresponding components for each other the same reference numerals as in Figs. 8 and 9 are used and not described again.
Es sei lediglich erneut betont, daß die angegebenen Leitungs- typen jeweils auch umgekehrt sein können.It should only be emphasized again that the specified line types can also be reversed.
Fig. 1 zeigt ein Schnittbild durch einen lateralen Hochvolt- MOS-Transistor gemäß einem ersten Ausführungsbeispiel der Erfindung. Zur Verdeutlichung der Darstellung sind hier wie in folgenden Schnittbildern nicht alle geschnittenen Teile schraffiert dargestellt.1 shows a sectional view through a lateral high-voltage MOS transistor according to a first exemplary embodiment of the invention. To clarify the illustration, not all cut parts are shown hatched, as in the following sectional views.
Der erfindungsgemäße laterale Hochvolt-MOS-Transistor unterscheidet sich von dem bestehenden lateralen Hochvolt-MOS- Transistor im wesentlichen dadurch, daß zusätzliche p-lei- tende Halbleitergebiete 14, die sich mit n-leitenden Halbleitergebieten 13 abwechseln, im Bereich zwischen Drain 3 und Source 4 vorgesehen sind. Diese Halbleitergebiete 13, 14, die zusammen mit der Oberflächenzone 12 eine p-n-Schichtenfolge bilden, haben eine Dosis von etwa beispielsweise 2a x 1012 The lateral high-voltage MOS transistor differs from the existing lateral high-voltage MOS transistor essentially in that additional p-conducting semiconductor regions 14, which alternate with n-conducting semiconductor regions 13, in the region between drain 3 and source 4 are provided. These semiconductor regions 13, 14, which together with the surface zone 12 form a pn layer sequence, have a dose of approximately 2a × 10 12, for example
Ladungsträgern cm"2 (a = 0,5 ... 50, vorzugsweise a = 1) und räumen sich bei hoher anliegender Source-Drain-Sperrspannung zwischen Sourceelektrode 7 und Drainelektrode 6 bezüglich ihrer Ladungsträger gegenseitig aus. Die oberste Schicht, nä - lieh die Oberflächenzone 12 hat eine Dosis von etwa a xCharge carriers cm "2 (a = 0.5 ... 50, preferably a = 1) and, when the source-drain reverse voltage is high, clear each other with respect to their charge carriers between source electrode 7 and drain electrode 6. The top layer, borrowed the surface zone 12 has a dose of approximately ax
1012 Ladungsträgern cm"2, während in der untersten Schicht, also in dem Halbleitergebiet unmittelbar angrenzend an das Halbleitersubstrat 1 eine Dosis von (a bis 2a) x 1012 Ladungsträgern cm"2 vorliegt. Diese niedrige Dotierung wird ge- wählt, da dieses Halbleitergebiet 13 die maximale Drainspannung aufnehmen muß .10 12 charge carriers cm "2 , while in the lowest layer, that is to say in the semiconductor region immediately adjacent to the semiconductor substrate 1, there is a dose of (a to 2a) x 10 12 charge carriers cm " 2 . This low doping is chosen because this semiconductor region 13 has to absorb the maximum drain voltage.
Die technische Realisierung der Schichtfolgen aus den Halbleitergebieten 13, 14 und der Oberflächenzone 12 wird in be- vorzugter Weise durch Hochvolt-Ionenimplantation von bei- spielsweise Bor und Phosphor mit unterschiedlichen Beschleunigungsspannungen vorgenommen. Hierzu wird auf die Fig. 7 verwiesen, in der auf der Abszisse die Eindringtiefe x in μm der einzelnen Ionenimplantationen und auf der Ordinate die Dotierungskonzentration in Ladungsträger cm"3 für verschiedene Beschleunigungsspannungen zwischen 300 keV und 2000 keV für Bor (B) und Phosphor (P) angegeben sind. Durch solche Hochvolt-Ionenimplantationen lassen sich über einer Eindringtiefe von 2 bis 6 μm (oder darüber) dünne n- und p-leitende Schichten als die Halbleitergebiete 13, 14 mit jeweils einer Dosis von etwa 2a x 1012 Ladungsträger cm"2 erzeugen (a = 0,5 ... 50) . Für die oberste Schicht, also die Oberflächenzone 12 wird eine Dosis von a x 1012 cm"2 bevorzugt, während die unterste Schicht, also das dem Siliziumsubstrat 1 benachbarte Halbleitergebiet 13 so niedrig dotiert ist, daß die maximale Drainspannung aufgenommen werden kann. Eine hierfür geeignete Dosis ist (a bis 2a) x 1012 cm'2.The technical implementation of the layer sequences from the semiconductor regions 13, 14 and the surface zone 12 is preferably carried out by high-voltage ion implantation of for example, boron and phosphor made with different acceleration voltages. For this purpose, reference is made to FIG. 7, in which on the abscissa the penetration depth x in μm of the individual ion implantations and on the ordinate the doping concentration in charge carriers cm "3 for different acceleration voltages between 300 keV and 2000 keV for boron (B) and phosphorus ( P) Such high-voltage ion implantations allow thin n- and p-type layers over a penetration depth of 2 to 6 μm (or more) than the semiconductor regions 13, 14, each with a dose of about 2a × 10 12 charge carriers cm "Generate 2 (a = 0.5 ... 50). For the top layer, ie the surface zone 12, a dose of ax 10 12 cm "2 is preferred, while the bottom layer, that is to say the semiconductor region 13 adjacent to the silicon substrate 1, is doped so low that the maximum drain voltage can be absorbed. A suitable one for this Dose is (a to 2a) x 10 12 cm '2 .
Die Halbleiterschicht 2 kann eine Dotierung von weniger als 1 xx 11001122 LLaadduunnggssttrrääggeerrnn ccmm--22 aauuffwweeiisen. Es sind aber auch deut- lieh höhere Dotierungen möglich,The semiconductor layer 2 can have a doping of less than 1 xx 1100 1122 LLaadduunnggsstträäggeerrnn ccmm --22. However, significantly higher dopings are also possible,
Sind nur wenige Halbleitergebiete 13, 14 vorhanden, so können für deren elektrische Aktivierung übliche Ofenprozesse ver- wendet werden. Ist die Anzahl der Halbleitergebiete 13, 14 dagegen höher, so sollte die elektrische Aktivierung durch RTA erfolgen, damit ein Verschmieren bzw. Ineinanderlaufen der Dotierungen verhindert wird.If only a few semiconductor regions 13, 14 are present, conventional furnace processes can be used for their electrical activation. If, on the other hand, the number of semiconductor regions 13, 14 is higher, the electrical activation should take place by RTA, so that smearing or running into one another of the dopings is prevented.
Während Fig. 1. ein Ausführungsbeispiel eines erfindungsgemäßen lateralen Hochvolt-MOS-Transistors zeigt, bei dem die p- leitenden Halbleitergebiete 14 sowie die Oberflächenzone 12 floaten, können diese Halbleiterbereiche auch an den Source- Body-Bereich angeschlossen sein, wie dies durch einen p-lei- tenden Halbleiterbereich 15 im Ausführungsbeispiel von Fig. 2 gezeigt ist.During Fig. 1 . shows an embodiment of a lateral high-voltage MOS transistor according to the invention, in which the p-type semiconductor regions 14 and the surface zone 12 float, these semiconductor regions can also be connected to the source body region, as is done by a p-type tendency semiconductor region 15 in the embodiment of FIG. 2 is shown.
Durch diesen Halbleiterbereich 15, der zwischen den p-lei- tenden Halbleitergebieten 14 bzw. der Oberflächenzone 12 und der Bodyzone 5 liegt, wird die ursprüngliche Löcherkonzentration für Ladungsneutralität in den Halbleitergebieten 14 bzw. der Oberflächenzone 12 nicht über thermische Erzeugung von Ladungsträgern, sondern durch Löcherleitung von der Source- seite her wiederhergestellt, was ein schnelles Umschalten von einem sperrenden Zustand in einen stromführenden Zustand ermöglicht .By means of this semiconductor region 15, which lies between the p-conducting semiconductor regions 14 or the surface zone 12 and the body zone 5, the original hole concentration for charge neutrality in the semiconductor regions 14 or the surface zone 12 is not through thermal generation of charge carriers, but through Hole line restored from the source side, which enables a quick switch from a blocking state to a current-carrying state.
Wenn die Halbleitergebiete 13, 14 und die Oberflächenzone 12 frei floatend sind, wie dies beim Ausführungsbeispiel von Fig. 1 vorgesehen ist, so ist es vorteilhaft, in diesen Gebieten bzw. dieser Zone eine die Ladungsträger-Lebensdauer reduzierende Dotierung aus beispielsweise Platin, Gold oder Molybdän oder eine Damage-Implantation mittels Helium, Elek- tronen oder Protronen im Bereich der n-p-Schichtfolge vorzusehen, wodurch nicht nur die Rekombination der Ladungsträger, sondern auch die Erzeugung der Ladungsträger und damit die Schaltzeiten des Transistors beschleunigt werden.If the semiconductor regions 13, 14 and the surface zone 12 are floating freely, as is provided in the exemplary embodiment of FIG. 1, it is advantageous in these regions or this zone to have a doping of platinum, gold or, for example, reducing the charge carrier life Molybdenum or a damage implantation by means of helium, electrons or protrons in the area of the np layer sequence, which not only accelerates the recombination of the charge carriers, but also the generation of the charge carriers and thus the switching times of the transistor.
Insgesamt kann festgestellt werden, daß der spezifische Einschaltwiderstand Ron des erfindungsgemäßen lateralen Hochvolt-Halbleiterbauelements proportional zu der Anzahl der verwendeten n- bzw. p-leitenden Halbleitergebiete 13 bzw. 14 reduziert wird. Das heißt, je mehr solche Halbleitergebiete 13, 14 abwechselnd unterschiedlichen Leitungstyps vorgesehen werden, desto geringer wird der spezifische Einschaltwiderstand des lateralen Hochvolt-Halbleiterbauelements.Overall, it can be determined that the specific switch-on resistance Ron of the lateral high-voltage semiconductor component according to the invention is reduced in proportion to the number of n- and p-type semiconductor regions 13 and 14 used. That is, the more such semiconductor regions 13, 14 are provided with alternately different conductivity types, the lower the specific on-resistance of the lateral high-voltage semiconductor component.
Die Fig. 3a bis 3c zeigen verschiedene Layouts für einen er- findungsgemäßen lateralen Hochvolt-MOS-Transistor. Diese kön- nen eine längliche Drainstruktur 3, 6 vorsehen, die von den3a to 3c show different layouts for a lateral high-voltage MOS transistor according to the invention. These can NEN provide an elongated drain structure 3, 6, which of the
Halbleitergebieten 12, 13, 14 und einer Sourcestruktur 4, 7 umgeben sind, wobei ein Source- bzw. Bodyanschluß 15 dieSemiconductor regions 12, 13, 14 and a source structure 4, 7 are surrounded, with a source or body connection 15
Halbleitergebiete mit Source verbindet (vgl. Fig. 3a).Connects semiconductor regions with source (cf. FIG. 3a).
Andere mögliche Strukturen bestehen in mäander- oder kammför- migen Strukturen, wie dies in Fig. 3b gezeigt ist, oder in wabenartigen Strukturen entsprechend dem Beispiel von Fig. 3c.Other possible structures consist of meandering or comb-shaped structures, as shown in FIG. 3b, or honeycomb-like structures corresponding to the example of FIG. 3c.
Lateral steigende und fallende Dotierungen in den Halbleitergebieten 13, 14 und der Oberflächenzone 12, wodurch eine stabilisierende Wirkung auf die Durchbruchsfestigkeit von DMOS- Transistoren ausgeübt werden kann, lassen sich ohne weiteres durch eine laterale Dosis-Staffelung bei der Ionenimplantation erzielen, wie dies schematisch in Fig. 4 veranschaulicht ist.Lateral rising and falling doping in the semiconductor regions 13, 14 and the surface zone 12, which can have a stabilizing effect on the breakdown strength of DMOS transistors, can be easily achieved by lateral dose grading in the ion implantation, as schematically shown in Fig. 4 is illustrated.
Es werden hier verschiedene Implantationsmasken 16, 17, 18 verwendet, so daß beispielsweise vier Hochvolt-Ionenimplan- tationen mit Implantationsenergien von beispielsweise 0,1 bzw. 0,3 bzw. 1 bzw. 2 MeV zu vier Halbleiterbereichen aus den drei Halbleitergebieten 14 und der Oberflächenzone 12 führen, die in lateraler Richtung - entsprechend den schema- tisch veranschaulichten Implantationsmasken 16 bis 18, eine von links nach rechts fallende Dotierung haben. In Bereichen 19 liegt eine Dosis der Ionenimplantation ohne Maske vor, während in Bereichen 20 diese Dosis durch die Abschirmwirkung der Maske 18 vermindert ist und in Bereichen 21 eine weitere Reduzierung der Dosis entsprechend der Abschirmwirkung der Masken 17 und 18 eintritt.Different implantation masks 16, 17, 18 are used here, so that, for example, four high-voltage ion implants with implantation energies of, for example, 0.1 or 0.3 or 1 or 2 MeV for four semiconductor regions from the three semiconductor regions 14 and 14 Guide surface zone 12 which have a doping falling from left to right in the lateral direction - corresponding to the schematically illustrated implantation masks 16 to 18. In areas 19 there is a dose of the ion implantation without a mask, while in areas 20 this dose is reduced by the shielding effect of the mask 18 and in areas 21 there is a further reduction in the dose corresponding to the shielding effect of the masks 17 and 18.
Werden nur wenige Halbleitergebiete 13, 14 vorgesehen, so kann anstelle des RTA ein üblicher Ofenprozeß eingesetzt wer- den. In diesem Fall ist eine einzige Implantationsmaske 22 ausreichend, die für etwa 1 μm breite Aussparungen 23 in einem streifenförmigen implantierten Halbleitergebiet 13 sorgt. Die angestrebte n- bzw. p-Lastigkeit kann hier mittels lateraler Diffusion in die Aussparungen 23 erzielt werden, wie dies in Fig. 5b veranschaulicht ist.If only a few semiconductor regions 13, 14 are provided, a conventional furnace process can be used instead of the RTA. In this case there is a single implantation mask 22 sufficient that provides for about 1 micron wide recesses 23 in a strip-shaped implanted semiconductor region 13. The desired n or p load can be achieved here by means of lateral diffusion into the recesses 23, as is illustrated in FIG. 5b.
Das oben erläuterte Prinzip steigender und fallender Dotierungen in den Halbleitergebieten 13, 14 kann ohne weiteres auch bei einem VMOS-Transistor eingesetzt werden, wie dieser schematisch in Fig. 6 veranschaulicht ist. Der Elektronenfluß wird hier durch Pfeile 24 angedeutet.The above-explained principle of increasing and decreasing doping in the semiconductor regions 13, 14 can also be used with a VMOS transistor, as is illustrated schematically in FIG. 6. The electron flow is indicated here by arrows 24.
Bei der vorliegenden Erfindung wird also nicht nur ein zusätzliches Halbleitergebiet, wie nach dem herkömmlichen Ein- fach-Resurf-Prinzip, ausgeräumt, sondern es werden vielmehr Schichtenfolgen aus n- und p-leitenden Halbleitergebieten vorgesehen, die Dosen haben, welche eine gegenseitige Ausräumung der Halbleitergebiete bezüglich ihrer Ladungsträger bei anliegender hoher Sperrspannung erlauben. Entscheidendes Kri- terium für die Dotierungsdosis ist, daß die kritische Feldstärke an den Grenzflächen zwischen n- und p-leitenden Halbleitergebieten nicht überschritten wird, d.h., daß das Ionisationsintegral kleiner als 1 bleibt.In the present invention, therefore, not only is an additional semiconductor region cleared out, as is the case with the conventional simple resurf principle, but rather layer sequences of n- and p-type semiconductor regions are provided which have cans which mutually clear out the Allow semiconductor regions with regard to their charge carriers when a high reverse voltage is present. The decisive criterion for the doping dose is that the critical field strength at the interfaces between n- and p-conducting semiconductor regions is not exceeded, i.e. that the ionization integral remains less than 1.
Die technische Realisierung solcher Halbleitergebiete wird durch Hochvolt-Ionenimplantation von beispielsweise Bor und Phosphor mit unterschiedlicher Beschleunigungsspannung ausgeführt. Dadurch lassen sich über eine Tiefe von etwa 3 bis 4 μm mehrere, beispielsweise 4 oder mehr, dünne n- und p- leitende schichtförmige Halbleitergebiete mit jeweils einer Dosis unterhalb des genannten kritischen Wertes erzeugen. Das oberste n- bzw. p-leitende Halbleitergebiet enthält, da es nur von einer Seite von Ladungsträgern ausgeräumt wird, nur die Hälfte der n- bzw. p-Dosis der übrigen, mittleren Halb- leitergebiete, wobei ausdrücklich zu vermerken ist, daß diese Dosis ohne weiteres - wie dies oben ausführlich erläutert wurde, auch größer als 2 x 1012 Ladungsträger cm"2 sein kann.The technical implementation of such semiconductor regions is carried out by high-voltage ion implantation of, for example, boron and phosphorus with different acceleration voltages. As a result, several, for example 4 or more, thin n- and p-type layered semiconductor regions can be produced over a depth of about 3 to 4 μm, each with a dose below the critical value mentioned. The uppermost n- or p-type semiconductor region contains only half of the n- or p-dose of the remaining, middle semiconductor regions, since it is only cleared from one side of charge carriers, it being expressly noted that these Dose without further ado - as explained in detail above, can also be larger than 2 x 10 12 charge carriers cm "2 .
Das unterste Halbleitergebiet, das an das Halbleitersubstrat angrenzt, ist so niedrig zu dotieren, daß es die maximale, beispielsweise an Drain liegende Spannung aufnehmen kann.The lowest semiconductor region, which adjoins the semiconductor substrate, is to be doped so low that it can take up the maximum voltage, for example at the drain.
Durch die höhere Dotierungsdosis wird eine Verminderung des Einschaltwiderstandes Ron bei gleichen Sperreigenschaften beispielsweise eines Transistors erreicht, da dieser Einschaltwiderstand proportional zu der höheren Dotierungsdosis sinkt .The higher doping dose results in a reduction in the on-resistance Ron with the same blocking properties, for example of a transistor, since this on-resistance decreases in proportion to the higher doping dose.
Die Halbleiterschicht kann außerhalb der Halbleitergebiete 13, 14 gegebenenfalls eine Dotierungsdosis haben, die deutlich höher als 2 x 1012 Ladungsträger cm"2 ist und beispielsweise ein 1 x 1013 Ladungsträger cm"2 beträgt. Von Bedeutung ist lediglich, daß die durch Hochenergie-Implantation erzeugten Halbleitergebiete 13, 14 sich in ihrer Ladung gegenseitig kompensieren und die kritische Feldstärke (vgl. oben) nicht überschritten wird. Gegebenenfalls ist es so möglich, beispielsweise lediglich p-leitende Halbleitergebiete zu implantieren und die Dotierungsdosis der n-leitenden Halbleitergebiete durch die Dotierung der Halbleiterschicht 2 festzule- gen.Outside of the semiconductor regions 13, 14, the semiconductor layer can optionally have a doping dose which is significantly higher than 2 x 10 12 charge carriers cm "2 and is, for example, 1 x 10 13 charge carriers cm " 2 . It is only important that the semiconductor regions 13, 14 produced by high-energy implantation mutually compensate each other in their charge and that the critical field strength (cf. above) is not exceeded. If necessary, it is possible, for example, to implant only p-type semiconductor regions and to determine the doping dose of the n-type semiconductor regions by doping the semiconductor layer 2.
Gegebenenfalls ist es aber auch möglich, lediglich das unterste Halbleitergebiet, das an das Halbleitersubstrat 1 angrenzt, auf diese Weise in seiner Dotierung festzulegen und die Dotierungsdosen von allen anderen Halbleitergebieten durch eine Kombination von Hochenergie-Implantation für die n-Dotierung und einen entsprechenden Abstand benachbarter p- leitender Halbleitergebiete festzulegen. Durch ein derartiges Vorgehen ist es möglich, einen tieferenIf necessary, however, it is also possible to determine the doping of only the lowermost semiconductor region, which adjoins the semiconductor substrate 1, and the doping doses of all other semiconductor regions by a combination of high-energy implantation for the n-doping and a corresponding spacing from one another p-type semiconductor regions. By doing so, it is possible to have a deeper one
Schichtaufbau bei zahlreichen Halbleitergebieten und damit einen weiteren Ron-Gewinn zu erreichen, was noch dadurch begünstigt werden kann, daß das Anschlußgebiet 15 höher dotiert wird.Layer structure in numerous semiconductor regions and thus to achieve a further Ron gain, which can be further favored by the fact that the connection region 15 is doped higher.
Die Erfindung ist in vorteilhafter Weise z.B. bei MOS-Transistoren, npn- bzw. pnp-Transistoren, Dioden, J-FET's und IGBT's (Bipolartransistor mit isoliertem Gate) einzusetzen. The invention is advantageously e.g. for MOS transistors, npn or pnp transistors, diodes, J-FETs and IGBTs (bipolar transistor with insulated gate).

Claims

Patentansprüche claims
1. Laterales Hochvolt-Halbleiterbauelement mit reduziertem spezifischem Einschaltwiderstand, mit einem Halbleiter- substrat (1) des ersten Leitungstyps, auf dem eine wenigstens eine aktive Zone aufweisende Halbleiterschicht (2) des zweiten, zum ersten Leitungstyp entgegengesetzten Leitungstyps vorgesehen ist, d a d u r c h g e k e n n z e i c h n e t , daß - in der Halbleiterschicht (2) zwischen deren Oberfläche und dem Halbleitersubstrat (1) abwechselnd Halbleitergebiete (13, 14) des zweiten Leitungstyps und des ersten Leitungstyps vorgesehen sind,1. Lateral high-voltage semiconductor component with reduced specific on-resistance, with a semiconductor substrate (1) of the first conduction type, on which an at least one active zone having semiconductor layer (2) of the second conduction type opposite to the first conduction type is provided, characterized in that - semiconductor regions (13, 14) of the second conductivity type and of the first conductivity type are alternately provided in the semiconductor layer (2) between the surface thereof and the semiconductor substrate (1),
- die Halbleitergebiete (13, 14) mit Ausnahme des an das Halbleitersubstrat (1) angrenzenden Halbleitergebiets (13) des zweiten Leitungstyps mit einer Dosis von etwa 2a x 1012 Ladungsträgern cm"2 dotiert sind, mit a = 0,5 ... 50,- The semiconductor regions (13, 14) with the exception of the semiconductor region (13) of the second conductivity type adjoining the semiconductor substrate (1) are doped with a dose of about 2a x 10 12 charge carriers cm "2 , with a = 0.5 ... 50,
- das an das Halbleitersubstrat (1) angrenzende Halbleitergebiet (13) des zweiten Leitungstyps mit einer Dosis von höchstens (a bis 2a) x 1012 Ladungsträgern cm"2 dotiert ist, und- The semiconductor region (13) of the second conductivity type adjacent to the semiconductor substrate (1) is doped with a dose of at most (a to 2a) x 10 12 charge carriers cm "2 , and
- eine Oberflächenzone (12) des ersten oder zweiten Leitungstyps in der Halbleiterschicht (2) mit einer Dosis von etwa a x 1012 Ladungsträgern cm"2 dotiert ist.- A surface zone (12) of the first or second conductivity type in the semiconductor layer (2) is doped with a dose of approximately ax 10 12 charge carriers cm "2 .
2. Laterales Hochvolt-Halbleiterbauelement nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleitergebiete (13, 14) und die Oberflächenzone (12) durch Hochvolt-Ionenimplantation mit unterschiedlicher Beschleunigungsspannung in die Halbleiterschicht (2) eingebracht sind.2. Lateral high-voltage semiconductor component according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the semiconductor regions (13, 14) and the surface zone (12) by high-voltage ion implantation with different acceleration voltage are introduced into the semiconductor layer (2).
3. Laterales Hochvolt-Halbleiterbauelement nach Anspruch 2, d a d u r c h g e k e n n z e i c h n e t , daß Akzeptoren und Donatoren durch die Hochvolt-Ionenim- plantationen eingebracht sind. 3. Lateral high-voltage semiconductor component according to claim 2, characterized in that acceptors and donors are introduced by the high-voltage ion implantation.
4. Laterales Hochvolt-Halbleiterbauelement nach Anspruch 3, d a d u r c h g e k e n n z e i c h n e t , daß als Akzeptor Bor oder ein vergleichbares dreiwertiges Element und als Donator Phosphor oder ein vergleichbares fünfwertiges Element vorgesehen sind.4. Lateral high-voltage semiconductor component according to claim 3, d a d u r c h g e k e n n z e i c h n e t that boron or a comparable trivalent element and as a donor phosphorus or a comparable pentavalent element are provided.
5. Laterales Hochvolt-Halbleiterbauelement nach einem der Ansprüche 1 bis 4, d a d u r c h g e k e n n z e i c h n e t , daß sich die Halbleitergebiete (13, 14) über eine Tiefe von etwa 1 bis 20 μm, vorzugsweise 2 bis 5 μm, erstrecken.5. Lateral high-voltage semiconductor component according to one of claims 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the semiconductor regions (13, 14) extend over a depth of about 1 to 20 microns, preferably 2 to 5 microns.
6. Laterales Hochvolt-Halbleiterbauelement nach einem der Ansprüche 1 bis 5, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleitergebiete (13, 14) durch rasches thermisches Glühen (RTA) elektrisch aktiviert sind.6. Lateral high-voltage semiconductor component according to one of claims 1 to 5, d a d u r c h g e k e n n z e i c h n e t that the semiconductor regions (13, 14) are electrically activated by rapid thermal annealing (RTA).
7. Laterales Hochvolt-Halbleiterbauelement nach einem der An- sprüche 1 bis 6, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleitergebiete durch maskierte Ionenimplantation mit unterschiedlichen Implantationsenergien eingebracht sind und dadurch eine lateral abfallende Dotierung aufweisen.7. Lateral high-voltage semiconductor component according to one of claims 1 to 6, so that the semiconductor regions are introduced by masked ion implantation with different implantation energies and thus have a laterally decreasing doping.
8. Laterales Hochvolt-Halbleiterbauelement nach einem der Ansprüche 1 bis 6, d a d u r c h g e k e n n z e i c h n e t , daß nur ein Halbleitergebiet des ersten oder zweiten Leitung- styps durch Ionenimplantation durch eine Maske mit anschließender lateraler Diffusion hergestellt ist.8. Lateral high-voltage semiconductor component according to one of claims 1 to 6, so that only one semiconductor region of the first or second conduction type is produced by ion implantation through a mask with subsequent lateral diffusion.
9. Laterales Hochvolt-Halbleiterbauelement nach einem der Ansprüche 1 bis 8, d a d u r c h g e k e n n z e i c h n e t , daß eine die Ladungsträger-Lebensdauer reduzierende Dotierung oder Damage-Implantation in die Halbleitergebiete (13, 14) eingebracht ist.9. Lateral high-voltage semiconductor component according to one of claims 1 to 8, characterized in that a doping or damage implantation which reduces the charge carrier life is introduced into the semiconductor regions (13, 14).
10. Laterales Hochvolt-Halbleiterbauelement nach Anspruch 9, d a d u r c h g e k e n n z e i c h n e t , daß die Dotierung aus Platin oder Gold oder Molybdän bzw. die Damage-Implantation aus Helium oder Elektronen oder Protronen oder einer anderen die Ladungsträger-Lebensdauer reduzieren- den Dotierung besteht.10. Lateral high-voltage semiconductor component according to claim 9, d a d u r c h g e k e n n z e i c h n e t that the doping consists of platinum or gold or molybdenum or the damage implantation of helium or electrons or protons or another doping reducing the charge carrier life.
11. Laterales Hochvolt-Halbleiterbauelement nach einem der Ansprüche 1 bis 10, d a d u r c h g e k e n n z e i c h n e t , daß es ein IGBT, ein J-FET, ein pnp- oder npn-Transistor oder eine Diode ist.11. Lateral high-voltage semiconductor component according to one of claims 1 to 10, d a d u r c h g e k e n n z e i c h n e t that it is an IGBT, a J-FET, a pnp or npn transistor or a diode.
12. Laterales Hochvolt-Halbleiterbauelement nach einem der Ansprüche 1 bis 10, d a d u r c h g e k e n n z e i c h n e t , daß es ein lateraler Hochvolt-MOS-Transistor mit einer Drainzone (3) des zweiten Leitungstyps, einer Sourcezone (4) des zweiten Leitungstyps und einer die Sourcezone (4) umgebenden Bodyzone (5) des ersten Leitungstyps, wobei die Drainzone (3) , die Sourcezone (4) und die Bodyzone (5) in der Halbleiterschicht (2) vorgesehen sind, und mit einer Gateelektrode (10) im Bereich oberhalb der Bodyzone (5), einer Drainelektrode (6) und einer Sourceelektrode (7) ist.12. Lateral high-voltage semiconductor component according to one of claims 1 to 10, characterized in that it is a lateral high-voltage MOS transistor with a drain zone (3) of the second conduction type, a source zone (4) of the second conduction type and one of the source zone (4) surrounding body zone (5) of the first conduction type, the drain zone (3), the source zone (4) and the body zone (5) being provided in the semiconductor layer (2), and with a gate electrode (10) in the region above the body zone (5 ), a drain electrode (6) and a source electrode (7).
13. Lateraler Hochvolt-MOS-Transistor nach Anspruch 12, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleitergebiete (14) des ersten Leitungstyps und/oder die Oberflächenzone (12) an die Bodyzone (5) angeschlossen sind.13. Lateral high-voltage MOS transistor according to claim 12, characterized in that the semiconductor regions (14) of the first conductivity type and / or the surface zone (12) is connected to the body zone (5).
14. Lateraler Hochvolt-MOS-Transistor nach Anspruch 12 oder 13, d a d u r c h g e k e n n z e i c h n e t , daß Drain (3, 6) von den Halbleitergebieten (13, 14) und14. Lateral high-voltage MOS transistor according to claim 12 or 13, d a d u r c h g e k e n n z e i c h n e t that drain (3, 6) from the semiconductor regions (13, 14) and
Source (4, 7) umgeben ist.Source (4, 7) is surrounded.
15. Lateraler Hochvolt-MOS-Transistor nach einem der Ansprüche 12 bis 14, d a d u r c h g e k e n n z e i c h n e t , daß Drain (3, 6) mäander- oder kammartig gestaltet ist.15. Lateral high-voltage MOS transistor according to one of claims 12 to 14, d a d u r c h g e k e n n z e i c h n e t that drain (3, 6) is designed meandering or comb-like.
16. Lateraler Hochvolt-MOS-Transistor nach einem der Ansprüche 12 bis 15, d a d u r c h g e k e n n z e i c h n e t , daß Drain (3, 6) wabenartig gestaltet ist.16. Lateral high-voltage MOS transistor according to one of claims 12 to 15, d a d u r c h g e k e n n z e i c h n e t that drain (3, 6) is honeycomb-shaped.
17. Lateraler Hochvolt-MOS-Transistor nach einem der Ansprüche 12 bis 16, d a d u r c h g e k e n n z e i c h n e t , daß weitere Halbleitergebiete (13, 14) durch Niedertemperatur-Epitaxie mit anschließender Hochvolt-Ionenimplantation vorgesehen sind.17. Lateral high-voltage MOS transistor according to one of claims 12 to 16, d a d u r c h g e k e n n z e i c h n e t that further semiconductor regions (13, 14) are provided by low-temperature epitaxy with subsequent high-voltage ion implantation.
18. Lateraler Hochvolt-MOS-Transistor nach einem der Ansprüche 12 bis 17, d a d u r c h g e k e n n z e i c h n e t , daß sich die Dotierung in den Halbleitergebieten (13, 14) zwischen Source und Drain lateral in der Konzentration verändert. 18. Lateral high-voltage MOS transistor according to one of claims 12 to 17, d a d u r c h g e k e n n z e i c h n e t that the doping in the semiconductor regions (13, 14) changes laterally in concentration between source and drain.
PCT/DE1999/003823 1998-12-07 1999-12-01 Lateral high-voltage semiconductor component with reduced specific closing resistor WO2000035020A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19856402 1998-12-07
DE19856402.3 1998-12-07

Publications (1)

Publication Number Publication Date
WO2000035020A1 true WO2000035020A1 (en) 2000-06-15

Family

ID=7890254

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/003823 WO2000035020A1 (en) 1998-12-07 1999-12-01 Lateral high-voltage semiconductor component with reduced specific closing resistor

Country Status (1)

Country Link
WO (1) WO2000035020A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19958151B4 (en) * 1999-12-03 2006-05-04 Infineon Technologies Ag Lateral high-voltage semiconductor device with reduced specific on-resistance
WO2008132703A1 (en) * 2007-04-30 2008-11-06 Nxp B.V. High-voltage metal-oxide semiconductor device and corresponding manufacturing method and implantation mask
WO2014044748A1 (en) * 2012-09-21 2014-03-27 Elmos Semiconductor Ag Nmos transistor and method for producing it
EP3644374A1 (en) * 2018-10-23 2020-04-29 Infineon Technologies Dresden GmbH & Co . KG Lateral superjunction transistor device and method for producing thereof

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754310A (en) * 1980-12-10 1988-06-28 U.S. Philips Corp. High voltage semiconductor device
EP0514060A2 (en) * 1991-05-06 1992-11-19 SILICONIX Incorporated DMOS transistor structure & method
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
DE4309764A1 (en) * 1993-03-25 1994-09-29 Siemens Ag Power MOSFET
US5378912A (en) * 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
US5432370A (en) * 1992-08-17 1995-07-11 Fuji Electric Co., Ltd. High withstand voltage M I S field effect transistor and semiconductor integrated circuit
GB2309336A (en) * 1996-01-22 1997-07-23 Fuji Electric Co Ltd Drift regions in semiconductor devices
US5726469A (en) * 1994-07-20 1998-03-10 University Of Elec. Sci. & Tech. Of China Surface voltage sustaining structure for semiconductor devices
DE19818300C1 (en) * 1998-04-23 1999-07-22 Siemens Ag Lateral high voltage sidewall transistor

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754310A (en) * 1980-12-10 1988-06-28 U.S. Philips Corp. High voltage semiconductor device
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
EP0514060A2 (en) * 1991-05-06 1992-11-19 SILICONIX Incorporated DMOS transistor structure & method
US5432370A (en) * 1992-08-17 1995-07-11 Fuji Electric Co., Ltd. High withstand voltage M I S field effect transistor and semiconductor integrated circuit
DE4309764A1 (en) * 1993-03-25 1994-09-29 Siemens Ag Power MOSFET
US5378912A (en) * 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
US5726469A (en) * 1994-07-20 1998-03-10 University Of Elec. Sci. & Tech. Of China Surface voltage sustaining structure for semiconductor devices
GB2309336A (en) * 1996-01-22 1997-07-23 Fuji Electric Co Ltd Drift regions in semiconductor devices
DE19818300C1 (en) * 1998-04-23 1999-07-22 Siemens Ag Lateral high voltage sidewall transistor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19958151B4 (en) * 1999-12-03 2006-05-04 Infineon Technologies Ag Lateral high-voltage semiconductor device with reduced specific on-resistance
WO2008132703A1 (en) * 2007-04-30 2008-11-06 Nxp B.V. High-voltage metal-oxide semiconductor device and corresponding manufacturing method and implantation mask
WO2014044748A1 (en) * 2012-09-21 2014-03-27 Elmos Semiconductor Ag Nmos transistor and method for producing it
EP3644374A1 (en) * 2018-10-23 2020-04-29 Infineon Technologies Dresden GmbH & Co . KG Lateral superjunction transistor device and method for producing thereof
US11094780B2 (en) 2018-10-23 2021-08-17 Infineon Technologies Dresden GmbH & Co. KG Lateral superjunction transistor device and method for producing thereof

Similar Documents

Publication Publication Date Title
DE3505393C2 (en) Method of making a vertical diffused field effect transistor
DE112014000679B4 (en) Insulating layer silicon carbide semiconductor device and process for its production
DE19848828C2 (en) Semiconductor device with low forward voltage and high blocking capability
EP1408554B1 (en) Field effect controlled semiconductor component
DE3122768C2 (en)
DE3816002C2 (en)
DE102008039845B4 (en) IGBT with a semiconductor body
DE2706623C2 (en)
DE112011104322T5 (en) Semiconductor device and method for manufacturing a semiconductor device
DE4114174A1 (en) POWER TRANSISTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
WO2000014807A1 (en) High-voltage semiconductor component
DE112019003790T5 (en) SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE
DE19811297A1 (en) Avalanche breakdown resistant MOS devices
DE112017003667B4 (en) Semiconductor device and method of manufacturing a semiconductor device
DE102018203693A1 (en) Semiconductor device
DE102019115161A1 (en) PERFORMANCE DEVICE WITH SUPER TRANSITION AND SCHOTTKY DIODE
DE19640561A1 (en) Insulated gate semiconductor device e.g. power MOSFET or IGBT
EP0913000B1 (en) Field effect controllable semiconductor component
DE102015118616B3 (en) Latchup-solid transistor
WO1999053549A1 (en) Universal semiconductor wafer for high-voltage semiconductor components
DE102021006492A1 (en) SEMICONDUCTOR DEVICE AND METHOD THEREOF
DE102005048447A1 (en) Semiconductor power component e.g. bipolar transistor, for high-voltage application, has charge compensation regions with vertically stacked pn-junctions, where sum of breakdown voltages of junctions is smaller than voltage of drift zones
DE112018002359T5 (en) SEMICONDUCTOR COMPONENT
DE102006002438A1 (en) Semiconductor device and method for its production
DE112018007354T5 (en) SILICON CARBIDE SEMICONDUCTOR UNIT AND MANUFACTURING METHOD FOR THE SAME

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase