WO2000036634A2 - Amorphization of substrate to prevent silicide encroachment into channel region of field effect transistor - Google Patents
Amorphization of substrate to prevent silicide encroachment into channel region of field effect transistorInfo
- Publication number
- WO2000036634A2 WO2000036634A2 PCT/US1999/026865 US9926865W WO0036634A2 WO 2000036634 A2 WO2000036634 A2 WO 2000036634A2 US 9926865 W US9926865 W US 9926865W WO 0036634 A2 WO0036634 A2 WO 0036634A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- source
- substrate
- metal
- drain terminals
- forming
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 40
- 229910021332 silicide Inorganic materials 0.000 title claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims description 10
- 230000005669 field effect Effects 0.000 title claims description 8
- 238000005280 amorphization Methods 0.000 title description 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 25
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 17
- 125000006850 spacer group Chemical group 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 11
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 239000002245 particle Substances 0.000 claims 2
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 20
- 239000004065 semiconductor Substances 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 206010010144 Completed suicide Diseases 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 238000011112 process operation Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 but not limited to Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
Definitions
- the invention relates to the field of semiconductor integrated circuits, and more particularly relates to metal-oxide-semiconductor field effect transistors.
- MOSFETs metal-oxide-semiconductor field effect transistors
- materials such as doped polycrystalline silicon to form the gate electrode, and doped crystalline silicon to form the source/drain terminals.
- Significant effort has been devoted to scaling down the physical dimensions of MOSFETs in order to increase the functionality of integrated circuits by including more transistors on each integrated circuit.
- a MOSFET includes suicided source/drain terminals and a substantially metal-free channel region, wherein the metal is characterized in that it diffuses more easily into the material of the substrate which contains the source/drain terminals than the material of the substrate diffuses into the metal.
- a portion of the source/drain terminals of a MOSFET are converted to an amorphous material prior to being reacted with a metal.
- Fig. 1 is a schematic cross-sectional view of a FET having sidewall spacers and a layer of metal overlying the source/drain terminals, sidewall spacers, and gate electrode.
- Fig. 2 is a schematic cross-sectional view of the FET of Fig. 1, after the layer of metal has been reacted with the source/drain terminals and the gate electrode.
- Fig. 3 is a schematic cross-sectional view of the FET of Fig. 1 , wherein the metal is highly diffusive in the substrate and after the layer of metal has been reacted with the source/drain terminals and the gate electrode, resulting in metal in the transistor channel region.
- Fig. 4 is a schematic cross-sectional view of a FET showing a gate electrode overlying a gate dielectric layer formed on the surface of a substrate, sidewall spacers disposed adjacent the gate electrode, and source/drain terminals self-aligned to the gate electrode and sidewall spacers.
- Fig. 5 is a schematic cross-sectional view of the FET of Fig. 4, after a portion of the source/drain terminals has been converted from a crystalline form to an amorphous form.
- Fig. 6 is a schematic cross-sectional view of the structure of Fig. 5, after a layer of metal, which is highly diffusive in the substrate, has been formed over the source/drain terminals, sidewall spacers, and gate electrode.
- Fig. 7 is a schematic cross-sectional view of the structure of Fig. 6, after the metal has been reacted with the amorphous portion of the source/drain terminals and the gate electrode.
- Fig. 8 is a flow diagram illustrating process operations in accordance with the present invention.
- gate is context sensitive and can be used in two ways when describing integrated circuits. Gate refers to a circuit for realizing an arbitrary logical function when used in the context of a logic gate. However, as used herein, gate refers to the insulated gate terminal of a three terminal FET when used in the context of transistor circuit configurations or formation of transistor structures. The expression “gate terminal” is generally interchangeable with the expression “gate electrode”. A FET can be viewed as a four terminal device when the semiconductor body is considered. However, for the purpose of describing illustrative embodiments of the present invention, the FET will be described using the traditional gate-drain-source, three terminal model.
- Channel refers to that portion of the semiconductor body that underlies the gate dielectric, is bounded by the source/drain terminals, and is the region of the FET where current flows between the source and drain terminals.
- Polycrystalline silicon is a nonporous form of silicon made up of randomly oriented crystallites or domains. Polycrystalline silicon is often formed by chemical vapor deposition from a silicon source gas or other methods and has a structure that contains large-angle grain boundaries, twin boundaries, or both. Polycrystalline silicon is often referred to in this field as polysilicon, or sometimes more simply as poly.
- Suicide refers generally to Si-metal compounds.
- Salicide refers generally to suicide that is self-aligned to some structure, for example, a suicide self-aligned to a FET gate structure.
- Source/drain terminals refer to the terminals of a FET, between which conduction occurs under the influence of an electric field, subsequent to the inversion of the semiconductor surface under the influence of another electric field resulting from a voltage applied to the gate terminal.
- the source and drain terminals are fabricated such that they are geometrically symmetrical. With geometrically symmetrical source and drain terminals it is common to simply refer to these terminals as source/drain terminals, and this nomenclature is used herein.
- Designers often designate a particular source/drain terminal to be a "source” or a “drain” on the basis of the voltage to be applied to that terminal when the FET is operated in a circuit.
- source/drain terminals are doped with either donor (n- type) or acceptor (p-type) atoms to create the desired electrical characteristics.
- a common approach to decreasing the resistivities associated with the scaled down source/drain terminals and gate electrodes has been to form a layer having a relatively low sheet resistivity, in parallel with the source/drain terminals, and also to form such a layer in parallel with the gate electrodes.
- various refractory metal silicides e.g., titanium suicide
- An advantage of such a process in addition to lowering the sheet resistivities mentioned above, is that the source/drain terminals and gate electrodes can be salicided in the same (i.e., a concurrent) process operation. This is true because the metals typically chosen to form the salicided regions react with both the doped crystalline silicon of the source/drain terminals and the polycrystalline silicon of the gate electrodes.
- FIG. 1 is a schematic cross-sectional view showing a prior art FET 100 having sidewall spacers 102 and a layer of metal 104 overlying a pair of source/drain terminals 106, sidewall spacers 102, and a gate electrode 108.
- Gate electrode 108 overlies a gate dielectric layer 110.
- a channel region 112 exists between source/drain terminals 106 and below gate dielectric 110.
- metal layer 104 is titanium.
- Fig. 2 shows a schematic cross-sectional view of FET 100 of Fig. 1, after metal layer 104 has been reacted with source/drain terminals 106 and gate electrode 108.
- the titanium of metal layer 104 reacts with the crystalline silicon of source/drain terminals 106 and the polysilicon of gate electrode 108 to form titanium suicide layers as indicated in Fig. 2.
- Fig. 3 shows a schematic cross-sectional view of FET 100 of Fig.
- an alternative metal layer 104 comprises a metal that is highly diffusive in the substrate and after metal layer 104 has been reacted with source/drain terminals 106 and gate electrode 108.
- the metal reacts with gate electrode 108 to form low resistance layer 120, and reacts with source/drain terminals 106 to form low resistance layers 118.
- low resistance layer 118 extends laterally through source/drain terminal 106 resulting in metal atoms physically occupying locations in transistor channel region 112. This phenomenon may also be referred to as silicide encroachment into the transistor channel.
- a metal such as nickel has been used, rather than titanium as shown in the example of Fig. 2.
- Embodiments of the present invention include salicided source/drain terminals wherein the metal salicide is formed from a metal that is highly diffusive in a substrate material such as, but not limited to, silicon.
- a substrate material such as, but not limited to, silicon.
- Fig. 4 shows a schematic cross-sectional view of a FET having gate electrode 108 overlying gate dielectric layer 110 formed on the surface of a substrate.
- Sidewall spacers 102 are disposed adjacent gate electrode 108, and source/drain terminals 106 are self-aligned to gate electrode 108 and sidewall spacers 102. That is, source/drain terminals 106 are substantially adjacent to sidewall spacers 102 and gate electrode 108.
- source/drain terminals 106 are shown completely disposed in the substrate in Fig. 4, it will be recognized that source/drain terminals may be partially in the substrate and partially raised above the substrate. No limitation on the exact geometries of the various constituent parts of the FET are intended herein.
- a transistor such as that shown in Fig. 4 may then be further processed, in accordance with the present invention, in order that salicided source/drain terminals may be formed with metals that are highly diffusive in silicon.
- Fig. 5 shows a schematic cross-sectional view of the FET of Fig. 4, after a portion of source/drain terminals 106 has been converted from a crystalline form to an amorphous form. That is an amorphous silicon (a-Si) layer 122 is created in an upper region of source/drain terminals 106.
- upper region refers to those portions of source/drain terminals 106 that are relatively closer to the surface of the substrate than other portions of source/drain terminals 106.
- a-Si layers 122 are formed by the ion implantation of silicon into the surface of source/drain terminals 106.
- Implant species, dose, and energy are selected to achieve a specific amorphous depth.
- the targeted depth of a-Si 122 is determined, at least in part, by the thickness of a metal layer with which a-Si 122 is to be reacted.
- an a-Si 122 depth of approximately 40 nm is selected. This can be accomplished by performing an ion implant operation of Si at an energy of approximately 20 keV and a dose of approximately 5xl0 l4 /cm 2 .
- Ge ions may be implanted at, for example, an energy of 40kev and a dose of 2xl0 14 /cm 2 .
- any suitable set of ion implantation specifications that produces an amorphous portion in the source/drain terminals may be used.
- the depth of the amorphous portion of the source/drain terminals is chosen such that the reaction between the metal and the amorphous silicon effectively results in the silicide remaining in the region of the source/drain terminals that was converted to amorphous form.
- Fig. 5 also shows an amorphous region 123 that is formed in the upper portion of gate electrode 108.
- Amorphous region 123 is created by the ion implantation that creates a-Si layers 122.
- Fig. 6 shows a schematic cross-sectional view of the structure of Fig. 5, after a layer of metal 124, which is highly diffusive in the substrate, has been formed over a-Si 122 of source/drain terminals 106, sidewall spacers 102, and gate electrode 108.
- metal 124 is nickel.
- Metal 124 may be deposited by any suitable, well-known process such as, but not limited to, sputtering. Alternatively, metal 124 may be deposited by a physical vapor deposition (PVD) operation.
- PVD physical vapor deposition
- Fig. 7 shows a schematic cross-sectional view of the structure of Fig. 6, after metal 124 has been reacted with amorphous portion 122 of source/drain terminals 106 to form salicided regions 126; and with gate electrode 108 to form salicided region 120.
- the reaction conditions include placing the wafer into an N, ambient at approximately 500°C for approximately 10 seconds. Those skilled in the art will recognize that various ranges of times and temperatures may be used to achieve the desired reaction.
- an insulated gate FET structure including gate electrode, gate insulator, and source/drain terminals, is formed 202 on a substrate in accordance with well-known microelectronic manufacturing operations. Subsequently, a portion of the source/drain terminals are converted 204 to amorphous form.
- the substrate is a silicon wafer
- the conversion operation is typically achieved by ion implantation of silicon. The implantation of silicon into the doped crystalline silicon regions that make up the source/drain terminals results in a layer of a-Si.
- a metal is deposited 206, typically over the entire surface of the substrate.
- a blanket deposition of metal although typical, is not required by the present invention.
- the metal that is over the a-Si is reacted 208 with the a-Si, such that the a-Si is substantially consumed and a low resistance layer is formed.
- Typical reaction conditions include placing the wafer in an N 2 ambient at approximately 500°C, for approximately 10 seconds.
- Embodiments of the present invention provide an a-Si/c-Si boundary to block silicide encroachment into the transistor channel.
- An a-Si region is typically produced in the source/drain terminals by ion implantation prior to metal deposition.
- the a-Si depth is chosen such that it will just be consumed by the metal to form silicide, and such that substantially none of the a-Si remains after the silicidation process.
- the metal is believed to react preferentially with the a-Si to form the silicide because the a-Si has a higher energy than c-Si and is therefore more reactive.
- the boundary between the a-Si and c-Si essentially serves as a barrier against further reaction or metal diffusion into the c-Si substrate.
- An advantage of embodiments of the present invention is lower sheet resistivities for polysilicon and source/drain terminals than is achievable with other metal silicides such as titanium silicide.
- a further advantage of the present invention is that encroachment of metal into the channel region of field effect transistors is avoided.
- metals such as, but not limited to cobalt (Co) may be used rather than nickel.
- the present invention is not limited to silicon substrates.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU16217/00A AU1621700A (en) | 1998-12-16 | 1999-11-12 | Amorphization of substrate to prevent silicide encroachment into channel region of field effect transistor |
KR1020017007390A KR20010089572A (en) | 1998-12-16 | 1999-11-12 | Amorphization of substrate to prevent silicide encroachment into channel region of field effect transistor |
JP2000588792A JP2003526198A (en) | 1998-12-16 | 1999-11-12 | Amorphization of substrate to prevent intrusion of silicide into channel region of field effect transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US21255398A | 1998-12-16 | 1998-12-16 | |
US09/212,553 | 1998-12-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2000036634A2 true WO2000036634A2 (en) | 2000-06-22 |
WO2000036634A3 WO2000036634A3 (en) | 2002-06-27 |
Family
ID=22791505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1999/026865 WO2000036634A2 (en) | 1998-12-16 | 1999-11-12 | Amorphization of substrate to prevent silicide encroachment into channel region of field effect transistor |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP2003526198A (en) |
KR (1) | KR20010089572A (en) |
AU (1) | AU1621700A (en) |
WO (1) | WO2000036634A2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10250611A1 (en) * | 2002-10-30 | 2004-05-19 | Advanced Micro Devices, Inc., Sunnyvale | Method for producing a nickel silicide region in a semiconductor region containing doped silicon |
EP1489647A2 (en) * | 2003-06-20 | 2004-12-22 | STMicroelectronics S.A. | Method of manufacturing a silicide |
US7022595B2 (en) | 2003-06-20 | 2006-04-04 | Stmicroelectronics Sa | Method for the selective formation of a silicide on a wafer using an implantation residue layer |
US7105429B2 (en) | 2004-03-10 | 2006-09-12 | Freescale Semiconductor, Inc. | Method of inhibiting metal silicide encroachment in a transistor |
KR100738066B1 (en) | 2003-12-01 | 2007-07-12 | 삼성전자주식회사 | Method of forming silicide film having excellent thermal stability, semiconductor device and semiconductor memory device comprising silicide film formed by the same, and methods of manufacturing the same |
US8053289B2 (en) | 2007-10-16 | 2011-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method for thin film transistor on insulator |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5691212A (en) * | 1996-09-27 | 1997-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS device structure and integration method |
US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
US5766997A (en) * | 1909-11-30 | 1998-06-16 | Nkk Corporation | Method of forming floating gate type non-volatile semiconductor memory device having silicided source and drain regions |
US5807770A (en) * | 1995-03-13 | 1998-09-15 | Nec Corporation | Fabrication method of semiconductor device containing semiconductor active film |
US5899720A (en) * | 1994-12-28 | 1999-05-04 | Nec Corporation | Process of fabricating salicide structure from high-purity reproducible cobalt layer without sacrifice of leakage current and breakdown voltage of P-N junction |
US6010936A (en) * | 1996-11-27 | 2000-01-04 | Lg Semicon Co., Ltd. | Semiconductor device fabrication method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62122173A (en) * | 1985-11-20 | 1987-06-03 | Fujitsu Ltd | Semiconductor device |
JPH05136398A (en) * | 1991-11-15 | 1993-06-01 | Toshiba Corp | Manufacture of semiconductor device |
-
1999
- 1999-11-12 WO PCT/US1999/026865 patent/WO2000036634A2/en not_active Application Discontinuation
- 1999-11-12 KR KR1020017007390A patent/KR20010089572A/en not_active Application Discontinuation
- 1999-11-12 AU AU16217/00A patent/AU1621700A/en not_active Abandoned
- 1999-11-12 JP JP2000588792A patent/JP2003526198A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5766997A (en) * | 1909-11-30 | 1998-06-16 | Nkk Corporation | Method of forming floating gate type non-volatile semiconductor memory device having silicided source and drain regions |
US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
US5899720A (en) * | 1994-12-28 | 1999-05-04 | Nec Corporation | Process of fabricating salicide structure from high-purity reproducible cobalt layer without sacrifice of leakage current and breakdown voltage of P-N junction |
US5807770A (en) * | 1995-03-13 | 1998-09-15 | Nec Corporation | Fabrication method of semiconductor device containing semiconductor active film |
US5691212A (en) * | 1996-09-27 | 1997-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS device structure and integration method |
US6010936A (en) * | 1996-11-27 | 2000-01-04 | Lg Semicon Co., Ltd. | Semiconductor device fabrication method |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10250611A1 (en) * | 2002-10-30 | 2004-05-19 | Advanced Micro Devices, Inc., Sunnyvale | Method for producing a nickel silicide region in a semiconductor region containing doped silicon |
DE10250611B4 (en) * | 2002-10-30 | 2006-01-26 | Advanced Micro Devices, Inc., Sunnyvale | A method for producing a metal silicide region in a semiconductor region containing doped silicon |
EP1489647A2 (en) * | 2003-06-20 | 2004-12-22 | STMicroelectronics S.A. | Method of manufacturing a silicide |
US7022595B2 (en) | 2003-06-20 | 2006-04-04 | Stmicroelectronics Sa | Method for the selective formation of a silicide on a wafer using an implantation residue layer |
EP1489647A3 (en) * | 2003-06-20 | 2007-08-29 | STMicroelectronics S.A. | Method of manufacturing a silicide |
KR100738066B1 (en) | 2003-12-01 | 2007-07-12 | 삼성전자주식회사 | Method of forming silicide film having excellent thermal stability, semiconductor device and semiconductor memory device comprising silicide film formed by the same, and methods of manufacturing the same |
US7105429B2 (en) | 2004-03-10 | 2006-09-12 | Freescale Semiconductor, Inc. | Method of inhibiting metal silicide encroachment in a transistor |
US8053289B2 (en) | 2007-10-16 | 2011-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method for thin film transistor on insulator |
US8664722B2 (en) | 2007-10-16 | 2014-03-04 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor with metal silicide layer |
Also Published As
Publication number | Publication date |
---|---|
WO2000036634A3 (en) | 2002-06-27 |
AU1621700A (en) | 2000-07-03 |
KR20010089572A (en) | 2001-10-06 |
JP2003526198A (en) | 2003-09-02 |
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