WO2000044087A2 - Down-converter using sine to square wave converter - Google Patents

Down-converter using sine to square wave converter Download PDF

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Publication number
WO2000044087A2
WO2000044087A2 PCT/US2000/001108 US0001108W WO0044087A2 WO 2000044087 A2 WO2000044087 A2 WO 2000044087A2 US 0001108 W US0001108 W US 0001108W WO 0044087 A2 WO0044087 A2 WO 0044087A2
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WO
WIPO (PCT)
Prior art keywords
signal
frequency
module
aliasing
converted
Prior art date
Application number
PCT/US2000/001108
Other languages
French (fr)
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WO2000044087A3 (en
WO2000044087A9 (en
Inventor
David F. Sorrells
Michael J. Bultman
Charles D. Clements
Robert W. Cook
Joseph M. Hamilla
Richard C. Looke
Charley D. Moses, Jr.
Gregory S. Silver
Original Assignee
Parkervision, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/476,091 external-priority patent/US6704558B1/en
Priority claimed from US09/476,093 external-priority patent/US7006805B1/en
Priority claimed from US09/476,330 external-priority patent/US6704549B1/en
Priority claimed from US09/476,092 external-priority patent/US7209725B1/en
Application filed by Parkervision, Inc. filed Critical Parkervision, Inc.
Priority to AU29672/00A priority Critical patent/AU2967200A/en
Publication of WO2000044087A2 publication Critical patent/WO2000044087A2/en
Publication of WO2000044087A3 publication Critical patent/WO2000044087A3/en
Publication of WO2000044087A9 publication Critical patent/WO2000044087A9/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing

Definitions

  • the present invention is generally directed toward receiver-transmitter systems referred to as Family Radio Service (FRS) units, although the invention is not limited to this embodiment.
  • the Family Radio Service is one of the citizens Band Radio Services. It is intended for the use of family, friends, and associates to communicate among themselves within a neighborhood or while on group outings.
  • the FRS unit channel frequencies are:
  • Modern day communication systems employ components such as transmitters and receivers to transmit information from a source to a destination. To accomplish this transmission, information is imparted on a carrier signal and the carrier signal is then transmitted.
  • the carrier signal is at a frequency higher than the baseband frequency of the information signal. Typical ways that the information is imparted on a carrier signal are called modulation.
  • the present invention is directed to a communications system with an image-reject down-converter and to a communications system comprising a method and system for directly down-converting FM signals to demodulated baseband information signals.
  • the invention has a number of aspects, including an image-reject down-converter, an ultra-low power down-converter, and a high-efficiency transmitter and can be used to directly down- convert analog FM signals and digital FM signals to demodulated baseband information signals.
  • the present invention is used in a family radio system. It is to be understood, however, that the invention is not limited to this particular embodiment.
  • the invention includes aliasing an FM signal at an aliasing rate substantially equal to the frequency of the FM signal or substantially equal to a sub- harmonic thereof; adjusting the aliasing rate in accordance with frequency changes on the
  • the FM signal to maintain the aliasing rate substantially equal to the frequency of the FM signal; and outputting a demodulated baseband information signal.
  • the invention includes an optional step of compensating for phase delays and/or other characteristics of the loop in order to maintain bandwidth and stability for the loop.
  • the invention is implemented as a zero IF FM decoder that down-converts an FM signal as an I and Q pair, sums the I and Q pair, and generates a correction signal from the sum.
  • the correction signal is used to adjust the aliasing rate to continually alias the FM signal at a sub-harmonic of the FM signal - even as the FM signal changes frequency.
  • the invention is implemented as an ultra-low power down- converter.
  • the present invention is also directed toward a multi-mode, multi-band communication system that can transmit and/or receive one or more information signals on one or more transmission frequencies using one or more modulation schemes.
  • An embodiment of the invention is directed to a receiver having multi-mode and multi-band functionality and capabilities.
  • the receiver is capable of selectively operating over a plurality of bands and channels.
  • the receiver operates in a plurality of modes, including but not limited to a single band/channel mode, and a multiple band/channel mode.
  • the receiver may form a portion of a transceiver.
  • Another embodiment of the invention is a transmission subsystem of the communications system.
  • the up-conversion section is implemented using a universal frequency translator (UFT).
  • UFT universal frequency translator
  • the transmission subsystem may form a portion of a transceiver.
  • the present invention is used in a family radio system. It is to be understood, however, that the invention is not limited to this particular embodiment. Other implementations in communications-related environments are within the scope and spirit of the invention.
  • the present invention has a number of advantages, including power reduction, tuning reduction, parts reduction, price reduction, size reduction, performance increase, greater efficiency, and increased integration possibilities.
  • FIG. 1 illustrates an exemplary block diagram of an ultra-low power down-converter in accordance with the present invention
  • FIG. 2 illustrates a schematic drawing of an exemplary implementation of the ultra- low power down-converter of FIG. 1 ;
  • FIG. 3 illustrates an exemplary block diagram of the universal frequency translator module being used in the ultra-low power down-converter embodiment of the present invention
  • FIG. 4 illustrates a process for directly down-converting an FM signal to a demodulated baseband information signal
  • FIG. 5 is a block diagram of an exemplary zero LF FM decoder for implementing the process of FIG. 4;
  • FIG. 6A is a timing diagram of an exemplary FM signal
  • FIG. 6B is a timing diagram of an exemplary first aliasing signal, in accordance with the present invention.
  • FIG. 6C is a timing diagram of an exemplary second aliasing signal, in accordance with the present invention.
  • FIG. 6D is a timing diagram of exemplary down-converted signals and a summation signal, in accordance with the present invention
  • FIG. 6E illustrates an exemplary control signal for controlling an aliasing rate for directly down-converting an FM signal to a demodulated baseband information signal, in accordance with the present invention
  • FIG. 7 is a schematic diagram of an exemplary implementation of a summing module, an integration module and an optional loop compensation module, in accordance with the present invention.
  • FIG. 8 illustrates an exemplary block diagram of a transmitter embodiment of the present invention
  • FIG. 9 illustrates an exemplary block diagram of the universal frequency translator module being used in a transmitter embodiment of the present invention
  • FIG. 10 is a schematic diagram of an exemplary implementation of the transmitter embodiment illustrated in FIG. 8
  • FIG. 11 illustrates an exemplary implementation of a switch in the universal frequency translator module of FIG. 9;
  • FIG. 12a illustrates an exemplary mixer circuit
  • FIG. 12b illustrates an exemplary frequency domain plot corresponding to the mixed circuit of FIG. 12a
  • FIG. 13a illustrates an exemplary block diagram of the image-reject down-converter embodiment of the present invention
  • FIG. 13b illustrates a frequency domain plot of waveforms associated with the exemplary block diagram of FIG. 13a
  • FIG. 13c illustrates a phase relationship table for waveforms associated with the exemplary block diagram of FIG. 13a;
  • FIGs. 14a and 14b illustrate a detailed schematic drawing of the exemplary block diagram of FIG. 13a;
  • FIG. 15 is a block diagram of a receiver according to an embodiment of the invention.
  • FIG. 16 is a block diagram of a receiver according to an alternative embodiment of the invention.
  • FIG. 17 is a flowchart of the invention when operating according to a single band/channel mode
  • FIG. 18 is a flowchart of the invention when operating according to a multiple band/channel mode
  • FIG. 19 is a block diagram of a transceiver according to an embodiment of the invention.
  • FIG. 20 illustrates an exemplary use scenario used to described the operation of an embodiment of the invention
  • FIG. 21 is a top level block diagram of one embodiment of the transmitter subsystem of the present invention
  • FIG. 22 is a block diagram of an exemplary embodiment of the information signal conditioning module and the signal selection module
  • FIG. 23 is a block diagram of an exemplary embodiment of the modulation and frequency selection module and an exemplary embodiment of the bias/reference signal module;
  • FIG. 24 illustrates an exemplary block diagram of the universal frequency translator module being used in the transmitter subsystem embodiment of the present invention
  • FIG.25 illustrates an exemplary implementation of a switch in the universal frequency translator module of FIG. 4;
  • FIG. 26 illustrates an exemplary structure for a frequency band selection module;
  • FIG.27 illustrates an exemplary structure for the optional output conditioning module
  • FIGs.28A-28D depict some frequency allocations operable with the present invention
  • FIG.29 illustrates equations for determining charge transfer, in accordance with the present invention
  • FIG. 30 illustrates relationships between capacitor charging and aperture, in accordance with the present invention
  • FIG. 31 illustrates relationships between capacitor charging and aperture, in accordance with the present invention
  • FIG.32 illustrates power-charge relationship equations, in accordance with the present invention
  • FIG. 33 illustrates insertion loss equations, in accordance with the present invention
  • FIG.34 illustrates a flowchart of state machine operation according to an embodiment of the present invention
  • FIG. 35 is a block diagram of a universal frequency up-conversion (UFU) module according to an embodiment of the invention.
  • FIG. 36 is a more detailed diagram of a universal frequency up-conversion (UFU) module according to an embodiment of the invention.
  • FIG. 37 is a block diagram of a universal frequency up-conversion (UFU) module according to an alternative embodiment of the invention.
  • FIGs. 38A-38I illustrate exemplary waveforms used to describe the operation of the UUFU
  • FIG. 39 illustrates a unified down-converting and filtering (UDF) module according to an embodiment of the invention
  • FIG. 40 is a table of exemplary values at nodes in the UDF module of FIG. 41 ; and FIG. 41 is a detailed diagram of an exemplary UDF module according to an embodiment of the invention. Detailed Description of the Preferred Embodiments
  • Multi-mode/Multi-band Receiver 5.3.3 Multiple Band/Channel Operation of the Multi-mode/Multi-band Receiver 6. Multi -mode and Multi -band Transmitter 7. Down-conversion Using a Universal Frequency Translation Module.
  • the present invention can be implemented with an aliasing system as described herein in the section entitled “Down-conversion Using a Universal Frequency Translation Module.”
  • FIG. 1 illustrates an exemplary aliasing system 100 for down-converting electromagnetic (EM) signals, such as an RF input (RF ⁇ n ) signal 102.
  • the aliasing system 100 is an exemplary embodiment of an optimized aliasing system, referred to herein as an ultra low power down-converter.
  • the exemplary aliasing system 100 includes an aliasing module 110 that aliases an aliasing module 110 .
  • Aliasing system 100 optionally includes one or more of an input impedance match module 1 18, a parallel resonant tank module 120, and an output impedance match module 122.
  • Aliasing system 100 optionally includes a local oscillator (LO) impedance match module 124 for impedance matching a local oscillator input (LO m ) signal 126, generated by a local oscillator 128, to the aliasing module 110.
  • the LO impedance match module 124 can be designed to increase the voltage of the LO in signal 126, as illustrated by a higher voltage LO in signal 130.
  • the LO impedance match module 124 permits the aliasing system 100 to efficiently operate with a relatively low voltage LO in signal 126, without the use of power consuming amplifiers that would otherwise be necessary to increase the amplitude of the LO jn signal 126.
  • the aliasing signal 114 is used interchangeably herein to refer to the LO in signal 126 and or the higher voltage LO jn signal 130.
  • the aliasing system 100 optionally includes a DC block 132 that substantially blocks DC while passing substantially all non-DC.
  • the DC block 132 is a capacitor 133.
  • a variety of implementations of the DC block 132 suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein.
  • the aliasing system 100 optionally includes a bias module 134 for biasing the aliasing signal 114.
  • a bias module 134 for biasing the aliasing signal 114.
  • a variety of implementations of the biasing module 134 suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein.
  • FIG. 2 illustrates an exemplary schematic diagram 202 that can be used to implement the aliasing system 100.
  • the exemplary schematic diagram 202 provides exemplary circuit elements that can be used within the optional input impedance match module 118, the optional parallel resonant tank 120, the optional output impedance match module 122, the optional LO impedance match module, the optional DC block 132, and the optional bias module 134.
  • the invention is not limited to the exemplary embodiment of FIG. 2.
  • the exemplary schematic diagram 202 includes a storage module 210 for storing energy transferred from the EM signal 112 as described herein in the section entitled
  • the aliasing module 110 of FIG. 1 is illustrated as an application specific integrated circuit (ASIC) 212.
  • the ASIC is implemented in complementary metal oxide semiconductor (CMOS).
  • CMOS complementary metal oxide semiconductor
  • the ASIC 212 is coupled to a first voltage source 218 for supplying power circuits within the ASIC 212.
  • the circuits within the ASIC 212 are described below with reference to FIG. 3.
  • An optional first bypass module 220 is optionally disposed as illustrated to substantially eliminate unwanted frequencies from the first power supply 218 and from the ASIC 212.
  • the ASIC 212 includes a substrate (not shown) which is optionally coupled to a second voltage source 214.
  • a substrate not shown
  • An advantage of coupling the substrate to the second voltage source 214 is described below with reference to FIG. 3.
  • an optional second bypass module 216 is optionally disposed as illustrated to substantially eliminate unwanted frequencies from the substrate and the second voltage source 214.
  • FIG. 3 illustrates an aliasing module 302, which is an exemplary embodiment of the aliasing module 110 and the ASIC 212.
  • the aliasing module 302 includes a sine wave to square wave converter module 310, a pulse shaper module 312 and a switch module 314.
  • the sine wave to square wave converter module 310 converts a sine wave 1 14 from the local oscillator 128 to a square wave 311.
  • the pulse shaper module 312 receives the square wave 311 and generates energy transfer pulses 313 therefrom. Energy transfer pulses are discussed in greater detail in the section entitled "Down-conversion Using a
  • the pulse shaper module 312 is implemented as a mono-stable multi-state vibrator.
  • a variety of implementations of the pulse shaper module 312 suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein.
  • the frequency of the energy transfer pulses 31 1 is determined by the frequency of the aliasing signal 114 and the width or aperture of the energy transfer pulses is determined by the pulse shaper module 312.
  • the ASIC substrate In the illustrated embodiment, where the sine wave to square wave converter module 310 and the pulse shaper module 312 are provided on-chip, the ASIC substrate
  • the second power supply 214 can be varied to affect the performance of the circuits on the ASIC 212, with a result of effectively adjusting the pulse width of the energy transfer pulses 313.
  • the sine wave to square wave converter module 310 and/or the pulse shaper module 312 are provided off-chip.
  • An advantage of the ultra-low power down-converter aliasing system 100 is its low power consumption.
  • the aliasing module 302 required an average of approximately 1 mA and consumed approximately 3 to 5 m Watt. This is significantly greater performance than conventional down converter systems.
  • ultra-low power down-converter aliasing system 100 advantages include tuning reduction, parts reduction, price reduction, size reduction, performance increase, low frequency and power LO, and excellent linearity.
  • Another advantage of the ultra-low power down-converter aliasing system is that it can down-convert EM signals as high as 3.5 GHz when implemented in CMOS. Higher frequencies can be down- converted using other materials such as gallium arsenide (GaAs), for example.
  • GaAs gallium arsenide
  • an ultra-low power down-converter as described above is implemented in an FRS.
  • the section entitled "Down-conversion Using a Universal Frequency Translation Module” describes methods and systems for directly down-converting EM signals.
  • modulated EM signals can be directly down- converted to demodulated baseband information signals (also referred to interchangeably herein as direct to data or D2D embodiments).
  • demodulated baseband information signals also referred to interchangeably herein as direct to data or D2D embodiments.
  • AM amplitude modulated
  • PM phase modulated
  • FM Frequency modulated
  • FM frequency shift keying
  • PSK phase shift keying
  • FM signals unlike AM and PM signals, are not necessarily directly down-converted to demodulated baseband information signals by aliasing at a fixed sub-harmonic.
  • the present invention is a method and system for directly down-converting FM signals to demodulated baseband information signals.
  • FIG. 4 is a flowchart 402 that illustrates a method for directly down-converting FM signals to demodulated baseband information signals.
  • FIG. 5 illustrates an exemplary embodiment of a zero IF FM decoder 502, which can be used to implement the process illustrated in the flowchart 402.
  • the process illustrated in the flowchart 402 is not, however, limited to the zero IF FM decoder 502.
  • the process illustrated in the flowchart 402 can be practiced by other systems as well.
  • the zero EF FM decoder 502 includes a first aliasing module 510 and a second aliasing module 512.
  • the first and second aliasing modules 510 and 512 are implemented as described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module” and may be optimized as illustrated in FIGS. 1- 3 of the present application and as described above.
  • Other components of the zero IF FM decoder 502 are described below with the description of the process flowchart 402.
  • the process begins at step 410, which includes aliasing an FM signal at an aliasing rate substantially equal to the frequency of the FM signal or substantially equal to a sub harmonic thereof.
  • step 410 is performed by the first and second aliasing module 510 and 512.
  • the first aliasing module 510 receives an FM signal 514 and a first a LO signal 516.
  • the first LO signal 516 is substantially equal to the frequency of the FM signal 514 or a sub-harmonic thereof. Details of maintaining the LO signal 516 at the frequency of the FM signal 514, or a sub-harmonic thereof, is described in connection with step 412 below.
  • the first aliasing module 510 uses the first LO signal 516 to down-convert the FM signal 514 to a first down-converted signal 518, as described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module.”
  • the second aliasing module 512 also receives the FM signal 514 and a second LO signal 520.
  • the first LO signal 516 and the second LO signal 520 are substantially similar except that one is shifted in phase relative to the other. This is performed by, for example, a phase shifter 524.
  • a variety of implementations of the phase shifter 524 suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein.
  • the first and second LO signals 516 and 520 are separated by period of the FM signal 514, or any multiple of a period of the FM signal 514 plus A period. Other phase differences are contemplated and are within the scope of the present invention.
  • the second aliasing module 512 uses the second LO signal 520 to down-convert the FM signal 514 to a second down-converted signal 522, as described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module.”
  • Step 412 includes adjusting the aliasing rate in accordance with frequency changes on the FM signal to maintain the aliasing rate substantially equal to the frequency of the FM signal.
  • the resultant down-converted signal is substantially a constant level.
  • the first and second down-converted signals 518 and 522 should generally be constant signals.
  • the zero IF FM decoder 502 maintains the phase of the aliasing signal 538 so that the phase of one of the aliasing signals 516 or 520 slightly leads the FM signal 514 while phase of the other aliasing signal slightly lags the FM signal 514.
  • one of the down-converted signals 518 or 522 is a constant level above DC while the other down-converted signal is a constant level below DC.
  • the sum of the down-converted signals 518 and 522 is thus substantially zero.
  • Summation of the down- converted signals 518 and 522 is performed by a summing module 526, which outputs a summation signal 536.
  • summation signal 536 When summation signal 536 tends away from zero, it indicates that the frequency of the FM signal 514 is changing.
  • the summation signal 536 is integrated by an integrator module 528, which outputs a control signal 532.
  • the control signal 532 controls a voltage controlled oscillator (VCO) 534, which outputs the aliasing signal 538.
  • VCO voltage controlled oscillator
  • the integrator maintains the control signal at a level necessary to insure that the FM signal 514 is aliased at a sub harmonic of the FM signal - even as the FM signal 514 changes frequency.
  • FIG. 7 illustrates, among other things, exemplary implementation details of the summing module 526 and the integrator module 528.
  • FIGS. 6A-6D illustrate exemplary timing diagrams for the above description.
  • FIG. 6A illustrates an exemplary FM signal 514.
  • FIG. 6B illustrates a first aliasing signal 612, which is generated within the first aliasing module 510 from the first LO signal 516.
  • FIG. 6C illustrates a second aliasing signal 614, which is generated within the second aliasing module 512 from the second LO signal 520.
  • the first LO signal 612 aliases the FM signal 514 at approximately the same positive position on successive periods.
  • the result is illustrated in FIG. 6D as down- converted signal 518.
  • the second LO signal 614 aliases the FM signal 514 at approximately the same negative position on successive periods. The result is illustrated in
  • FIG. 6D as down-converted signal 522.
  • FIG. 6D illustrates the sum of the down-converted signals 518 and 522 as summation signal 536.
  • control signal 532 changes accordingly so that the VCO 534 changes the aliasing rate of the aliasing signal 538 so that the sum of the down-converted signals 518 and 520, summation signal 536, is maintained at zero.
  • the control signal 532 changes in proportion to frequency changes on the FM signal 514.
  • the changes on the FM signal 514 form a demodulated baseband information signal, which represents the information that had been frequency modulated on the FM signal 514.
  • the integrator module 528 changes the control signal 532 to track and follow the deviation. This will reproduce - within the bandwidth of the loop - any arbitrary wave form, including analog and digital.
  • the invention tracks frequency changes on the FM signal by aliasing the FM signal at a sub-harmonic of the FM signal, adjusting the aliasing rate as necessary to maintain the aliasing rate at the sub-harmonic - even as the FM signal changes frequency.
  • the aliasing rate changes in proportion to frequency changes on the FM signal.
  • changes to the aliasing rate are directly indicative of the information modulated on the FM signal.
  • changes to the aliasing rate are indicated by the control voltage 532, which controls the VCO 534, which determines the aliasing rate.
  • FIG. 6E illustrates an exemplary control signal 532 for controlling the aliasing rate for directly down-converting the exemplary FM signal 514 illustrated in FIG. 6 A to a demodulated baseband information signal.
  • the control signal 532 has a first amplitude during time Tl, when the FM signal 514 is at a first frequency.
  • the control signal 532 has a second amplitude during time T2, when the FM signal 514 is at a second frequency.
  • the control signal 532 reverts to the first amplitude during time T3, when the FM signal 514 returns to the first frequency.
  • FIGS. 6A-6E are exemplary illustrations of the invention. Other timing diagrams will apply for different situations, all of which are within the scope of the present invention.
  • Step 414 includes outputting a demodulated baseband information signal. In FIG. 5, this is performed by outputting the control signal 532 as a demodulated baseband information signal
  • An optional step 416 includes compensating for phase delays and/or other characteristics of the loop in order to maintain bandwidth and stability for the loop.
  • step 416 is performed by an optional loop compensator module 530.
  • FIG. 7 illustrates exemplary implementation details of the loop compensation module 530. A variety of other loop compensation modules suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein.
  • a zero IF FM decoder as described above is implemented in an FRS.
  • This section describes the high-efficiency transmitter embodiment of a frequency up-converter for use in the family radio system. It describes methods and systems related to a transmitter. Structural exemplary embodiments for achieving these methods and systems are also described. It should be understood that the invention is not limited to the particular embodiments described below. Equivalents, extensions, variations, deviations, etc., of the following will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such equivalents, extensions, variations, deviations, etc., are within the scope and spirit of the present invention. The present invention has significant advantages over conventional transmitters.
  • FIG. 4 An embodiment for transmitting a voice signal is shown in FIG. 4.
  • the voice signal is input to a microphone 402.
  • the output of microphone 402 is an analog voice signal 424 which is connected to an audio amplifier 404.
  • the output of audio amplifier 404 is an amplified signal 426 which is filtered by an audio buffer amplifier 406.
  • Audio buffer amplifier 406 acts as a low pass filter to eliminate unwanted higher frequency signals.
  • the output of audio buffer amplifier 406 is a signal 428 which is accepted by crystal oscillator 408.
  • Crystal oscillator 408 operates as a voltage controlled oscillator and outputs a frequency modulated (FM) signal 430 that is a sinusoidal signal biased substantially around zero volts.
  • FM frequency modulated
  • a bias voltage 410 combines with FM signal 430.
  • bias voltage 410 is a positive voltage
  • UFT module 412 is comprised of a pulse shaping circuit and a switch, and is described in detail below in FIG. 6.
  • the output of UFT module 412 is a rectangular waveform 434 that contains a plurality of harmonics.
  • Rectangular waveform 434 is accepted by a filter 416 which filters out the undesired harmonic frequencies and outputs a desired output signal 436.
  • Desired output signal 436 is the frequency modulated signal at the desired output frequency. Desired output signal 436 goes to a driver 418 and then to a power amplifier 420. The output of power amplifier 420 is an amplified output signal 430. Amplified output signal 430 is ready for transmission and is routed to an antenna 422.
  • the design of UFT module 412 is shown in FIG. 6.
  • FM control signal 432 is accepted by a "square-up" circuit 602 to create a frequency modulated square wave 608 from the sinusoidal waveform of FM control signal 432.
  • FM square wave 608 is then routed to a pulse shaper 604 to create a string of pulses 610.
  • pulse shaper 604 is a mono-stable multivibrator.
  • the string of pulses 610 operates a switch 606 which creates rectangular waveform 434.
  • pulse shaper 604 is designed such that each pulse in string of pulses 610 has a pulse width " ⁇ " that is substantially equal to
  • switch 606 outputs rectangular waveform 434, which is then routed to filter 416 of FIG. 4.
  • bias signal 414 Another input to UFT module 412 is bias signal 414, which, in this embodiment, is connected to the opposite terminal of switch 606 from rectangular waveform 434.
  • switch 606 is a field effect transistor (FET).
  • FET field effect transistor
  • FIG 9. A specific implementation wherein the FET is a complementary metal oxide semiconductor (CMOS) FET is shown is FIG 9.
  • CMOS FET has three terminals: a gate 902, a source 904, and a drain 906.
  • String of pulses 610 is shown at gate 902
  • bias signal 414 is shown at source 904,
  • rectangular waveform 434 is shown at drain 906.
  • CMOS FET has three terminals: a gate 902, a source 904, and a drain 906.
  • String of pulses 610 is shown at gate 902
  • bias signal 414 is shown at source 904
  • rectangular waveform 434 is shown at drain 906.
  • Numerous circuit designs are available to eliminate any possible asymmetry, which will be understood by one skilled in the relevant art(s).
  • FIG. 8 is a detailed schematic drawing of the embodiment described above. Those skilled in the relevant art(s) will appreciated that numerous circuit designs can be used, and that FIG. 8 is shown for illustrative purposes only, and is not limiting. In addition, there are a variety of commercially available components and assemblies suitable for use in the present invention (e.g., audio amplifiers, audio buffer amplifiers, crystal oscillators, drivers, and power amplifiers) as will be apparent to those skilled in the relevant art(s) based on the teachings contained herein.
  • audio amplifiers e.g., audio buffer amplifiers, crystal oscillators, drivers, and power amplifiers
  • Microphone 402 of FIG. 4 is shown as a microphone 802.
  • the output of microphone 802 is a voice signal which is routed to an audio amplifier 804 and then to an audio buffer amplifier 806.
  • a crystal oscillator 808 is driven by the output of audio buffer amplifier 806 to create the FM signal 430.
  • a bias voltage 810 combines with FM signal 430 to create the FM control signal 432.
  • FM control signal 432 is routed to a UFT module
  • a filter 816 which creates rectangular signal 434. Also connected to UFT 812 is a bias signal 812. Rectangular signal 434 is filtered by a filter 816 to remove the unwanted harmonics and results in desired output signal 436. Desired output signal 436 goes to a driver 818 and then to a power amplifier 820. The output of power amplifier 820 is amplified output signal 438. Amplified output signal 438 is ready for transmission and is routed to an antenna 822.
  • the frequency of FM control signal 432 is a sub-harmonic of the frequency of desired output signal 436. It will be understood by those skilled in the relevant art(s) that the selection of the frequencies will have an impact on the amplitude of the desired output signal 436, and will be a determinative factor as to whether or not driver 418 and/or power amplifier 420 will be needed. Similarly, those skilled in the relevant art(s)will understand that the selection of microphone 402 will have an effect on analog voice signal 424, and will be a determinative factor as to whether or not audio amplifier 404 and/or audio buffer amplifier 406 will be needed. Additionally, those skilled in the relevant art(s) will understand that the specific design of UFT 412 will be a determinative factor as to whether or not bias voltage 410 is needed.
  • the present invention is directed toward an image reject mixer using a universal frequency translation (UFT) module.
  • the image reject mixer down-converts an input signal to an intermediate frequency signal, but rejects or attenuates the associated image frequency signal.
  • the present invention down- converts an input signal to a lower frequency with lower front-end attention, lower component count, lower cost, and lower overall power requirements when compared with conventional frequency mixers.
  • a conventional mixer 1206 generates an intermediate frequency (LF) signal 1210 at frequency (f IF ) using a local oscillator (LO) signal 1208 at frequency f L0 and at least one input signal.
  • FIGs. 12A-12B illustrate input signal 1202 at frequency (f,) and input signal 1204 at frequency (f 2 ) being down-converted to IF signal 1210 at f IF .
  • f is 901 MHz
  • f, is 899 MHz
  • f L0 is 900 MHz
  • both the input signal 1202 and input signal 1204 are down-converted to the desired f, F of 1MHz.
  • the IF signal 1210 contain a down-converted representation of only one of the first or second input signals.
  • the input signal that is desired to be down-converted is called the desired input signal, and the other input signal is called the undesired input signal.
  • the representation of the undesired signal in the IF signal be significantly attenuated compared with the desired signal. For example, if input signals 1202, 1204 represent independent voice messages, then the simultaneous down-conversion of both input signals 1202, 1204 to f 1F using a conventional mixer may result in neither message being clearly recovered.
  • the undesired input signal and it's down-converted representation are often referred to as an image signal.
  • the input signal 1204 may be referred to as the image signal of the desired input signal 1202.
  • f 2 is referred to the "image frequency", even when no signal is currently present at this frequency.
  • the input signal 1204 could be chosen as the desired input signal. In which case, input signal 1202 would be the image signal and f, would be the image frequency, as will be understood by those skilled in the arts based on the discussion herein.
  • FIG. 13A illustrates a block diagram of an image rejection mixer 1301 according to the present invention.
  • Image rejection mixer 1301 down-converts a desired input signal but significantly attenuates the down-conversion of the image input signal.
  • FIG. 13A illustrates an antenna 1304 and a the image reject mixer 1301.
  • Image rejection mixer 1301 comprises: input signal splitter 1308, path 1310, path 1324, and summer 1338.
  • Path 1310 comprises: UFT module 1314, and phase shifter 1318.
  • Path 1324 comprises: phase shifter 1328, UFT module 1326, and gain balance module 1327.
  • Antenna 1304 receives an input signal 1302.
  • Input signal 1302 may contain a desired input signal F D and an image signal F administrat as illustrated by F D 1344 and F, 1346 in FIG. 13B.
  • F D and F are separated by 2f IF , where f IF is the frequency of the IF signal 1342 generated by image reject mixer 1301.
  • the operation of image reject mixer 1301 is as follows.
  • Splitter 1308 receives input signal 1302 from antenna 1304.
  • Splitter 1308 splits the input signal 1302 into two signals that are routed to two paths, path 1310 and path 1324.
  • the splitter output signals are approximately equal amplitude and equal phase to each other.
  • splitter 1308 generates a desired signal F D1 and a image signal F shelter that exist at node 1312, and a desired signal F D2 and image signal F I2 that exist at node 1323.
  • Splitter 1334 receives a control signal F c 1348.
  • Splitter 1334 generates control signals F c , and F C2 at nodes 1332 and 1330, respectively.
  • Splitter 1334 is preferably equal amplitude and equal phase splitter; a variety of which are available as will be apparent to those skilled in the arts based on the discussion herein.
  • F C1 will be used by UFT module 1314 to down-convert F DI and F restroom
  • F C2 will be used by UFT module 1326 to down-convert F D2 and F I2 as will be described below.
  • path 1310 contains UFT module 1314 and phase shifter 1318.
  • UFT module 1314 accepts desired signal F D1 , image signal F recreational, and control signal F C1 .
  • UFT module 1314 down-converts the F D1 and F render to the lower intermediate frequency
  • the universal frequency translator down-converts an input signal.
  • the UFT may down-convert the input signal to an IF signal, or to a demodulated baseband signal.
  • the rate of a control signal determines whether the input signal is down-converted to an IF signal, or down-converted to a demodulated baseband signal.
  • Other down-conversion options are also possible using the UFT 118.
  • relationships between the input signal, the rate of the control signal, and the down-converted output signal are illustrated below:
  • path 1310 The operation of path 1310 will now be described in detail, after which path 1324 will be described. Finally, summer 1338 will be described.
  • Phase shifter 1318 receives the down-converted signals F D1 and F,,, and phase shifts F D , and F consume by approximately 90 degrees.
  • a variety of 90 degree phase shifters are readily available as will be apparent to those skilled the relevant arts.
  • Path 1324 comprises UFT module 1326, phase shifter 1328, and gain balance module 1327.
  • Phase shifter 1328 accepts control signal F C2 from splitter 1334.
  • UFT module 1326 accepts desired signal F D2 , image signal F I2 , and phase shifted control signal F C2 .
  • UFT module 1326 down-converts the F D2 and F, 2 to the lower intermediate frequency (f 1F ) using the phase shifted control signal from phase shifter 1328.
  • F D2 and F I2 are down-converted to a lower frequency, f IF .
  • Gain Balance module 1327 accepts the down-converted signals F D2 and F, 2 and adjusts the power level of F D2 and F, 2 such that the power of F D2 and F [2 at node 1337 is approximately equal to that of F D , and F procedura at node 1320. This improves the cancellation of F prison and F I2 by summer 1338.
  • gain balance module is an attenuator with an attenuation that is similar to the attenuation caused by phase shifter 1318.
  • gain balance module 1327 is an inverter amplifier that can be used change the selected signal that adds in-phase at summer 1338.
  • Summer 1338 receives down-converted signals F D , and Fmony from path 1310, and down-converted signals F D2 and
  • F I2 from path 1324.
  • Summer 1338 sums these four signal to generate F !F 1342. Because of the relative phase relationship of the four signals, F D1 and F D2 substantially add in-phase, and F recreational and F I2 substantially cancel. Therefore, F IF 1342 substantially comprises the desired signal F D , and the undesired image signal F, is substantially attenuated when compared with that of F D .
  • FIG. 13C lists the phase relationship for the above mentioned signals at various nodes in image reject mixer 1301 relative to the phase of F D , at node 1312. This is done for illustrative purposes only, as any phase reference could be chosen. ' At node 1312, F D , and F ⁇ are shifted by 0 degrees. Likewise at node 1323, F D2 and
  • F l2 are phase shifted by 0 degrees. This occurs because splitter 1308 is preferably an equal phase splitter that causes negligible phase shift.
  • down-converted F D and down-converted F linen are phase shifted by 0 degrees.
  • down-converted F D2 and down-converted F I2 are phase shifted by - 90 degrees, and +90 degrees, respectively. This occurs because the control signal F C2 is phase shifted by the amount of (90- M/N), where N is associated with the control signal F c as described above.
  • This phase shifted control signal operates UFT module 1326, which down-converts F D2 and F 12 and implements the described phase shift.
  • down-converted F D and down-converted F, are phase shifted by - 90 degrees, and -90 degrees respectively by phase shifter 1318.
  • down-converted F D2 and down-converted F I2 maintain the phase relationship of -90 degrees and +90 degrees.
  • summer 1338 combines down-converted F D , and down-converted F D2 in an additive manner because down-converted F D1 at node 1320 and down-converted F D2 at node 1337 have approximately the same relative phase shift of -90 degrees. Therefore,
  • F, F 1342 substantially contains the down-converted representation of the desired signal F D , only.
  • the level of signal rejection of the image signal F is theoretically infinite and only limited by component mismatches.
  • FIGs. 14A-14B illustrate a detailed schematic diagram that further describes one embodiment of image rejection mixer 1301.
  • Splitter 1401 is one embodiment of splitter
  • UFTs 1402 and 1404 are one embodiment of UFT 1314 and UFT 1326, respectively.
  • UFT 1402 comprises a CMOS chip 1403
  • UFT 1404 comprises a CMOS chip 1405.
  • Signals 1414 and 1416 connect FIGs. 14A and 14B for illustration purposes.
  • Signal 1420 comprises down-converted F D1 and down-converted F afford at node 1316 in FIG. 13 A
  • down-converted signal 1422 comprises down-converted
  • amplifier 1410 is included in path 1310, and amplifier 1412 is included in path 1324. Amplifiers 1410 and 1412 are optional to improve the signal strength and are not necessary to practice the present invention.
  • phase shifter 1318 comprises phase shifter 1414.
  • gain balance module 1327 comprises gain balance module 1416. 5. Multi-mode and Multi-band Receiver
  • An embodiment of the invention is directed to a receiver having multi-mode and multi-band functionality and capabilities.
  • the receiver is capable of selectively operating over a plurality of bands and channels.
  • the receiver operates in the following modes: (1) single band/channel mode; or (2) multiple band channel mode.
  • the receiver In the single band/channel mode, the receiver is configured to receive information in a particular channel of a particular frequency band.
  • the receiver may be dynamically reconfigured to listen to other channels and/or other bands.
  • the receiver is configured to receive information in one or more channels in one or more frequency bands.
  • the receiver could be configured to receive information from a plurality of channels of a single band, or one or more channels of a plurality of bands.
  • a channel in a band that is being monitored i.e., a channel in a band that the receiver is listening to
  • a channel/band combination i.e., a channel in a band that the receiver is listening to
  • the receiver preferably listens to each channel/band combination for a finite period of time. After the time period of a given channel/band combination expires, the receiver listens to another channel/band combination for a limited amount of time. In an embodiment, the receiver listens to the channel/band combinations in a round robin manner. The receiver listens to each channel/band combination for the same time duration. In other embodiments, the receiver listens to the channel/band combinations in other orders. For example, a user may specify the order in which the channel/band combinations are listened to by the receiver. The user may specify that some channel/band combinations are listened to more often than others. The user may specify that some channel/band combinations are listened to for durations different than the durations associated with other channel/band combinations.
  • the receiver 1904 is a component of a transceiver 1902.
  • the transceiver 1902 also includes a transmitter 1906.
  • the transceiver 1902 is an FRS unit that is enabled for multi- mode and multi-band operation, where the bands of operation include bands other than that associated with FRS. It is noted that this FRS embodiment is discussed herein for illustrative purposes only. The invention is not limited to this embodiment. As will be apparent to persons skilled in the relevant art(s) based on the discussion herein, the invention is applicable to other applications of receivers and transceivers.
  • the receiver is operable at a plurality of frequency bands.
  • the receiver is operable at least all U.S. frequency allocations from 10 KHz to 4
  • FIG. 28D illustrates the orientation of FIGS. 28A- 28C.
  • FIG. 28A partially overlaps with FIG. 28B, which partially overlaps with FIG. 28C.
  • this embodiment is described for illustrative purposes. The invention is not limited to these bands. As will be appreciated by persons skilled in the relevant art(s) based on the discussion herein, embodiments of the invention are applicable at other frequency ranges.
  • FIG. 15 is a block diagram of a receiver 1502 according to an embodiment of the invention.
  • the receiver 1502 includes one or more input filters and/or Z match modules 1506, an input selector 1516, a universal frequency translator 1518, an output selector
  • the input filters and/or Z match (impedance match) modules 1506 include filter and/or Z match modules 1508, 1510, 1512, 1514 (four such modules are shown in FIG. 15, but the invention is not limited to this embodiment).
  • Each input filter and/or Z match module 1508, 1510, 1512, 1514 operates to select or pass a frequency band. Accordingly, each input filter and/or Z match module 1508, 1510, 1512, 1514 operates as a band select filter.
  • each input filter and/or Z match module 1508, 1510, 1512, 1514 is configured to pass a frequency band of interest.
  • each input filter and/or Z match module 1508, 1510, 1512, 1514 also operates to impedance match the input to downstream circuitry.
  • filters and Z match modules operable for use with the present invention will be apparent to persons skilled in the relevant art(s) based on the discussion herein. Filters are also described herein in the sections entitled "Down-conversion Using a Universal Frequency
  • the receiver 1502 includes a single filter and/or Z match module that is adjustable over a plurality of frequency bands. In another embodiment, the receiver 1502 includes a plurality of filters and/or Z match modules that are adjustable over a plurality of frequency bands. Reference is made to the section included herein entitled “Unified Down-conversion and Filtering.”
  • the input selector 1516 operates to select one of a plurality of input signals. The selected input signal is passed to an output.
  • the input selector 1516 includes a switchl 17.
  • the switch 1517 includes a plurality of input nodes and an output node. The switch 1517 connects one of the input nodes to the output node.
  • the universal frequency translator (UFT) 1518 down-converts an input signal 1519.
  • the UFT 1518 may down-convert the input signal 1519 to an IF signal, or to a demodulated baseband signal.
  • the rate of a control signal 1550 determines whether the input signal 1519 is down-converted to an IF signal, or down- converted to a demodulated baseband signal.
  • Other down-conversion options are also possible using the UFT 1518.
  • relationships between the input signal 1519, the rate of the control signal 1550, and the down-converted output signal 1521 are illustrated below:
  • the UFT 1518 is further described herein in the section entitled “Down-conversion Using a Universal Frequency Translation Module.”
  • the control signal generator 1542 generates a control signal 1550.
  • the frequency of the control signal 1550 is adjustable.
  • the control signal generator 1542 includes a voltage controlled oscillator (VCO). VCO and other types of devices operable for performing the functionality of the control signal generator 1542 will be apparent to persons skilled in the relevant art(s) based on the discussion herein.
  • the control signal generator 1542 may include circuitry to modify characteristics of the control signal 1550, such as adjusting the pulse widths of the control signal 1550. Such aspects are described herein in the section entitled “Down-conversion Using a Universal Frequency Translation Module.”
  • the output selector 1520 operates to route an input signal to one of a plurality of output nodes.
  • the output selector 1520 includes a switchl23.
  • the switch 1523 includes an input node and a plurality of output nodes.
  • the switch 1523 connects one of the output nodes to the input node.
  • the output filters 1522 include filters 1524, 1526, 1528, 1530 (four such modules are shown in FIG. 15, but the invention is not limited to this embodiment).
  • Each filter 1524, 1526, 1528, 1530 operates to select or pass a frequency channel. Accordingly, each filter 1524, 1526, 1528, 1530 operates as a channel select filter.
  • each filter 1524, 1526, 1528, 1530 is configured to pass a frequency channel of interest.
  • filters operable for use with the present invention will be apparent to persons skilled in the relevant art(s) based on the discussion herein. Filters are also described herein in the section entitled "Unified Down-conversion and Filtering.”
  • the receiver 1502 includes a single output filter that is adjustable over a plurality of frequency bands. In another embodiment, the receiver 1502 includes a single output filter that is adjustable over a plurality of frequency bands. In another embodiment, the receiver
  • 1502 includes a plurality of output filters modules that are adjustable over a plurality of frequency bands. Reference is made, for example, to the section included herein entitled “Unified Down-conversion and Filtering.”
  • the receiver 1502 includes decoders 1532.
  • Decoders 1532 preferably include a plurality of decoders 1534, 1536, 1538, 1540 (four such devices are shown in FIG. 15, but the invention is not limited to this example). Decoders 1534, 1536,
  • the decoders 1534, 1536, 1538, 1540 decode an input signal to obtain an output signal 1548.
  • the decoders 1534, 1536, 1538, 1540 are preferably configured to operate with signals of interest.
  • a variety of decoders operable for use with the present invention will be apparent to persons skilled in the relevant art(s) based on the discussion herein.
  • the operation of many if not all of the components of the receiver 1502 is adjustable. Such adjustability is discussed above, and further discussed below.
  • a controller 1544 issues commands to the components of the receiver 1502. Such commands control the operation of such components.
  • the controller 1544 is implemented using a microprocessor and/or a digital signal processor (DSP).
  • DSP digital signal processor
  • the controller 1544 may receive instructions and/or data from users 1546.
  • the receiver 1502 receives input signals 1504 over some communication medium.
  • the communication medium may be any communication medium, including but not limited to a wireless medium or a wired medium, or a combination thereof.
  • the input signals 1504 may include information present in a plurality of channels of a plurality of frequency bands.
  • the input signals 1504 may include, without limitation, information present in one or more AM channels, one or more FM channels, one or more CB channels, one or more TV channels, one or more FRS channels, one or more Weatherband channels, local area networks, etc..
  • the input signals 1504 are received by the input filters and/or Z match modules
  • Each of the input filters and/or Z match modules 1508, 1510, 1512, 1514 are configured to pass a frequency band of interest.
  • the input filter and/or Z match module 1508 may be configured to pass the AM band.
  • the input filter and/or Z match module 1510 may be configured to pass a band of frequencies associated with a local area network (LAN).
  • the input filter and/or Z match module 1512 may be configured to pass the FRS band.
  • the input filter and/or Z match module 1514 may be configured to pass the Weather band.
  • the input filters and/or Z match modules 1508, 1510, 1512, 1514 pass those input signals 1504 that fall within their respective bands.
  • the filter and/or Z match modules 1508, 1510, 1512, 1514 generate filtered signals. These filtered signals are received by the input selector 1516. At any instance of time, the input selector 1516 routes one of these filtered signals to the universal frequency translator (UFT) 1518. Switching and routing by the input selector 1516 is controlled by the controller 1544.
  • the filtered signal that is routed to the UFT 1518 corresponds to a channel/band combination that is currently being processed or monitored (this channel/band combination is referred to as the "current channel/band").
  • the UFT 1518 down-converts the filtered signal that it receives from the input selector 1516 to a lower frequency suitable for down-stream processing.
  • the operation of the UFT 1518 is controlled by the controller 1544. For example, the controller 1544 establishes the frequency of the control signal 1550 generated by the control signal generator 1542, which controls the down-conversion operation performed by the UFT 1518.
  • the output selector 1520 routes the down-converted signal to an output filter 1522 associated with the current channel/band. Switching and routing performed by the output selector 1520 is controlled by the controller 1544. Assume, for example purposes, that the filter 1526 is associated with the current channel/band. In this case, the output selector 1520 routes the down-converted signal to the filter 1526.
  • the filter 1526 is configured to pass a channel within the band of the "current channel/band.”
  • the channel filtered signal is passed to the decoder 1536 coupled to the filter 1526.
  • the decoder 1536 decodes the channel filtered signal to obtain the output signal 1548.
  • the output signal 1548 is thereafter processed in an application dependent manner.
  • FIG. 16 illustrates a receiver 1602 according to an alternative embodiment of the invention.
  • the receiver 1602 includes a unified down-converting and filtering (UDF) module 1606.
  • UDF down-converting and filtering
  • the UDF module 1606 performs frequency selectivity and frequency translation as a single unified (i.e., integrated) operation. By performing frequency selectivity and translation as a single unified operation, the invention achieves high frequency selectivity prior to frequency translation.
  • the invention achieves high frequency selectivity at any input frequency (the input frequency refers to the frequency of the input spectrum being filtered and translated), including but not limited to RF (radio frequency) and greater frequencies. It should be understood that the invention is not limited to this example of RF and greater frequencies. The invention is intended, adapted, and capable of working with lower than radio frequencies.
  • the effect achieved by the UDF module 1606 is to perform the frequency selectivity operation prior to the performance of the frequency translation operation.
  • the UDF module 1606 effectively performs input filtering.
  • such input filtering involves a relatively narrow bandwidth.
  • such input filtering represents channel select filtering, where the filter bandwidth may be, for example and without limitation, 50 KHz to 150 KHz. It should be understood, however, that the invention is not limited to these frequencies. The invention is intended, adapted, and capable of achieving filter bandwidths of less than and greater than these values.
  • the UDF module 1606 of the present invention includes a number of advantages.
  • the UDF module 1606 can be designed with a filter center frequency f c on the order of 900 MHz, and a filter bandwidth on the order of 50 KHz. This represents a Q of 18,000, as indicated by the equation
  • the filtering center frequency f c and other filtering characteristics of the UDF module 1606 can be electrically adjusted, either statically or dynamically.
  • the frequency translation characteristics of the UDF module 1606 can be electrically adjusted, either statically or dynamically.
  • the UDF module 1606 can be designed to amplify input signals. Further, the UDF module 1606 can be implemented without large resistors, capacitors, or inductors. Also, the UDF module 1606 does not require that high tolerances be maintained on its individual components, i.e., its resistors, capacitors, inductors, etc. As a result, the architecture of the UDF module 1606 is friendly to integrated circuit design techniques and processes.
  • the UDF module 1606 operationally replaces the band select filtering, frequency translation, and channel select filtering operations performed by the input filters and/or Z match modules 1506, the UFT 1518, and the output filters 1522 of the receiver 1502 of FIG. 15.
  • the output of the UDF module 1606 is a channel filtered and down-converted signal corresponding to the current channel/band.
  • the filtering and down-conversion characteristics of the UDF module 1606 are adjusted pursuant to the current channel/band (so as to appropriately process the current channel/band) based on commands issued by the controller 1612 to the UDF 1606 and the control signal generator 1610.
  • the receiver 1602 may include an output selector (not shown), similar to that described with respect to FIG. 15, to route the channel filtered and down-converted signal to one of the decoders 1616 associated with the current channel/band.
  • the decoders 1616 may represent an adjustable decoder whose operation is controlled by the controller 1612. The decoder then decodes the channel filtered and down-converted signal to produce the output signal 1618. The output signal 1618 is thereafter processed in an application dependent manner.
  • the UDF module is described in further detail in the section included herein entitled "Unified Down-conversion and Filtering.”
  • the operation of the receiver 1904 is further described below.
  • the receiver 1904 may represent either the receiver 1502 of FIG. 15, or the receiver 1602 of FIG. 16.
  • Other embodiments of the receiver 1904 will be apparent to persons skilled in the relevant art(s) based on the discussion herein.
  • the receiver 1904 is considered to be a component of a transceiver 1902.
  • the transceiver 1902 also includes a transmitter 1906.
  • the transceiver 1902 is an FRS unit enabled for multi-mode and multi-band operation, although the invention is not limited to this embodiment.
  • a user 2004 has the FRS unit 1902, which is coupled to a computer 2018 via a wireless or wired connection (alternatively, the computer 2018 may be integrated with the FRS unit 1902).
  • the user 2004 is using the FRS unit 1902 to communicate with user 2006 (FCC rules permitting), who may be a family member.
  • User 2006 includes a second FRS unit 2007, and communicates with user 2004 via FRS channel 2024.
  • the user 2004 also wishes to communicate with user 2020 (FCC rules permitting), who may be another family member.
  • the user 2020 includes a third FRS unit 2022, and communicates with user 2004 via FRS channel 2026.
  • the user 2004 also wishes to receive an FM channel 2030 from FM station 2008, an FM channel 2032 from FM station 2010, a weather channel 2034 from weather station 2012, a TV channel 2036 from TV station 2014, and network communication 2038 from a local area network (LAN) 2016.
  • LAN local area network
  • Such network communication 2038 may be routed to and processed by computer 2018.
  • the invention enables the user 2004 to receive all of these signals (and others) using the FRS unit 1902.
  • the filter and/or Z match modules 1508 and 1510 may be configured for the FM band.
  • the filters 1524 and 1526 may be configured for FM channels 2030 and 2032, respectively.
  • decoders 1534 and 1536 may be configured for FM channels 2030 and 2032, respectively.
  • the filter and/or Z match module 1512 may be configured for the weather band, and filter 1528 and decoder 1538 may be configured for the weather channel 2034.
  • the filter and/or Z match module 1514 may be configured for an appropriate TV band, and the filter 1530 and decoder 1540 may be configured for TV channel 2036.
  • Other filter and/or Z match modules 1506, output filters 1522, and decoders 1532 may be similarly configured for network communication 2038, FRS channel 2026, and FRS channel 2024.
  • the user 2004 can enter an appropriate command(s) into the FRS unit 1902 to cause the FRS unit 1902 to enable and/or adjust the components contained therein for operation with the FM channel 2030.
  • the input selector 1516 will switch to connect the filter and or Z match module 1508 to the UFT 1518.
  • the output selector 1520 will switch to connect the UFT 1518 to the filter 1524.
  • the control signal generator 1542 will generate a control signal 1550 having a frequency appropriate for down-converting the FM channel 2030.
  • the user 2004 may issue such commands by, for example, pressing keys on a keypad of the FRS unit 1902. Other means for issuing commands are envisioned, such as voice activation.
  • the user 2004 can easily switch to any of the other sources of information of interest. For example, if the user 2004 wishes to receive the TV channel 2036, the user 2004 can enter an appropriate command into the FRS unit 1902 to cause the FRS unit
  • the input selector 1516 will switch to connect the filter and/or Z match module 1514 to the UFT 1518.
  • the output selector 1520 will switch to connect the UFT 1518 to the filter 1530.
  • the control signal generator 1542 will generate a control signal 1550 having a frequency appropriate for down-converting the TV channel
  • the user 2004 may issue such commands by, for example, pressing keys on a keypad of the FRS unit 1902.
  • Other means for issuing commands are envisioned, such as voice activation.
  • the receiver 1502 (or 1602) has a scan mode.
  • the controller 1544 automatically scans among the programmed channel/band combinations. Specifically, the components within the FRS unit 1902 are adjusted for operation with a channel/band combination. After some time period, which may be pre-programmed, user programmed, dynamically programmed, random, fixed, etc., the components within the FRS unit 1902 are adjusted for operation with a different channel/band combination. Such scanning operation continues until receipt of some command. It is noted that the scanning mode is not limited to programmed channel/band combinations. The receiver 1502 can be instructed to scan throughout the frequency spectrum in any order and/or increment.
  • the receiver can be instructed to recognize and act upon particular content.
  • the receiver can be instructed to listen and recognize particular content while monitoring a weather band.
  • Such content may be a storm warning, for example.
  • the receiver can be instructed to act in predefined ways upon receipt and recognition of such content. For example, while monitoring a weather band, if a storm warning is received, then the receiver may be programmed to issue an audible alarm and/or to switch to the weather band until further user command to enable the user to receive weather updates.
  • Channel/band combinations can be programmed in the receiver 1502.
  • the FM channel 2030 is programmed in the receiver 1502 by adjusting or otherwise establishing the filter and/or Z match 1508 for operation in the FM band, by adjusting or otherwise establishing the filter 1524 and the decoder 1534 for operation with the FM channel 2030, programming the controller 1544 with information sufficient for generating a control signal 1550 (using the control signal generator 1542) having a frequency suitable for down-converting the FM channel 2030, and also programming the controller 1544 with information to control the input selector 1516 and the output selector
  • Channel/band combinations can be pre-programmed, user programmed, downloaded from an information source such as the Internet or a computer, or via any well known programming means.
  • an information source such as the Internet or a computer, or via any well known programming means.
  • the operation of the FRS unit 1902 is further described below.
  • the invention supports a variety of modes, as indicated above. Additional modes of operation will be apparent to persons skilled in the relevant art(s) based on the discussion herein.
  • One of the modes supported by the invention is a single band/channel mode. In this mode, the receiver is configured to receive information in a particular channel of a particular frequency band. The receiver may be dynamically reconfigured to listen to other channels and/or other bands.
  • FIG. 17 illustrates a flowchart 1702 that depicts in greater detail the operation of the receiver when in the single band/channel mode. It is noted that the ordering of the steps shown in FIG. 17 is not mandatory. Other orderings of the steps of FIG. 17 are possible and within the scope and spirit of the present invention. Such other orderings will be apparent to persons skilled in the relevant art(s) based on the discussion herein.
  • a band is selected.
  • a channel within the selected band is selected.
  • the selected channel/band combination represents the channel and band that are to be monitored/received by the receiver.
  • the band and channel can be selected in steps 1704 and 1706 using any of the procedures discussed above, such as having a user enter an appropriate command, during the scan function, due to an interrupt or time-based command, etc..
  • step 1708 with respect to the embodiment of FIG. 15, the controller 1544 selects the input filter and/or Z match module 1506, the output filter 1522, and the decoder 1532 that are configured for operation with the selected channel/band.
  • the controller 1612 instructs/adjusts the UDF 1606 and selects the decoder 1616 for appropriate operation with the selected channel/band.
  • step 1710 the controller 1544/1612 causes the control signal generator 1542/1610 to generate a control signal 1550/1608 having a frequency suitable for down- converting the selected channel/band. Steps 1704- 1710 may be repeated for another channel/band.
  • the receiver also supports a multiple band/channel mode.
  • the receiver in the multiple band/channel mode, is configured to receive information in one or more channels in one or more frequency bands.
  • the receiver could be configured to receive information in a plurality of channels of a single band, or one or more channels of a plurality of bands.
  • a channel in a band that is being monitored i.e., a channel in a band that the receiver is listening to
  • the receiver preferably listens to each channel/band combination for a finite period of time. After the time period of a given channel/band combination expires, the receiver listens to another channel/band combination for a limited amount of time.
  • the receiver listens to the channel/band combinations in a round robin manner.
  • the receiver listens to each channel/band combination for the same time duration.
  • the receiver listens to the channel/band combinations in other orders. For example, a user may specify the order in which the channel/band combinations are listened to by the receiver. The user may specify that some channel/band combinations are listened to more often than others. The user may specify that some channel/band combinations are listened to for durations different than the durations associated with other channel/band combinations.
  • FIG. 18 illustrates a flowchart which depicts in greater detail the operation of the receiver when operating in the multiple band/channel mode.
  • step 1804 one or more bands are selected.
  • step 1806 for each of the selected bands, one or more channels are selected.
  • the selected channel/band combinations represent the channels and bands that are to be monitored/received by the receiver.
  • the bands and channels can be selected in steps 1804 and 1806 using any of the procedures discussed above, such as having a user enter appropriate commands, during the scan function, due to an interrupt or time-based command, etc..
  • the receiver is instructed to search over the entire frequency spectrum, or a specified portion of the spectrum. In this case, the channel/band combinations represent frequencies in the specified portion of the spectrum.
  • step 1808 one of the channel/band combinations is selected for monitoring.
  • the controller 1544 selects the input filter and/or Z match module 1506, the output filter 1522, and the decoder
  • the controller 1612 instructs/adjusts the UDF 1606 and selects the decoder 1616 for appropriate operation with the selected channel/band combination.
  • step 1812 the controller 1544/1612 causes the control signal generator 1542/1610 to generate a control signal 1550/1608 having a frequency suitable for down- converting the selected channel/band combination.
  • step 1814 the selected channel/band combination is monitored.
  • step 1816 the controller 1544/1612 determines whether a time duration associated with the selected channel/band combination has expired.
  • the time duration may differ for different channel/band combinations, or may be the same for all. If the time duration has not expired, then the receiver continues to monitor the selected channel/band combination. This is represented by the return to step 1814. If the time duration has expired, then another channel/band combination is selected. This is represented by the return to step 1808.
  • Another embodiment of the present invention is directed toward a multi-mode, multi-band communication system that can transmit and/or receive one or more information signals on one or more transmission frequencies using one or more modulation schemes.
  • the invention described herein is directed to the transmission subsystem of the communications system.
  • the up-conversion section is implemented using a universal frequency translator (UFT).
  • UFT universal frequency translator
  • the transmission subsystem is hereafter referred to as the subsystem, and those skilled in the relevant art(s) will appreciate that the subsystem can be integrated with receiver subsystems, such as, and without limitation, the receiver subsystem described herein in the section entitled "Multi-mode and Multi-band Receiver.”
  • the block diagram of FIG. 21 illustrates an embodiment of the present invention.
  • the subsystem is comprised of an information signal conditioning module 2102, a signal selection module 2104, a modulation and frequency selection module 2106, a universal frequency translator (UFT) module 2108, a bias/reference module 2110, a frequency band selection module 2112, an optional output conditioning module 2114, and a control module 2116.
  • the description provided below is for an implementation of the embodiment wherein a single signal is up-converted and transmitted at any time.
  • Those skilled in the relevant art(s) will understand, based on the teachings contained herein, that more than one information signal can be modulated, up-converted, and transmitted simultaneously and be within the spirit and scope of the invention. Looking to the structural diagram of FIG.
  • one or more information signals 2120 are received by information signal conditioning module 2102 and one or more conditioned information signals 2122 are output.
  • the one or more conditioned information signals 2122 are routed to signal selection module 2104.
  • Signal selection module 2104 determines which of the one or more information signals 2120 are to be transmitted at any time. In other words, signal selection module 2104 selects one of the information signals 2120 for transmission.
  • Selected information signal 2124 is output from signal selection module 2104 and routed to modulation and frequency selection module 2106.
  • the purpose of modulation and frequency selection module 2106 is to ensure that the desired modulation scheme and desired output frequency are achieved. Modulation and frequency selection module 2106 outputs an oscillating signal
  • UFT module 2108 receives oscillating signal 2126 and a bias/reference signal 2128 from bias/reference signal module 2110.
  • the output of UFT module 2108 is a substantially rectangular signal 2130 comprised of a plurality of harmonics. Rectangular signal 2130 is routed to frequency band selection module 2112 which outputs one or more desired output signals 2132 (each of which correspond to one of the harmonics of rectangular signal 2130), which are then routed to optional output conditioning module 2114.
  • An output signal 2134 is generated by optional output conditioning module 2114 and is routed to appropriate transmission devices, such as one or more antennas (not shown).
  • control module 2116 which outputs a format control signal 2136, a buffer control signal 2138, a signal selection control signal 2140, a modulation control signal 2142, a frequency control signal 2144, a band selection control signal 2146, and a filter control signal 2148.
  • control module 2116 which outputs a format control signal 2136, a buffer control signal 2138, a signal selection control signal 2140, a modulation control signal 2142, a frequency control signal 2144, a band selection control signal 2146, and a filter control signal 2148.
  • information signals 2120 are received by information signal conditioning module 2102.
  • information signal conditioning module 2102 receives format control signal 2136 and buffer control signal 2138.
  • a format module 2202a receives an information signal 2120a, and, based on instructions contained in format control signal 2136, converts information signal 2120a from digital to analog, from analog to digital, or allows it to pass unchanged. If this signal is digital, it may be passed to a buffer memory 2204a which also receives buffer control signal 2138. Based on buffer control signal 2138, digital information signal 2120a is either passed directly out of information signal conditioning module 2102 as a conditioned information signal 2122a, or it is temporarily stored in buffer memory 2204a.
  • a condition under which a digital information signal 2120a might be stored in buffer memory 2204a is when another information signal (e.g., information signal 2120b) is being modulated, up- converted, and transmitted. In this manner, multiple information signals can be transmitted sequentially with minimal loss of information. If the signal is analog, it will pass directly out of information signal conditioning module 2102 as conditioned information signal 2122a.
  • another information signal e.g., information signal 2120b
  • Signal selection module 2104 receives conditioned information signals 2122 and signal selection control signal 2140. Based on the control given, signal selection module
  • signal selection module 2104 selects which conditioned information signal 2122 is to be output as selected information signal 2124.
  • the operation of signal selection module 2104 underscores the highly integrated nature of control module 2116. As an example, signal selection module 2104 should not select a conditioned information signal 2122 that is being stored in buffer memory 2204, until that signal is ready to be transferred.
  • information signal conditioning module 2102 are not required elements in the invention. For example, if information signals 2120 are all in the proper format (i.e., no A-to-D or D- to-A conversion is required), and there is no requirement for them to be buffered (e.g., they are all analog), signal selection module 2104 will receive information signals 2120 directly. Similarly, depending on system requirements, format modules 2202 may be eliminated while retaining buffer memories 2204 (i.e., the signals are already in a desired digital format), or buffer memories 2204 may be eliminated while retaining format modules 2202. Both the inclusion or elimination of any of the functions performed by the information signal conditioning module 2102 is within the spirit and scope of the invention. FIG.
  • Modulation and frequency selection module 2106 is preferably comprised of a modulation selector 2306, an oscillating signal generator 2308, and a frequency selector 2330.
  • Bias/reference signal module 2110 is preferably comprised of a summer 2310 and an impedance 2312. Selected information signal 2124 is received by modulation selector 2306. The operation of modulation selector 2306 is controlled by modulation control signal 2142. The purpose of modulation selector 2306 is to effect the proper modulation of selected information signal 2124.
  • a switch 2314 is coupled to a contact 2318 when amplitude modulation (AM) is desired, to a contact 2320 when phase modulation (PM) is desired, and to a contact 2322 when frequency modulation (FM) is desired.
  • AM amplitude modulation
  • PM phase modulation
  • FM frequency modulation
  • I Q In- phase/Quadrature-phase
  • QAM quadrature amplitude modulation
  • AM on angle modulation i.e., FM or PM
  • switch 2314 When AM is desired, switch 2314 is coupled to contact 2318, and selected information signal 2124 is routed to bias/reference signal module 2110 where it is summed with a bias signal 2338 by summer 2310. To avoid bias/reference signall28 being shorted directly to ground, impedance 2312 is placed in series between the source of bias/reference signal 2128 and UFT module 2108.
  • switch 2314 When PM is desired, switch 2314 is coupled to contact 2320, and selected information signal 2124 is routed to oscillating signal generator 2308. Selected information signal 2124 is then coupled to a phase modulator 2326. Similarly, when FM is desired, switch 2314 is coupled to contact 2322, and selected information signal 2124 is routed to oscillating signal generator 2308 where it is coupled to a frequency modulator 2328.
  • the operation of frequency selector 2330 is controlled by frequency control signal 2144. Frequency selector 2330 controls the operation of frequency modulator 2328, phase modulator 2326, and an oscillator 2324 such that the frequency of oscillating signal 2126 is a desired sub-harmonic of the frequency of desired output signal 2134.
  • Oscillating signal generator 2308 also includes a switch 2316 that is ganged together with switch 2314 such that when switch 2314 is coupled to contact 2318 (for AM), switch 2316 is coupled to contact 2332.
  • oscillating signal 2126 is an unmodulated oscillating signal having a frequency that is a sub-harmonic of the frequency of the desired output signal 2134
  • bias/reference signal 2128 is a function of selected information signal 2124.
  • oscillating signal 2126 is the output of phase modulator 2326 and is a phase modulated oscillating signal having a frequency that is a sub-harmonic of the frequency of the desired output signal 2134.
  • bias/reference signal 2128 is comprised of bias signal 2338.
  • oscillating signal 2126 is the output of frequency modulator 2326 and is a frequency modulated oscillating signal having a frequency that is a sub-harmonic of the frequency of the desired output signal 2134.
  • bias/reference signal 2128 is comprised of bias signal 2338.
  • modulation and frequency selection module 2106 and bias/reference signal module 2110 can be designed without the unneeded circuits.
  • modulation and frequency selection module 2106 and bias/reference signal module 2110 can be designed without the unneeded circuits.
  • modulation selector 2306, summer 2310, oscillator 2324, phase modulator 2326, switch 2316, and contacts 2332, 2334, 2336, as well as modulation control signal 2142 can be eliminated.
  • selected information signal 2124 is routed directly to frequency modulator 2328, the output of which is oscillating signal 2126. Note that frequency modulator 2328 is still controlled by frequency control signal 2144.
  • UFT module 2108 is preferably comprised of a square wave generator 2402, a pulse shaper 2404, and a switch 2406. The use of UFT module 2108 as a transmitter is further described herein in the section entitled "Frequency Up-conversion.”
  • FIG. 24 illustrates oscillating signal 2126 being accepted by square wave generator 2402 to create a square wave 2408 from the periodic waveform of oscillating signal 2126.
  • Square wave generators useful for operation with the invention are well known.
  • Square wave 2408 has substantially the same frequency and modulation (if any) as does oscillating signal 2126.
  • Square wave 2408 is then routed to pulse shaper 2404 to create a string of pulses 2410.
  • string of pulses 2410 has substantially the same frequency and modulation (if any) as does oscillating signal 2126.
  • pulse shaper 2404 is a mono-stable multi-vibrator.
  • the frequency of string of pulses 2410 is not the same as the frequency of oscillating signal 2126.
  • the string of pulses 2410 controls switch 2406 to create rectangular signal 2130.
  • pulse shaper 2404 is designed such that each pulse in string of pulses 2410 has a pulse width " ⁇ " that is substantially equal to (n/2)»T, where "T” is the period of desired output signal 2134, and "n” is any odd number.
  • bias/reference signal 2128 Another input to UFT module 2108 is bias/reference signal 2128, which, in this embodiment, is connected to the opposite terminal of switch 2406 from rectangular signal
  • bias/reference signal 2128 is gated to a second potential (e.g., ground, not shown), thereby creating rectangular signal 2130.
  • switch 2406 is a field effect transistor (FET).
  • FET field effect transistor
  • FIG 25 A specific implementation wherein the FET is a complementary metal oxide semiconductor (CMOS) FET is shown in FIG 25.
  • CMOS FET has three terminals: a gate 2502, a source 2504, and a drain 2506.
  • String of pulses 2410 is connected to gate 2502
  • bias/reference signal 2128 is connected to source 2504, and rectangular signal 2130 is connected to drain 2506.
  • the output of UFT module 2108 is rectangular signal 2130 that contains a plurality of harmonics.
  • Rectangular signal 2130 is sometimes referred to as a harmonically rich signal. Rectangular signal 2130 is accepted by frequency band selection module 2112 which filters out any undesired harmonic frequencies and outputs desired output signals 2132 which are the harmonics of rectangular signal 2130 that were not filtered out by frequency band selection module 2112. Desired output signals 2132 are modulated signals at the desired output frequency.
  • frequency band selection module 2112 An exemplary structure for frequency band selection module 2112 is shown in FIG. 26. Rectangular signal 2130 is received by frequency band selection module 2112. To accommodate the wide range of possible output frequencies for output signal 2134 (for example, and not meant to be limiting, output signal 2134 may have frequencies ranging from 10 KHz to 3.5 GHz), a frequency band selector 2606 and a parallel network of filter circuits 2618 are shown. It will be apparent to those skilled in the relevant art(s), based on the teachings contained herein, that it would be within the spirit and scope of the invention if the desired output frequency range were to be accommodated by a single filter circuit. In the implementation shown here, frequency band selection module 2112 is comprised of a frequency band selector 2606 and one or more filter circuits 2618.
  • Frequency band selector 2606 is further comprised of a switch 2608 and one or more contacts 2610.
  • the purpose of frequency band selection module 2112 is to accommodate the wide range of possible output frequencies for output signal 2134.
  • Those skilled in the relevant art(s) will understand, based on the teachings contained herein, that the exact number of filter circuits 2618 will depend, mter alia, on the actual desired frequency range of output signal 2134 and the components and design of each filter.
  • frequency band selector 2606 being controlled by band selection control signal 2146, will, for example, be coupled to contact 2610a for desired output frequencies between 10 KHz and 100 KHz (referred to herein as "Band 1"), coupled to contact 2610b for desired output frequencies between 100 KHz and 10 MHz (referred to herein as “Band 2"), coupled to contact 2610c for desired output frequencies between 10 MHz and 500 MHz (referred to herein as “Band 3”), and coupled to contact 2610m for desired output frequencies above 1 GHz (referred to herein as "Band m").
  • Band 1 desired output frequencies between 10 KHz and 100 KHz
  • Band 2 coupled to contact 2610b for desired output frequencies between 100 KHz and 10 MHz
  • Band 3 coupled to contact 2610c for desired output frequencies between 10 MHz and 500 MHz
  • Band m coupled to contact 2610m for desired output frequencies above 1 GHz
  • Filter circuits 2618 are controlled by filter control signal 2148 to specifically tune each filter for the specific output frequency.
  • the desired output frequency is 467.6125 MHz (i.e., channel 10 of the Family Radio Service)
  • switch 2608 would couple with contact 2610c, and filter circuit 2618c would respond to filter control signal 2148 to tune its components to band pass only the desired frequency.
  • filter control signal 2148 to tune its components to band pass only the desired frequency.
  • the outputs of filter circuits 2618 are desired output signals 2132. Desired output signals 2132 are then routed to optional output conditioning module 2114, an embodiment of which is shown in FIG. 27.
  • Optional output condition module 2114 is preferably comprised of one or more drivers 2702 and one or more power amplifiers 2704.
  • the requirement for drivers 2702 and/or power amplifiers 2704 is dependent on a number of factors.
  • the frequency of oscillating signal 2126 is a sub- harmonic of the frequency of desired output signal 2132. It will be understood by those skilled in the relevant art(s) that the selection of the frequencies will have an impact on the amplitude of the desired output signal 2132, and will be a determinative factor as to whether or not drivers 2702 and/or power amplifiers 2704 will be needed. A more thorough discussion of this is described herein in the section entitled "Frequency Up- conversion.”
  • Output signal 2134 is then routed to appropriate transmission devices, such as one or more antennas (not shown). 7. Down-conversion Using a Universal Frequency Translation Module.
  • An aliasing module for down-conversion uses a universal frequency translation (UFT) module which down-converts an EM input signal
  • the aliasing module includes a switch and a capacitor
  • the electronic alignment of the circuit components is flexible. That is, in one implementation, the switch is in series with the input signal and the capacitor is shunted to ground (although it may be other than ground in configurations such as differential mode). In a second implementation, the capacitor is in series with the input signal and the switch is shunted to ground (although it may be other than ground in configurations such as differential mode).
  • the aliasing module with the UFT module can be easily tailored to down-convert a wide variety of electromagnetic signals using aliasing frequencies that are well below the frequencies of the EM input signal.
  • the aliasing module down-converts the input signal to an intermediate frequency (IF) signal.
  • the aliasing module down- converts the input signal to a demodulated baseband signal.
  • the input signal is a frequency modulated (FM) signal, and the aliasing module down-converts it to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal.
  • FM frequency modulated
  • AM amplitude modulated
  • control signal includes a train of pulses that repeat at an aliasing rate that is equal to, or less than, twice the frequency of the input signal
  • control signal is referred to herein as an aliasing signal because it is below the Nyquist rate for the frequency of the input signal.
  • the frequency of control signal is much less than the input signal 6404.
  • the train of pulses controls the switch to alias the input signal with the control signal to generate a down-converted output signal. More specifically, in an embodiment, the switch closes on a first edge of each pulse and opens on a second edge of each pulse. When the switch is closed, the input signal is coupled to the capacitor, and charge is transferred from the input signal to the capacitor. The charge stored during successive pulses forms down-converted output signal.
  • the pulse aperture may also be referred to as the pulse width as will be understood by those skilled in the art(s).
  • the pulses repeat at an aliasing rate, or pulse repetition rate of the aliasing signal. The aliasing rate is determined as described below.
  • the train of pulses control the switch to alias the analog AM carrier signal (i.e., the input signal) at the aliasing rate of the aliasing signal.
  • the switch closes on a first edge of each pulse and opens on a second edge of each pulse.
  • the input signal is coupled to the capacitor, and charge is transferred from the input signal to the capacitor.
  • the charge transferred during a pulse is referred to herein as an under-sample.
  • Exemplary under-samples form the down-converted signal portion that co ⁇ esponds to the analog AM carrier signal portion and the train of pulses.
  • the charge stored during successive under- samples of the AM carrier signal form the down-converted signal that is an example of the down-converted output signal.
  • the aliasing rate of the control signal determines whether the input signal is down- converted to an IF signal, down-converted to a demodulated baseband signal, or down- converted from an FM signal to a PM or an AM signal.
  • relationships between the input signal, the aliasing rate of the control signal, and the down-converted output signal are illustrated below:
  • the input signal is down- converted to an IF signal. This is because the under-sampling pulses occur at different phases of subsequent cycles of the input signal. As a result, the under-samples form a lower frequency oscillating pattern.
  • the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the down-converted IF signal.
  • the frequency of the control signal 6406 would be calculated as follows:
  • the frequency of the control signal would be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc.
  • the input signal is directly down-converted to a demodulated baseband signal.
  • the under-sampling pulses occur at the same point of subsequent cycles of the input signal.
  • the under-samples form a constant output baseband signal.
  • the input signal includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the demodulated baseband signal.
  • the frequency of the control signal would be calculated as follows:
  • the frequency of the control signal 6406 should be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc.
  • a frequency within the FM bandwidth must be down-converted to baseband (i.e., zero IF).
  • baseband i.e., zero IF
  • FSK frequency shift keying
  • PSK phase shift keying
  • the mid-point between a lower frequency F, and an upper frequency F 2 (that is, [(F, + F 2 ) ⁇ 2]) of the FSK signal is down- converted to zero IF.
  • FSK frequency shift keying
  • PSK phase shift keying
  • Frequency of the down-converted signal 0 (i.e., baseband)
  • the frequency of the control signal 6406 should be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc.
  • the frequency of the down-converted PSK signal is substantially equal to one half the difference between the lower frequency F, and the upper frequency F 2 .
  • ASK ASK signal
  • F the lower frequency
  • F 2 the upper frequency
  • the aliasing rate of the control signal should be substantially equal to:
  • the frequency of the control signal 6406 should be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc.
  • the frequency of the control signal 6406 should be substantially equal to 1.802 GHz, 901 MHz, 450.5 MHz, 300.333 MHz, 225.25 MHz, etc.
  • the frequency of the down-converted AM signal is substantially equal to the difference between the lower frequency F, and the upper frequency F 2 (i.e., 1 MHz).
  • the pulses of the control signal have negligible apertures that tend towards zero. This makes the UFT module a high input impedance device. This configuration is useful for situations where minimal disturbance of the input signal may be desired.
  • the pulses of the control signal have non-negligible apertures that tend away from zero. This makes the UFT module a lower input impedance device. This allows the lower input impedance of the UFT module to be substantially matched with a source impedance of the input signal. This also improves the energy transfer from the input signal to the down-converted output signal, and hence the efficiency and signal to noise (s/n) ratio of UFT module.
  • the aliasing module is refe ⁇ ed to interchangeably herein as an energy transfer module or a gated transfer module, and the control signal is referred to as an energy transfer signal.
  • Exemplary systems and methods for generating and optimizing the control signal and for otherwise improving energy transfer and/or signal to noise ratio in an energy transfer module are described below.
  • An energy transfer system that includes an optional energy transfer signal module which can perform any of a variety of functions or combinations of functions including, but not limited to, generating an energy transfer signal.
  • the optional energy transfer signal module includes an aperture generator.
  • the aperture generator generates non-negligible aperture pulses from an input signal.
  • the input signal can be any type of periodic signal, including, but not limited to, a sinusoid, a square wave, a saw-tooth wave, etc. Systems for generating the input signal are described below.
  • the width or aperture of the pulses is determined by delay through a branch of the aperture generator. Generally, as the desired pulse width increases, the difficulty in meeting the requirements of the aperture generator decrease. In other words, to generate non-negligible aperture pulses for a given EM input frequency, the components used in the exemplary aperture generator do not require as fast reaction times as those that are required in an under-sampling system operating with the same EM input frequency.
  • the exemplary logic and implementation of the aperture generator are described for illustrative purposes only, and are not limiting. The actual logic employed can take many forms.
  • the exemplary aperture generator includes an optional inverter, which is shown for polarity consistency with other examples provided herein.
  • the input signal is generated externally of the optional energy transfer signal module.
  • the input signal is generated internally by the optional energy transfer signal module.
  • the input signal can be generated by an oscillator.
  • the oscillator can be internal to the optional energy transfer signal module or external to the optional energy transfer signal module.
  • the oscillator can be external to the energy transfer system.
  • the output of the oscillator may be any periodic waveform.
  • the type of down-conversion performed by the energy transfer system depends upon the aliasing rate of the energy transfer signal, which is determined by the frequency of the pulses.
  • the frequency of the pulses is determined by the frequency of the input signal. For example, when the frequency of the input signal is substantially equal to a harmonic or a sub-harmonic of the EM signal, the EM signal is directly down-converted to baseband (e.g. when EM signal is an AM signal or a PM signal), or converted from FM to a non-FM signal. When the frequency of the input signal is substantially equal to a harmonic or a sub-harmonic of a difference frequency, the EM signal is down-converted to an intermediate signal.
  • the optional energy transfer signal module can be implemented in hardware, software, firmware, or any combination thereof.
  • the down-converted output signal may be smoothed by filtering as desired.
  • the energy transfer module has input and output impedances generally defined by (1) the duty cycle of the switch module (i.e., the UFT module), and (2) the impedance of the storage module (e.g., the capacitor), at the frequencies of interest (e.g. at the EM input, and intermediate/baseband frequencies).
  • this aperture width e.g. the "closed time"
  • the characteristic impedance at the input and the output of the energy transfer module increases.
  • the impedance of the energy transfer module decreases.
  • the energy transfer module's characteristic input impedance is 300 ohms.
  • An impedance matching circuit can be used to efficiently couple an input EM signal that has a source impedance of, for example, 50 ohms, with the energy transfer module's impedance of, for example, 300 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary impedance directly or the use of an impedance match circuit as described below.
  • An impedance matched aliasing module may comprise an input impedance match module, an aliasing module, and an output impedance match module.
  • an initial configuration for the input impedance match module can be configured to include an inductor and a capacitor.
  • the configuration of the inductor and the capacitor in an "L network" is a possible configuration when going from a low impedance to a high impedance. The calculation of the values for the inductor and the capacitor is well known to those skilled in the relevant arts.
  • the output characteristic impedance can be impedance matched to take into consideration the desired output frequencies.
  • One of the steps in determining the characteristic output impedance of the energy transfer module could be to measure its value. Balancing the very low impedance of the storage module at the input EM frequency, the storage module should have an impedance at the desired output frequencies that is preferably greater than or equal to the load that is intended to be driven (for example, in an embodiment, storage module impedance at a desired 1MHz output frequency is 2K ohm and the desired load to be driven is 50 ohms).
  • An additional benefit of impedance matching is that filtering of unwanted signals can also be accomplished with the same components.
  • the energy transfer module's characteristic output impedance is, for example, 2K ohms.
  • An impedance matching circuit can be used to efficiently couple the down-converted signal with an output impedance of, for example, 2K ohms, to a load of, for example, 50 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary load impedance directly or the use of an impedance match circuit as described below.
  • a capacitor and an inductor can be configured in an "L network" matched filter.
  • the calculation of the values for the capacitor and the inductor is well known to those skilled in the relevant arts.
  • the configuration of the input impedance match module and the output impedance match module are considered to be initial starting points for impedance matching, in accordance with the present invention.
  • the initial designs may be suitable without further optimization.
  • the initial designs can be optimized in accordance with other various design criteria and considerations.
  • Resonant tank and other resonant structures can be used to further optimize the energy transfer characteristics of the invention.
  • resonant structures resonant about the input frequency
  • Resonant tank and other resonant structures can include, but are not limited to, surface acoustic wave (SAW) filters, dielectric resonators, diplexers, capacitors, inductors, etc.
  • SAW surface acoustic wave
  • An exemplary embodiment may comprise parallel tank circuits in a differential implementation.
  • a first parallel resonant or tank circuit (tankl) consists of a capacitor and an inductor.
  • a second tank circuit (tank2) also consists of a capacitor and an inductor.
  • parallel tank circuits provide: low impedance to frequencies below resonance; low impedance to frequencies above resonance; and high impedance to frequencies at and near resonance.
  • the first and second tank circuits may resonate at approximately
  • both tank circuits appear as relatively high impedance to the input frequency of 950 MHz, while simultaneously appearing as relatively low impedance to frequencies in the desired output range of 50 MHz.
  • An energy transfer signal controls a switch. When the energy transfer signal causes the switch to open and close, high frequency signal components will not pass through tankl or tank2. However, the lower signal components (50MHz in this embodiment) generated by the system will pass through tankl and tank2 with little attenuation. The effect of tankl and tank2 is to further separate the input and output signals from the same node, thereby producing a more stable input and output impedance.
  • the capacitors act to store the 50 MHz output signal energy between energy transfer pulses.
  • the series resonant frequency of a circuit a ⁇ angement is approximately 1 GHz.
  • This circuit increases the energy transfer characteristic of the system.
  • the ratio of the impedance of the inductor and the impedance of the storage capacitor is preferably kept relatively small so that the majority of the energy available will be transferred to the storage capacitor during operation.
  • a circuit may include a switch S and a capacitor having a capacitance "C.”
  • the switch S is controlled by a control signal , which includes pulses having apertures of duration "T.”
  • Equation 1 can be rewritten as Equation 3.
  • Equation 4 The change in charge over time is illustrated as " ⁇ q(t)"in Equation 4, which can be rewritten as Equation 5.
  • Equation 5 Using the trigonometric identity of Equation 6, Equation 5 becomes Equation 7, which can be rewritten as
  • Equation 8 the sine term in Equation 8 is a function of the aperture "T" only.
  • ⁇ q(t) is at a maximum when “T” is equal to an odd multiple of ⁇ (i.e., ⁇ , 3 ⁇ , 5 ⁇ , . . . ). Therefore, the capacitor experiences the greatest change in charge when the aperture "T” has a value of ⁇ or a time interval representative of 180 degrees of the input sinusoid.
  • Equations 9, 10, and 11 solve for "q(t)" by integrating Equation 1, allowing the charge on the capacitor with respect to time to be graphed on the same axis as the input sinusoid, "sin(t)," as illustrated in the graph of FIG. 30.
  • the aperture "T” decreases in value or tends toward an impulse, the phase between the charge on the capacitor "C" (or
  • Insertion loss Concepts of insertion loss are illustrated in FIG. 33.
  • the noise figure of a lossy passive device is numerically equal to the device insertion loss.
  • the noise figure for any device cannot be less that its insertion loss.
  • Insertion loss can be expressed by Equation 18 or 19. From the above discussion, it is observed that as the aperture "T" increases, more charge is transferred from the input to the capacitor, which increases power transfer from the input to the output. It has been observed that it is not necessary to accurately reproduce the input voltage at the output because relative modulated amplitude and phase information is retained in the transfened power.
  • the energy transfer signal is used to vary the input impedance seen by the EM Signal and to vary the output impedance driving a load.
  • An example of this embodiment is described below using a gated transfer module. The method described below is not limited to a gated transfer module.
  • the impedance looking into the circuit is substantially the impedance of a storage module, such as a storage capacitance, in parallel with the impedance of a load.
  • a storage module such as a storage capacitance
  • the impedance approaches infinity. It follows that the average impedance can be varied from the impedance of the storage module illustrated in parallel with load, to the highest obtainable impedance when switch is open, by varying the ratio of the time that the switch is open to the time the switch is closed.
  • the switch is controlled by an energy transfer signal.
  • the impedance can be varied by controlling the aperture width of the energy transfer signal in conjunction with the aliasing rate.
  • a circuit receives an input oscillating signal and outputs a pulse train that is a doubler output signal.
  • the circuit can be used to generate an energy transfer signal.
  • the width of the pulses in the doubler output signal can be varied. Increasing the delay of the signal propagated by the inverter, increases the width of the pulses.
  • the signal propagated by the inverter can be delayed by introducing a R/C low pass network in the output of the inverter. Other means of altering the delay of the signal propagated by the inverter will be well known to those skilled in the art. 7.5.2 Real Time Aperture Control
  • the aperture width/duration is adjusted in real time.
  • a clock signal may be used to generate an energy transfer signal, which includes energy transfer pluses having variable apertures.
  • the clock signal is inverted.
  • the clock signal may also be delayed.
  • the inverted clock signal and the delayed clock signal are then combined by an AND gate, generating the energy transfer signal, which is "high" when the delayed clock signal and the inverted clock signal are both "high.”
  • the amount of delay imparted to the delayed clock signal substantially determines the width or duration of the variable apertures.
  • the inverted clock signal is delayed relative to the clock signal, and then combined with the clock signal by an AND gate.
  • the clock signal may be delayed and then inverted. The result is then combined with the clock signal by an AND gate.
  • a real time aperture control system may comprise includes an RC circuit, which includes a voltage variable capacitor and a resistor.
  • a real time aperture control system may also include an inverter and an AND gate.
  • the AND gate includes an optional enable input for enabling/disabling the AND gate.
  • a real time aperture control system may optionally include an amplifier. Operation of a real time aperture control system is described as follows.
  • a real time aperture control system receives a clock signal, which is provided to both the inverter and to the RC circuit.
  • the inverter outputs an inverted clock signal and presents it to an AND gate.
  • the RC circuit delays the clock signal and outputs a delayed clock signal. The delay is determined primarily by the capacitance of the voltage variable capacitor. Generally, as the capacitance decreases, the delay decreases.
  • the delayed clock signal is optionally amplified by an optional amplifier, before being presented to the AND gate.
  • Amplification is desired, for example, where the RC constant of the RC circuit attenuates the signal below the threshold of the AND gate.
  • the AND gate combines the delayed clock signal, the inverted clock signal, and the optional enable signal, to generate the energy transfer signal.
  • the apertures are adjusted in real time by varying the voltage to the voltage variable capacitor. In an embodiment, the apertures are controlled to optimize power transfer. For example, in an embodiment, the apertures are controlled to maximize power transfer. Alternatively, the apertures are controlled for variable gain control (e.g. automatic gain control - AGC). In this embodiment, power transfer is reduced by reducing the apertures.
  • variable gain control e.g. automatic gain control - AGC
  • Modification or selection of the aperture can be done at the design level to remain a fixed value in the circuit, or in an alternative embodiment, may be dynamically adjusted to compensate for, or address, various design goals such as receiving RF signals with enhanced efficiency that are in distinctively different bands of operation, e.g. RF signals at 900 MHz and 1.8 GHz.
  • a bypass network is added to improve the efficiency of the energy transfer module.
  • Such a bypass network can be viewed as a means of synthetic aperture widening.
  • Components for a bypass network are selected so that the bypass network appears substantially lower impedance to transients of the switch module (i.e., frequencies greater than the received EM signal) and appears as a moderate to high impedance to the input EM signal (e.g., greater that 100 Ohms at the RF frequency).
  • the time that the input signal is now connected to the opposite side of the switch module is lengthened due to the shaping caused by this network, which in simple realizations may be a capacitor or series resonant inductor-capacitor.
  • a network that is series resonant above the input frequency would be a typical implementation.
  • This shaping improves the conversion efficiency of an input signal that would otherwise, if one considered the aperture of the energy transfer signal only, be relatively low in frequency to be optimal.
  • a bypass network may bypass a switch module.
  • the bypass network increases the efficiency of the energy transfer module when, for example, less than optimal aperture widths were chosen for a given input frequency on an energy transfer signal.
  • the bypass network could be of a variety of configurations. The following discussion will demonstrate the effects of a minimized aperture and the benefit provided by a bypassing network.
  • the peak-to-peak output (Vpp) may be 2.8mVpp applied to a 50 ohm load. Changing the aperture to 270ps will result in a diminished output of 2.5mVpp applied to a 50 ohm load.
  • a bypass network may be added. The result of this addition is that, for example, 3.2Vpp can now be applied to the 50 ohm load.
  • a system may use a down-converted signal as a feedback to control various characteristics of the energy transfer module to modify the down-converted signal.
  • the amplitude of the down-converted signal varies as a function of the frequency and phase differences between the EM signal and the energy transfer signal.
  • the down-converted signal is used as the feedback to control the frequency and phase relationship between the EM signal and the energy transfer signal. This can be accomplished using a logic circuit.
  • a state-machine is used as an example.
  • a state machine reads an analog to digital (A/D) converter and controls a digital to analog (D/A) converter.
  • the state machine includes
  • the state machine uses at least one memory flag.
  • the D/A converter controls an input to a voltage controlled oscillator (VCO).
  • VCO voltage controlled oscillator
  • the VCO controls a frequency input of a pulse generator, which, in an embodiment, is substantially similar to a pulse generator.
  • the pulse generator may generate an energy transfer signal.
  • the state machine operates in accordance with a state machine flowchart 3400 in FIG. 34.
  • the result of this operation is to modify the frequency and phase relationship between energy transfer signal and the EM signal to substantially maintain the amplitude of the down-converted signal at an optimum level.
  • the amplitude of the down-converted signal can be made to vary with the amplitude of the energy transfer signal.
  • a switch module is a FET, wherein the gate of the FET receives the energy transfer signal
  • the amplitude of the energy transfer signal can determine the "on" resistance of the FET, which affects the amplitude of the down-converted signal.
  • An optional energy transfer signal module can be an analog circuit that enables an automatic gain control function. Alternate implementations will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Alternate implementations fall within the scope and spirit of the present invention.
  • the present invention is directed to systems and methods of frequency up- conversion, and applications of same.
  • FIG. 35 An exemplary frequency up-conversion system 3500 is illustrated in FIG. 35. The frequency up-conversion system 3500 is now described.
  • An input signal 3502 (designated as "Control Signal” in FIG. 35) is accepted by a switch module 3504.
  • the input signal 3502 is a FM input signal 3806, an example of which is shown in FIG. 38C.
  • FM input signal 3806 may have been generated by modulating information signal 3802 onto oscillating signal 3804 (FIGs. 38A and 38B).
  • the information signal 3802 can be analog, digital, or any combination thereof, and any modulation scheme can be used.
  • the output of switch module 3504 is a harmonically rich signal 3506, shown for example in FIG. 38D as a harmonically rich signal 3808.
  • the harmonically rich signal 3808 has a continuous and periodic waveform.
  • FIG. 38E is an expanded view of two sections of harmonically rich signal 3808, section 3810 and section 3812.
  • the harmonically rich signal 3808 may be a rectangular wave, such as a square wave or a pulse (although, the invention is not limited to this embodiment).
  • rectangular waveform is used to refer to waveforms that are substantially rectangular.
  • square wave refers to those waveforms that are substantially square and it is not the intent of the present invention that a perfect square wave be generated or needed.
  • Harmonically rich signal 3808 is comprised of a plurality of sinusoidal waves whose frequencies are integer multiples of the fundamental frequency of the waveform of the harmonically rich signal 3808. These sinusoidal waves are referred to as the harmonics of the underlying waveform, and the fundamental frequency is refened to as the first harmonic.
  • FIG. 38F and FIG. 38G show separately the sinusoidal components making up the first, third, and fifth harmonics of section 3810 and section 3812. (Note that in theory there may be an infinite number of harmonics; in this example, because harmonically rich signal 3808 is shown as a square wave, there are only odd harmonics). Three harmonics are shown simultaneously (but not summed) in FIG. 38H.
  • the relative amplitudes of the harmonics are generally a function of the relative widths of the pulses of harmonically rich signal 3506 and the period of the fundamental frequency, and can be determined by doing a Fourier analysis of harmonically rich signal 3506.
  • the input signal 3806 may be shaped to ensure that the amplitude of the desired harmonic is sufficient for its intended use (e.g., transmission).
  • a filter 3508 filters out any undesired frequencies (harmonics), and outputs an electromagnetic (EM) signal at the desired harmonic frequency or frequencies as an output signal 3510, shown for example as a filtered output signal 3814 in FIG. 381.
  • EM electromagnetic
  • FIG. 36 illustrates an exemplary universal frequency up-conversion (UFU) module 3601.
  • the UFU module 3601 includes an exemplary switch module 3504, which comprises a bias signal 3602, a resistor or impedance 3604, a universal frequency translator (UFT) 3650, and a ground 3608.
  • the UFT 3650 includes a switch 3606.
  • the input signal 3502 (designated as "Control Signal” in FIG. 36) controls the switch 3606 in the UFT 3650, and causes it to close and open. Harmonically rich signal 3506 is generated at a node 3605 located between the resistor or impedance 3604 and the switch 3606.
  • an exemplary filter 3508 is comprised of a capacitor 3610 and an inductor 3612 shunted to a ground 3614.
  • the filter is designed to filter out the undesired harmonics of harmonically rich signal 3506.
  • the invention is not limited to the UFU embodiment shown in FIG. 36.
  • an unshaped input signal 3701 is routed to a pulse shaping module 3702.
  • the pulse shaping module 3702 modifies the unshaped input signal 3701 to generate a (modified) input signal 3502
  • the input signal 3502 is routed to the switch module 3504, which operates in the manner described above. Also, the filter 3508 of FIG. 37 operates in the manner described above.
  • the purpose of the pulse shaping module 3702 is to define the pulse width of the input signal 3502. Recall that the input signal 3502 controls the opening and closing of the switch 3606 in switch module 3504. During such operation, the pulse width of the input signal 3502 establishes the pulse width of the harmonically rich signal 3506. As stated above, the relative amplitudes of the harmonics of the harmonically rich signal 3506 are a function of at least the pulse width of the harmonically rich signal 3506. As such, the pulse width of the input signal 3502 contributes to setting the relative amplitudes of the harmonics of harmonically rich signal 3506.
  • the present invention is directed to systems and methods of unified down- conversion and filtering (UDF), and applications of same.
  • the present invention includes a unified down-converting and filtering
  • UDF frequency selectivity module
  • the invention achieves high frequency selectivity prior to frequency translation (the invention is not limited to this embodiment).
  • the invention achieves high frequency selectivity at substantially any frequency, including but not limited to RF (radio frequency) and greater frequencies. It should be understood that the invention is not limited to this example of RF and greater frequencies.
  • the invention is intended, adapted, and capable of working with lower than radio frequencies.
  • FIG. 39 is a conceptual block diagram of a UDF module 3902 according to an embodiment of the present invention.
  • the UDF module 3902 performs at least frequency translation and frequency selectivity.
  • UDF module 3902 The effect achieved by UDF module 3902 is to perform the frequency selectivity operation prior to the performance of the frequency translation operation.
  • UDF module 3902 effectively performs input filtering.
  • input filtering involves a relatively nanow bandwidth.
  • such input filtering may represent channel select filtering, where the filter bandwidth may be, for example, 50 KHz to 150 KHz. It should be understood, however, that the invention is not limited to these frequencies.
  • the invention is intended, adapted, and capable of achieving filter bandwidths of less than and greater than these values.
  • input signals 3904 received by UDF module 3902 are at radio frequencies.
  • the UDF module 3902 effectively operates to input filter these RF input signals 3904.
  • UDF module 3902 effectively performs input, channel select filtering of RF input signal 3904. Accordingly, the invention achieves high selectivity at high frequencies.
  • the UDF module 3902 effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof.
  • UDF module 3902 includes a frequency translator 3908.
  • the frequency translator 3908 conceptually represents that portion of UDF module 3902 that performs frequency translation (down conversion).
  • the UDF module 3902 also conceptually includes an apparent input filter 3906 (also sometimes called an input filtering emulator).
  • apparent input filter 3906 represents that portion of UDF module 3902 that performs input filtering.
  • the input filtering operation performed by UDF module 3902 is integrated with the frequency translation operation.
  • the input filtering operation can be viewed as being performed concunently with the frequency translation operation. This is a reason why input filter 3906 is herein refened to as an "apparent" input filter 3906.
  • the UDF module 3902 of the present invention includes a number of advantages.
  • UDF module 3902 can be designed with a filter center frequency f c on the order of 900 MHz, and a filter bandwidth on the order of 50 KHz.
  • the filtering center frequency f c of UDF module 3902 can be electrically adjusted, either statically or dynamically.
  • UDF module 3902 can be designed to amplify input signals.
  • UDF module 3902 can be implemented without large resistors, capacitors, or inductors. Also, UDF module 3902 does not require that tight tolerances be maintained on the values of its individual components, i.e., its resistors, capacitors, inductors, etc. As a result, the architecture of UDF module 3902 is friendly to integrated circuit design techniques and processes.
  • UDF module 3902 performs the frequency selectivity operation and the frequency translation operation as a single, unified (integrated) operation. According to the invention, operations relating to frequency translation also contribute to the performance of frequency selectivity, and vice versa.
  • the UDF module generates an output signal from an input signal using samples/instances of the input signal and samples/instances of the output signal. More particularly, first, the input signal is under-sampled. This input sample includes information (such as amplitude, phase, etc.) representative of the input signal existing at the time the sample was taken.
  • the effect of repetitively performing this step is to translate the frequency (that is, down-convert) of the input signal to a desired lower frequency, such as an intermediate frequency (LF) or baseband.
  • a desired lower frequency such as an intermediate frequency (LF) or baseband.
  • the input sample is held (that is, delayed).
  • one or more delayed input samples are combined with one or more delayed instances of the output signal (some of which may have been scaled) to generate a current instance of the output signal.
  • the output signal is generated from prior samples/instances of the input signal and/or the output signal.
  • cu ⁇ ent samples/instances of the input signal and/or the output signal may be used to generate current instances of the output signal.
  • the UDF module preferably performs input filtering and frequency down-conversion in a unified manner.
  • FIG. 41 illustrates an exemplary implementation of a unified down-converting and filtering (UDF) module 4122.
  • the UDF module 4122 performs the frequency translation operation and the frequency selectivity operation in an integrated, unified manner as described above, and as further described below.
  • the frequency selectivity operation performed by UDF module 4122 comprises a band-pass filtering operation according to EQ. 20, below, which is an exemplary representation of a band-pass filtering transfer function.
  • the invention effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof.
  • filtering including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof.
  • EQ. 20 is referred to herein for illustrative purposes only, and is not limiting.
  • the UDF module 4122 includes a down-convert and delay module 4124, first and second delay modules 4128 and 4130, first and second scaling modules 4132 and 4134, an output sample and hold module 4136, and an (optional) output smoothing module 4138.
  • output smoothing module 4138 is optional.
  • down-convert and delay module 4124 and first and second delay modules 4128 and 4130 include switches that are controlled by a clock having two phases, ⁇ , and ⁇ 2 .
  • ⁇ , and ⁇ 2 preferably have the same frequency, and are non-overlapping (alternatively, a plurality such as two clock signals having these characteristics could be used).
  • non-overlapping is defined as two or more signals where only one of the signals is active at any given time.
  • signals are "active" when they are high. In other embodiments, signals are active when they are low.
  • each of these switches closes on a rising edge of ⁇ , or ⁇ 2 , and opens on the next co ⁇ esponding falling edge of ⁇ , or ⁇ 2 .
  • the invention is not limited to this example. As will be apparent to persons skilled in the relevant art(s), other clock conventions can be used to control the switches.
  • the exemplary UDF module 4122 has a filter center frequency of 900.2 MHz and a filter bandwidth of 570 KHz.
  • the pass band of UDF module 4122 is on the order of 899.915 MHz to 900.485 MHz.
  • the Q factor of UDF module 4122 is approximately 1879 (i.e., 900.2 MHz divided by 570 KHz).
  • UDF module 4122 shall now be described with reference to a Table 4002 (FIG. 40) that indicates exemplary values at nodes in UDF module 4122 at a number of consecutive time increments. It is assumed in Table 4002 that UDF module 4122 begins operating at time t-1. As indicated below, UDF module 4122 reaches steady state a few time units after operation begins. The number of time units necessary for a given UDF module to reach steady state depends on the configuration of the UDF module, and will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. At the rising edge of ⁇ , at time t-1, a switch 4150 in down-convert and delay module 4124 closes.
  • capacitor 4152 This allows a capacitor 4152 to charge to the current value of an input signal, VI,.rion such that node 4102 is at VI,. ,. This is indicated by cell 4004 in FIG. 40.
  • the combination of switch 4150 and capacitor 4152 in down-convert and delay module 4124 operates to translate the frequency of the input signal VI to a desired lower frequency, such as IF or baseband.
  • the value stored in capacitor 4152 represents an instance of a down-converted image of the input signal VI.
  • down-convert and delay module 4124 performs frequency down-conversion is further described elsewhere in this application in the section entitled "Down-conversion Using a Universal Frequency Translation Module.”
  • a switch 4158 in first delay module 4128 closes, allowing a capacitor 4160 to charge to VO,_ ,, such that node 4106 is at NO,.,. This is indicated by cell 4006 in Table 4002. (In practice, VO,., is undefined at this point. However, for ease of understanding, VO,. , shall continue to be used for purposes of explanation.)
  • a switch 4154 in down-convert and delay module 4124 closes, allowing a capacitor 4156 to charge to the level of capacitor 4152.
  • capacitor 4156 charges to VI, ,, such that node 4104 is at VI,.,. This is indicated by cell 4010 in Table 4002.
  • the UDF module 4122 may optionally include a unity gain module 4190A between capacitors 4152 and 4156.
  • the unity gain module 4190A operates as a cu ⁇ ent source to enable capacitor 4156 to charge without draining the charge from capacitor
  • UDF module 4122 may include other unity gain modules 4190B-4190G. It should be understood that, for many embodiments and applications of the invention, these unity gain modules 4190A-4190G are optional. The structure and operation of unity gain modules 4190 will be apparent to persons skilled in the relevant art(s).
  • a switch 4162 in first delay module 4128 closes, allowing a capacitor 4164 to charge to the level of capacitor 4160. Accordingly, capacitor 4164 charges to VO,.,, such that node 4108 is at VO,.,. This is indicated by cell 4014 in Table 4002.
  • a switch 4170 in second delay module 4130 closes, allowing a capacitor 4172 to charge to a value stored in a capacitor 4168.
  • the value in capacitor 4168 is undefined, so the value in capacitor 4172 is undefined. This is indicated by cell 4015 in table 4002.
  • switch 4150 in down-convert and delay module 4124 closes. This allows capacitor 4152 to charge to VI, such that node 4102 is at VI,. This is indicated in cell 4016 of Table 4002. Also at the rising edge of ⁇ , at time t, switch 4158 in first delay module 4128 closes, thereby allowing capacitor 4160 to charge to VO,. Accordingly, node 4106 is at VO,. This is indicated in cell 4020 in Table 4002.
  • switch 4166 in second delay module 4130 closes, allowing a capacitor 4168 to charge to the level of capacitor 4164. Therefore, capacitor 4168 charges to VO,.,, such that node 4110 is at VO,.,. This is indicated by cell
  • switch 4154 in down-convert and delay module 4124 closes, allowing capacitor 4156 to charge to the level of capacitor 4152. Accordingly, capacitor 4156 charges to VI tent such that node 4104 is at VI,. This is indicated by cell 4028 in Table 4002.
  • switch 4162 in first delay module 4128 closes, allowing capacitor 4164 to charge to the level in capacitor 4160. Therefore, capacitor 4164 charges to VO mouth such that node 4108 is at VO,. This is indicated by cell 4032 in Table 4002.
  • switch 4170 in second delay module 4130 closes, allowing capacitor 4172 in second delay module 4130 to charge to the level of capacitor 4168 in second delay module 4130. Therefore, capacitor 4172 charges to VO,_ ,, such that node 4112 is at VO,_ ,. This is indicated in cell 4036 of FIG. 40.
  • switch 4150 in down-convert and delay module 4124 closes, allowing capacitor 4152 to charge to VI, +1 . Therefore, node 4102 is at VI, +1 , as indicated by cell 4038 of Table 4002.
  • switch 4158 in first delay module 4128 closes, allowing capacitor 4160 to charge to VO, +1 . Accordingly, node 4106 is at VO, +rod as indicated by cell 4042 in Table 4002.
  • switch 4166 in second delay module 4130 closes, allowing capacitor 4168 to charge to the level of capacitor 4164.
  • capacitor 4168 charges to VOficient as indicated by cell 4046 of Table 4002.
  • first scaling module 4132 scales the value at node 4108 (i.e., the output of first delay module 4128) by a scaling factor of -0.1. Accordingly, the value present at node 41 14 at time t+1 is -0.1'VO,.
  • second scaling module 4134 scales the value present at node 4112 (i.e., the output of second scaling module 4130) by a scaling factor of -0.8. Accordingly, the value present at node 4116 is -0.8»VO,_, at time t+1.
  • summer 4126 At time t+1, the values at the inputs of summer 4126 are: VI, at node 4104, -0.1'VO, at node 4114, and -0.8»VO,_, at node 4116 (in the example of FIG. 41, the values at nodes 4114 and 4116 are summed by a second summer 4125, and this sum is presented to summer 4126). Accordingly, at time t+1, summer 4126 generates a signal equal to VI, - 0.1'VO, - 0.8»VO,.,.
  • a switch 4191 in output sample and hold module 4136 closes, thereby allowing a capacitor 4192 to charge to VO, + ,. Accordingly, capacitor 4192 charges to VO, + ,, which is equal to the sum generated by adder 4126. As just noted, this value is equal to: VI, - 0.1»VO, - 0.8»VO,_,. This is indicated in cell 4050 of Table 4002. This value is presented to optional output smoothing module 4138, which smooths the signal to thereby generate the instance of the output signal VO, +1 . It is apparent from inspection that this value of VO, + , is consistent with the band pass filter transfer function of EQ. 20. 10.
  • an integrated communication system will result by combining any two of the embodiments described above, or by combining all three of the embodiments described above.
  • This integrated communication system can be employed, for example, in a transceiver used in a family radio system.

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Abstract

A method and system is described for several embodiments of a communication system. In a first embodiment, a method and system is described wherein a signal is received and down-converted and wherein power consumption can be characterized as 'ultra-low.' In a second embodiment, a method and system is described wherein undesirable images are rejected in a down-conversion system. In a third embodiment, a method and system is described for directly down-converting analog FM signals and digital FM signals to demodulated baseband information signals. In a fourth embodiment, a method and system is described wherein a signal is transmitted in a highly efficient manner. In a fifth embodiment, the present invention is directed toward a multi-band communication system that can transmit and/or receive one or more information signals on one or more transmission frequencies using one or more modulation schemes. The receiver and transmitter operate in a plurality of modes, including but not limited to a single band/channel mode, and a multiple band/channel mode. The receiver and transmitter may operate separately or as part of a transceiver. According to embodiments of the invention, the frequency translation is implemented using a universal frequency translator (UFT). In the aforementioned embodiments, the invention is used in a family radio service (FRS) unit, although the invention is not limited to this embodiment.

Description

Frequency Translation and Embodiments Thereof Such as the Family Radio Service
Background of the Invention
Field of the Invention
The present invention is generally directed toward receiver-transmitter systems referred to as Family Radio Service (FRS) units, although the invention is not limited to this embodiment. The Family Radio Service is one of the Citizens Band Radio Services. It is intended for the use of family, friends, and associates to communicate among themselves within a neighborhood or while on group outings. There are fourteen discreet FRS channels available for use on a "take turns" basis. The FRS unit channel frequencies are:
Channel No. (MHz)
1 462.5625
2 462.5875
3 462.6125
4 462.6375
5 462.6625
6 462.6875
7 462.7125
8 467.5625
9 467.5875
10 467.6125
11 467.6375
12 467.6625
13 467.6875
14 467.7125
Other selected technical specifications include, but are not limited to:
(a) Frequency modulation (although phase modulation is allowed);
(b) Frequency tolerance of each FRS unit must be maintained within 0.00025%;
(c) The authorized bandwidth for an FRS unit is 12.5 KHz; and (d) Effective radiated power (ERP) shall not, under any condition of modulation, exceed 0.500 W.
The operating rules for the FRS are found at 47 C.F.R. 95.191 - 95.194. For additional technical information, see 47 C.F.R. 95.601 - 95.669.
Related Art
Modern day communication systems employ components such as transmitters and receivers to transmit information from a source to a destination. To accomplish this transmission, information is imparted on a carrier signal and the carrier signal is then transmitted. Typically, the carrier signal is at a frequency higher than the baseband frequency of the information signal. Typical ways that the information is imparted on a carrier signal are called modulation.
Summary of the Invention
The present invention is directed to a communications system with an image-reject down-converter and to a communications system comprising a method and system for directly down-converting FM signals to demodulated baseband information signals. The invention has a number of aspects, including an image-reject down-converter, an ultra-low power down-converter, and a high-efficiency transmitter and can be used to directly down- convert analog FM signals and digital FM signals to demodulated baseband information signals. In an embodiment, the present invention is used in a family radio system. It is to be understood, however, that the invention is not limited to this particular embodiment.
Other implementations in communications-related environments are within the scope and spirit of the invention.
In an embodiment, the invention includes aliasing an FM signal at an aliasing rate substantially equal to the frequency of the FM signal or substantially equal to a sub- harmonic thereof; adjusting the aliasing rate in accordance with frequency changes on the
FM signal to maintain the aliasing rate substantially equal to the frequency of the FM signal; and outputting a demodulated baseband information signal. The invention includes an optional step of compensating for phase delays and/or other characteristics of the loop in order to maintain bandwidth and stability for the loop.
In an embodiment, the invention is implemented as a zero IF FM decoder that down-converts an FM signal as an I and Q pair, sums the I and Q pair, and generates a correction signal from the sum. The correction signal is used to adjust the aliasing rate to continually alias the FM signal at a sub-harmonic of the FM signal - even as the FM signal changes frequency.
In an embodiment, the invention is implemented as an ultra-low power down- converter. The present invention is also directed toward a multi-mode, multi-band communication system that can transmit and/or receive one or more information signals on one or more transmission frequencies using one or more modulation schemes.
An embodiment of the invention is directed to a receiver having multi-mode and multi-band functionality and capabilities. According to the invention, the receiver is capable of selectively operating over a plurality of bands and channels. The receiver operates in a plurality of modes, including but not limited to a single band/channel mode, and a multiple band/channel mode. The receiver may form a portion of a transceiver.
Another embodiment of the invention is a transmission subsystem of the communications system. According to embodiments of the invention, the up-conversion section is implemented using a universal frequency translator (UFT). The transmission subsystem may form a portion of a transceiver.
In an embodiment, the present invention is used in a family radio system. It is to be understood, however, that the invention is not limited to this particular embodiment. Other implementations in communications-related environments are within the scope and spirit of the invention.
The present invention has a number of advantages, including power reduction, tuning reduction, parts reduction, price reduction, size reduction, performance increase, greater efficiency, and increased integration possibilities.
Further features and advantages of the invention, as well as various embodiments of the invention, are described in detail below with reference to the accompanying drawings. Brief Description of the Figures
FIG. 1 illustrates an exemplary block diagram of an ultra-low power down-converter in accordance with the present invention;
FIG. 2 illustrates a schematic drawing of an exemplary implementation of the ultra- low power down-converter of FIG. 1 ;
FIG. 3 illustrates an exemplary block diagram of the universal frequency translator module being used in the ultra-low power down-converter embodiment of the present invention;
FIG. 4 illustrates a process for directly down-converting an FM signal to a demodulated baseband information signal;
FIG. 5 is a block diagram of an exemplary zero LF FM decoder for implementing the process of FIG. 4;
FIG. 6A is a timing diagram of an exemplary FM signal;
FIG. 6B is a timing diagram of an exemplary first aliasing signal, in accordance with the present invention;
FIG. 6C is a timing diagram of an exemplary second aliasing signal, in accordance with the present invention;
FIG. 6D is a timing diagram of exemplary down-converted signals and a summation signal, in accordance with the present invention; FIG. 6E illustrates an exemplary control signal for controlling an aliasing rate for directly down-converting an FM signal to a demodulated baseband information signal, in accordance with the present invention;
FIG. 7 is a schematic diagram of an exemplary implementation of a summing module, an integration module and an optional loop compensation module, in accordance with the present invention;
FIG. 8 illustrates an exemplary block diagram of a transmitter embodiment of the present invention;
FIG. 9 illustrates an exemplary block diagram of the universal frequency translator module being used in a transmitter embodiment of the present invention; FIG. 10 is a schematic diagram of an exemplary implementation of the transmitter embodiment illustrated in FIG. 8; FIG. 11 illustrates an exemplary implementation of a switch in the universal frequency translator module of FIG. 9;
FIG. 12a illustrates an exemplary mixer circuit;
FIG. 12b illustrates an exemplary frequency domain plot corresponding to the mixed circuit of FIG. 12a;
FIG. 13a illustrates an exemplary block diagram of the image-reject down-converter embodiment of the present invention;
FIG. 13b illustrates a frequency domain plot of waveforms associated with the exemplary block diagram of FIG. 13a; FIG. 13c illustrates a phase relationship table for waveforms associated with the exemplary block diagram of FIG. 13a;
FIGs. 14a and 14b illustrate a detailed schematic drawing of the exemplary block diagram of FIG. 13a;
FIG. 15 is a block diagram of a receiver according to an embodiment of the invention; FIG. 16 is a block diagram of a receiver according to an alternative embodiment of the invention;
FIG. 17 is a flowchart of the invention when operating according to a single band/channel mode;
FIG. 18 is a flowchart of the invention when operating according to a multiple band/channel mode;
FIG. 19 is a block diagram of a transceiver according to an embodiment of the invention;
FIG. 20 illustrates an exemplary use scenario used to described the operation of an embodiment of the invention; FIG. 21 is a top level block diagram of one embodiment of the transmitter subsystem of the present invention;
FIG. 22 is a block diagram of an exemplary embodiment of the information signal conditioning module and the signal selection module;
FIG. 23 is a block diagram of an exemplary embodiment of the modulation and frequency selection module and an exemplary embodiment of the bias/reference signal module; FIG. 24 illustrates an exemplary block diagram of the universal frequency translator module being used in the transmitter subsystem embodiment of the present invention;
FIG.25 illustrates an exemplary implementation of a switch in the universal frequency translator module of FIG. 4; FIG. 26 illustrates an exemplary structure for a frequency band selection module;
FIG.27 illustrates an exemplary structure for the optional output conditioning module; FIGs.28A-28D depict some frequency allocations operable with the present invention; FIG.29 illustrates equations for determining charge transfer, in accordance with the present invention; FIG. 30 illustrates relationships between capacitor charging and aperture, in accordance with the present invention;
FIG. 31 illustrates relationships between capacitor charging and aperture, in accordance with the present invention;
FIG.32 illustrates power-charge relationship equations, in accordance with the present invention;
FIG. 33 illustrates insertion loss equations, in accordance with the present invention; FIG.34 illustrates a flowchart of state machine operation according to an embodiment of the present invention;
FIG. 35 is a block diagram of a universal frequency up-conversion (UFU) module according to an embodiment of the invention;
FIG. 36 is a more detailed diagram of a universal frequency up-conversion (UFU) module according to an embodiment of the invention;
FIG. 37 is a block diagram of a universal frequency up-conversion (UFU) module according to an alternative embodiment of the invention; FIGs. 38A-38I illustrate exemplary waveforms used to describe the operation of the
UFU module;
FIG. 39 illustrates a unified down-converting and filtering (UDF) module according to an embodiment of the invention;
FIG. 40 is a table of exemplary values at nodes in the UDF module of FIG. 41 ; and FIG. 41 is a detailed diagram of an exemplary UDF module according to an embodiment of the invention. Detailed Description of the Preferred Embodiments
The following sections describe methods related to an ultra-low power down- converter, an image-reject down-converter, and a high-efficiency transmitter. Structural exemplary embodiments for achieving these methods are also described. It should be understood that the invention is not limited to the particular embodiments described below. Equivalents, extensions, variations, deviations, etc., of the following will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such equivalents, extensions, variations, deviations, etc., are within the scope and spirit of the present invention.
Table of Contents
1. Ultra-Low Power Down-Converter
2. Zero IF FM Decoder
3. High-Efficiency Transmitter
4. Image-Reject Down-Converter 5. Multi-mode and Multi -band Receiver
5.1 Overview of the Multi-mode/Multi-band Receiver
5.2 Structure of the Multi-mode/Multi-band Receiver
5.3 Operation of the Multi-mode/Multi-band Receiver
5.3.1 Exemplary Scenario Using the Multi-mode/Multi-band Receiver 5.3.2 Single Band/Channel Operation of the Multi-mode/Multi-band
Receiver 5.3.3 Multiple Band/Channel Operation of the Multi-mode/Multi-band Receiver 6. Multi -mode and Multi -band Transmitter 7. Down-conversion Using a Universal Frequency Translation Module.
7.1 Optional Energy Transfer Signal Module
7.2 Impedance Matching
7.3 Tanks and Resonant Structures 7.4 Charge and Power Transfer Concepts
7.5 Optimizing and Adjusting the Non-Negligible Aperture Width/Duration
7.5.1 Varying the Input and Output Impedances
7.5.2 Real Time Aperture Control 7.6 Adding a Bypass Network
7.7 Modifying the Energy Transfer Signal Using Feedback
7.8 Other Implementations
8. Frequency Up-conversion
9. Unified Down-conversion and Filtering 10. Integrated Communication System
11. Conclusion
/. Ultra-Low Power Down-Converter
The present invention can be implemented with an aliasing system as described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module."
FIG. 1 illustrates an exemplary aliasing system 100 for down-converting electromagnetic (EM) signals, such as an RF input (RFιn) signal 102. The aliasing system 100 is an exemplary embodiment of an optimized aliasing system, referred to herein as an ultra low power down-converter. The exemplary aliasing system 100 includes an aliasing module 110 that aliases an
EM signal 112, using an aliasing signal 114, and outputs a down-converted signal 1 16, as described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module." The aliasing module 110 is also referred to herein as a universal frequency translator (UFT) module. Aliasing system 100 optionally includes one or more of an input impedance match module 1 18, a parallel resonant tank module 120, and an output impedance match module 122.
Aliasing system 100 optionally includes a local oscillator (LO) impedance match module 124 for impedance matching a local oscillator input (LOm) signal 126, generated by a local oscillator 128, to the aliasing module 110. The LO impedance match module 124 can be designed to increase the voltage of the LOin signal 126, as illustrated by a higher voltage LOin signal 130. The LO impedance match module 124 permits the aliasing system 100 to efficiently operate with a relatively low voltage LOin signal 126, without the use of power consuming amplifiers that would otherwise be necessary to increase the amplitude of the LOjn signal 126.
Unless otherwise noted, the aliasing signal 114 is used interchangeably herein to refer to the LOin signal 126 and or the higher voltage LOjn signal 130.
The aliasing system 100 optionally includes a DC block 132 that substantially blocks DC while passing substantially all non-DC. In the exemplary embodiment, the DC block 132 is a capacitor 133. A variety of implementations of the DC block 132 suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein.
The aliasing system 100 optionally includes a bias module 134 for biasing the aliasing signal 114. A variety of implementations of the biasing module 134 suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein.
FIG. 2 illustrates an exemplary schematic diagram 202 that can be used to implement the aliasing system 100. The exemplary schematic diagram 202 provides exemplary circuit elements that can be used within the optional input impedance match module 118, the optional parallel resonant tank 120, the optional output impedance match module 122, the optional LO impedance match module, the optional DC block 132, and the optional bias module 134. The invention is not limited to the exemplary embodiment of FIG. 2.
The exemplary schematic diagram 202 includes a storage module 210 for storing energy transferred from the EM signal 112 as described herein in the section entitled
"Down-conversion Using a Universal Frequency Translation Module."
In the schematic diagram 202, the aliasing module 110 of FIG. 1 is illustrated as an application specific integrated circuit (ASIC) 212. In an embodiment, the ASIC is implemented in complementary metal oxide semiconductor (CMOS). The ASIC 212 is coupled to a first voltage source 218 for supplying power circuits within the ASIC 212. The circuits within the ASIC 212 are described below with reference to FIG. 3. An optional first bypass module 220 is optionally disposed as illustrated to substantially eliminate unwanted frequencies from the first power supply 218 and from the ASIC 212.
The ASIC 212 includes a substrate (not shown) which is optionally coupled to a second voltage source 214. An advantage of coupling the substrate to the second voltage source 214 is described below with reference to FIG. 3. When the substrate is coupled to the second voltage source 214, an optional second bypass module 216 is optionally disposed as illustrated to substantially eliminate unwanted frequencies from the substrate and the second voltage source 214.
FIG. 3 illustrates an aliasing module 302, which is an exemplary embodiment of the aliasing module 110 and the ASIC 212. The aliasing module 302 includes a sine wave to square wave converter module 310, a pulse shaper module 312 and a switch module 314. The sine wave to square wave converter module 310 converts a sine wave 1 14 from the local oscillator 128 to a square wave 311. The pulse shaper module 312 receives the square wave 311 and generates energy transfer pulses 313 therefrom. Energy transfer pulses are discussed in greater detail in the section entitled "Down-conversion Using a
Universal Frequency Translation Module."
In an embodiment, the pulse shaper module 312 is implemented as a mono-stable multi-state vibrator. A variety of implementations of the pulse shaper module 312 suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein.
Generally, the frequency of the energy transfer pulses 31 1 is determined by the frequency of the aliasing signal 114 and the width or aperture of the energy transfer pulses is determined by the pulse shaper module 312.
In the illustrated embodiment, where the sine wave to square wave converter module 310 and the pulse shaper module 312 are provided on-chip, the ASIC substrate
(not shown) is optionally coupled to the second power supply 214. The second power supply 214 can be varied to affect the performance of the circuits on the ASIC 212, with a result of effectively adjusting the pulse width of the energy transfer pulses 313.
In an alternative embodiment, the sine wave to square wave converter module 310 and/or the pulse shaper module 312 are provided off-chip.
An advantage of the ultra-low power down-converter aliasing system 100 is its low power consumption. For example, in an actual implementation, the aliasing module 302 required an average of approximately 1 mA and consumed approximately 3 to 5 m Watt. This is significantly greater performance than conventional down converter systems.
Other advantages of the ultra-low power down-converter aliasing system 100 include tuning reduction, parts reduction, price reduction, size reduction, performance increase, low frequency and power LO, and excellent linearity. Another advantage of the ultra-low power down-converter aliasing system is that it can down-convert EM signals as high as 3.5 GHz when implemented in CMOS. Higher frequencies can be down- converted using other materials such as gallium arsenide (GaAs), for example.
In an embodiment, an ultra-low power down-converter as described above is implemented in an FRS.
2. Zero IF FM Decoder
The section entitled "Down-conversion Using a Universal Frequency Translation Module" describes methods and systems for directly down-converting EM signals.
Among other things, it describes how modulated EM signals can be directly down- converted to demodulated baseband information signals (also referred to interchangeably herein as direct to data or D2D embodiments). For example, amplitude modulated (AM) signals and phase modulated (PM) signals can be directly down-converted to demodulated baseband information signals by aliasing the AM and PM signals at sub-harmonics of the AM and PM signals. Frequency modulated (FM) signals, however, pose special challenges. For example, frequency shift keying (FSK) signals, when aliased at fixed sub-harmonic, are down-converted to amplitude shift keying signals or to phase shift keying (PSK) signals. FM signals, unlike AM and PM signals, are not necessarily directly down-converted to demodulated baseband information signals by aliasing at a fixed sub-harmonic. The present invention is a method and system for directly down-converting FM signals to demodulated baseband information signals.
FIG. 4 is a flowchart 402 that illustrates a method for directly down-converting FM signals to demodulated baseband information signals. FIG. 5 illustrates an exemplary embodiment of a zero IF FM decoder 502, which can be used to implement the process illustrated in the flowchart 402. The process illustrated in the flowchart 402 is not, however, limited to the zero IF FM decoder 502. Upon reading this disclosure, one skilled in the relevant art(s) will recognize that the process illustrated in the flowchart 402 can be practiced by other systems as well.
The zero EF FM decoder 502 includes a first aliasing module 510 and a second aliasing module 512. Preferably, the first and second aliasing modules 510 and 512 are implemented as described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module" and may be optimized as illustrated in FIGS. 1- 3 of the present application and as described above. Other components of the zero IF FM decoder 502 are described below with the description of the process flowchart 402. The process begins at step 410, which includes aliasing an FM signal at an aliasing rate substantially equal to the frequency of the FM signal or substantially equal to a sub harmonic thereof.
In FIG. 5, step 410 is performed by the first and second aliasing module 510 and 512. The first aliasing module 510 receives an FM signal 514 and a first a LO signal 516. The first LO signal 516 is substantially equal to the frequency of the FM signal 514 or a sub-harmonic thereof. Details of maintaining the LO signal 516 at the frequency of the FM signal 514, or a sub-harmonic thereof, is described in connection with step 412 below. The first aliasing module 510 uses the first LO signal 516 to down-convert the FM signal 514 to a first down-converted signal 518, as described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module."
The second aliasing module 512 also receives the FM signal 514 and a second LO signal 520. The first LO signal 516 and the second LO signal 520 are substantially similar except that one is shifted in phase relative to the other. This is performed by, for example, a phase shifter 524. A variety of implementations of the phase shifter 524 suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein.
In an exemplary embodiment, the first and second LO signals 516 and 520 are separated by period of the FM signal 514, or any multiple of a period of the FM signal 514 plus A period. Other phase differences are contemplated and are within the scope of the present invention. The second aliasing module 512 uses the second LO signal 520 to down-convert the FM signal 514 to a second down-converted signal 522, as described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module."
Step 412 includes adjusting the aliasing rate in accordance with frequency changes on the FM signal to maintain the aliasing rate substantially equal to the frequency of the FM signal.
So long as an aliasing rate remains substantially equal to the frequency of an FM signal, the resultant down-converted signal is substantially a constant level. In the case of the zero IF FM decoder 502, therefore, the first and second down-converted signals 518 and 522 should generally be constant signals. In order to maintain this condition, the zero IF FM decoder 502 maintains the phase of the aliasing signal 538 so that the phase of one of the aliasing signals 516 or 520 slightly leads the FM signal 514 while phase of the other aliasing signal slightly lags the FM signal 514.
As a result, one of the down-converted signals 518 or 522 is a constant level above DC while the other down-converted signal is a constant level below DC. The sum of the down-converted signals 518 and 522 is thus substantially zero. Summation of the down- converted signals 518 and 522 is performed by a summing module 526, which outputs a summation signal 536.
When summation signal 536 tends away from zero, it indicates that the frequency of the FM signal 514 is changing. The summation signal 536 is integrated by an integrator module 528, which outputs a control signal 532. The control signal 532 controls a voltage controlled oscillator (VCO) 534, which outputs the aliasing signal 538. The integrator maintains the control signal at a level necessary to insure that the FM signal 514 is aliased at a sub harmonic of the FM signal - even as the FM signal 514 changes frequency. FIG. 7 illustrates, among other things, exemplary implementation details of the summing module 526 and the integrator module 528. A variety of other implementations of the summing module 526 and the integrator module 528, suitable for the present invention, are available, as will be apparent to persons skilled in the relevant art, based on the teachings herein. A variety of implementations of the VCO 534 suitable for the present invention are also available as will be apparent to persons skilled in the relevant art, based on the teachings herein. FIGS. 6A-6D illustrate exemplary timing diagrams for the above description. FIG. 6A illustrates an exemplary FM signal 514. FIG. 6B illustrates a first aliasing signal 612, which is generated within the first aliasing module 510 from the first LO signal 516. FIG. 6C illustrates a second aliasing signal 614, which is generated within the second aliasing module 512 from the second LO signal 520. The first and second aliasing signals 612 and
614 are separated by approximately !/ period of the FM signal 514.
In operation, the first LO signal 612 aliases the FM signal 514 at approximately the same positive position on successive periods. The result is illustrated in FIG. 6D as down- converted signal 518. Similarly, the second LO signal 614 aliases the FM signal 514 at approximately the same negative position on successive periods. The result is illustrated in
FIG. 6D as down-converted signal 522. FIG. 6D illustrates the sum of the down-converted signals 518 and 522 as summation signal 536.
When the frequency of the FM signal 514 changes, summation signal 536 tends away from zero. When this happens, the output of the integrator module 528 - i.e., control signal 532 - changes accordingly so that the VCO 534 changes the aliasing rate of the aliasing signal 538 so that the sum of the down-converted signals 518 and 520, summation signal 536, is maintained at zero. Thus, the control signal 532 changes in proportion to frequency changes on the FM signal 514. The changes on the FM signal 514 form a demodulated baseband information signal, which represents the information that had been frequency modulated on the FM signal 514.
In other words, as the frequency of the FM signal 514 changes, the integrator module 528 changes the control signal 532 to track and follow the deviation. This will reproduce - within the bandwidth of the loop - any arbitrary wave form, including analog and digital. Another way of explaining it is to say that the invention tracks frequency changes on the FM signal by aliasing the FM signal at a sub-harmonic of the FM signal, adjusting the aliasing rate as necessary to maintain the aliasing rate at the sub-harmonic - even as the FM signal changes frequency.
In this way, the aliasing rate changes in proportion to frequency changes on the FM signal. Thus, changes to the aliasing rate are directly indicative of the information modulated on the FM signal. In the exemplary embodiment of FIG. 5, changes to the aliasing rate are indicated by the control voltage 532, which controls the VCO 534, which determines the aliasing rate.
FIG. 6E illustrates an exemplary control signal 532 for controlling the aliasing rate for directly down-converting the exemplary FM signal 514 illustrated in FIG. 6 A to a demodulated baseband information signal. In this example, the control signal 532 has a first amplitude during time Tl, when the FM signal 514 is at a first frequency. The control signal 532 has a second amplitude during time T2, when the FM signal 514 is at a second frequency. The control signal 532 reverts to the first amplitude during time T3, when the FM signal 514 returns to the first frequency. One skilled in the relevant art(s) will recognize, based on the disclosure herein, that the timing diagrams of FIGS. 6A-6E are exemplary illustrations of the invention. Other timing diagrams will apply for different situations, all of which are within the scope of the present invention.
Step 414 includes outputting a demodulated baseband information signal. In FIG. 5, this is performed by outputting the control signal 532 as a demodulated baseband information signal
An optional step 416 includes compensating for phase delays and/or other characteristics of the loop in order to maintain bandwidth and stability for the loop. In FIG. 5, step 416 is performed by an optional loop compensator module 530. FIG. 7 illustrates exemplary implementation details of the loop compensation module 530. A variety of other loop compensation modules suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein.
In an embodiment, a zero IF FM decoder as described above is implemented in an FRS.
Other advantages of the zero IF FM decoder include tuning reduction, parts reduction, price reduction, size reduction, performance increase, low frequency and power
LO, and excellent linearity. Another advantage is that it can down-convert EM signals as high as 3.5 GHz when implemented in CMOS. Higher frequencies can be down- converted using other materials such as GaAs, for example. 3. High-Efficiency Transmitter
This section describes the high-efficiency transmitter embodiment of a frequency up-converter for use in the family radio system. It describes methods and systems related to a transmitter. Structural exemplary embodiments for achieving these methods and systems are also described. It should be understood that the invention is not limited to the particular embodiments described below. Equivalents, extensions, variations, deviations, etc., of the following will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such equivalents, extensions, variations, deviations, etc., are within the scope and spirit of the present invention. The present invention has significant advantages over conventional transmitters.
These advantages include, but are not limited to, a reduction in the number of parts to accomplish the transmitter function, a reduction in the power requirements for the circuit, and a reduction of cost and complexity by permitting the use of circuits designed for lower frequency applications, including, but not limited to, lower frequency oscillators. An embodiment for transmitting a voice signal is shown in FIG. 4. The voice signal is input to a microphone 402. The output of microphone 402 is an analog voice signal 424 which is connected to an audio amplifier 404. The output of audio amplifier 404 is an amplified signal 426 which is filtered by an audio buffer amplifier 406. Audio buffer amplifier 406 acts as a low pass filter to eliminate unwanted higher frequency signals. The output of audio buffer amplifier 406 is a signal 428 which is accepted by crystal oscillator 408. Crystal oscillator 408 operates as a voltage controlled oscillator and outputs a frequency modulated (FM) signal 430 that is a sinusoidal signal biased substantially around zero volts.
At a node 440, a bias voltage 410 combines with FM signal 430. For the implementation wherein bias voltage 410 is a positive voltage, the bias point of FM signal
430 is raised such that substantially the entire waveform is above zero. In an alternate implementation wherein bias voltage 410 is negative, the bias point of FM signal 430 is lowered such that substantially all of the waveform is below zero. This combination of FM signal 430 and bias voltage 410 results in an FM control signal 432. Substantially all of FM control signal 432 is above zero (or below zero if bias voltage 410 is negative). FM control signal 432 is then input to a universal frequency translator (UFT) module 412. UFT module 412 is comprised of a pulse shaping circuit and a switch, and is described in detail below in FIG. 6. The output of UFT module 412 is a rectangular waveform 434 that contains a plurality of harmonics. Rectangular waveform 434 is accepted by a filter 416 which filters out the undesired harmonic frequencies and outputs a desired output signal 436. Desired output signal 436 is the frequency modulated signal at the desired output frequency. Desired output signal 436 goes to a driver 418 and then to a power amplifier 420. The output of power amplifier 420 is an amplified output signal 430. Amplified output signal 430 is ready for transmission and is routed to an antenna 422. The design of UFT module 412 is shown in FIG. 6. FM control signal 432 is accepted by a "square-up" circuit 602 to create a frequency modulated square wave 608 from the sinusoidal waveform of FM control signal 432. FM square wave 608 is then routed to a pulse shaper 604 to create a string of pulses 610. In one embodiment, pulse shaper 604 is a mono-stable multivibrator. The string of pulses 610 operates a switch 606 which creates rectangular waveform 434. Typically, pulse shaper 604 is designed such that each pulse in string of pulses 610 has a pulse width "τ" that is substantially equal to
(n/2)»T, where "T" is the period of desired output signal 436, and "n" is any odd number. As stated previously, switch 606 outputs rectangular waveform 434, which is then routed to filter 416 of FIG. 4. Another input to UFT module 412 is bias signal 414, which, in this embodiment, is connected to the opposite terminal of switch 606 from rectangular waveform 434.
In one implementation of the invention, switch 606 is a field effect transistor (FET). A specific implementation wherein the FET is a complementary metal oxide semiconductor (CMOS) FET is shown is FIG 9. A CMOS FET has three terminals: a gate 902, a source 904, and a drain 906. String of pulses 610 is shown at gate 902, bias signal 414 is shown at source 904, and rectangular waveform 434 is shown at drain 906. Those skilled in the relevant art(s) will appreciate that the source and drain of a FET are interchangeable, and that bias signal 414 could be at the drain 906, with rectangular waveform 434 being at the source 904. Numerous circuit designs are available to eliminate any possible asymmetry, which will be understood by one skilled in the relevant art(s).
FIG. 8 is a detailed schematic drawing of the embodiment described above. Those skilled in the relevant art(s) will appreciated that numerous circuit designs can be used, and that FIG. 8 is shown for illustrative purposes only, and is not limiting. In addition, there are a variety of commercially available components and assemblies suitable for use in the present invention (e.g., audio amplifiers, audio buffer amplifiers, crystal oscillators, drivers, and power amplifiers) as will be apparent to those skilled in the relevant art(s) based on the teachings contained herein.
Microphone 402 of FIG. 4 is shown as a microphone 802. The output of microphone 802 is a voice signal which is routed to an audio amplifier 804 and then to an audio buffer amplifier 806. A crystal oscillator 808 is driven by the output of audio buffer amplifier 806 to create the FM signal 430. A bias voltage 810 combines with FM signal 430 to create the FM control signal 432. FM control signal 432 is routed to a UFT module
812 which creates rectangular signal 434. Also connected to UFT 812 is a bias signal 812. Rectangular signal 434 is filtered by a filter 816 to remove the unwanted harmonics and results in desired output signal 436. Desired output signal 436 goes to a driver 818 and then to a power amplifier 820. The output of power amplifier 820 is amplified output signal 438. Amplified output signal 438 is ready for transmission and is routed to an antenna 822.
In the above implementation, looking back to FIG. 4, the frequency of FM control signal 432 is a sub-harmonic of the frequency of desired output signal 436. It will be understood by those skilled in the relevant art(s) that the selection of the frequencies will have an impact on the amplitude of the desired output signal 436, and will be a determinative factor as to whether or not driver 418 and/or power amplifier 420 will be needed. Similarly, those skilled in the relevant art(s)will understand that the selection of microphone 402 will have an effect on analog voice signal 424, and will be a determinative factor as to whether or not audio amplifier 404 and/or audio buffer amplifier 406 will be needed. Additionally, those skilled in the relevant art(s) will understand that the specific design of UFT 412 will be a determinative factor as to whether or not bias voltage 410 is needed.
The invention described above is for an embodiment wherein the output of the microphone is described as an analog voice signal. Those skilled in the relevant art(s) will understand that the invention applies equally to a digital signal, either digital data or a voice signal that has been digitized. 4. Image-Reject Down-Converter
The present invention is directed toward an image reject mixer using a universal frequency translation (UFT) module. The image reject mixer down-converts an input signal to an intermediate frequency signal, but rejects or attenuates the associated image frequency signal. As compared with conventional mixers, the present invention down- converts an input signal to a lower frequency with lower front-end attention, lower component count, lower cost, and lower overall power requirements when compared with conventional frequency mixers.
Referring to FIGs. 12A-12B, a conventional mixer 1206 generates an intermediate frequency (LF) signal 1210 at frequency (fIF) using a local oscillator (LO) signal 1208 at frequency fL0 and at least one input signal. For a given LO frequency (fL0) and LF frequency (fIF), IF signal 1210 contains a down-converted representation of input signals located at frequencies f,= fL0 + fIF, and f2= fL0 - f[F. FIGs. 12A-12B, illustrate input signal 1202 at frequency (f,) and input signal 1204 at frequency (f2) being down-converted to IF signal 1210 at fIF. For example, if f, is 901 MHz, f, is 899 MHz, and fL0 is 900 MHz, then both the input signal 1202 and input signal 1204 are down-converted to the desired f,F of 1MHz.
Typically, it is desired that the IF signal 1210 contain a down-converted representation of only one of the first or second input signals. Herein, the input signal that is desired to be down-converted is called the desired input signal, and the other input signal is called the undesired input signal. Alternatively, it is desired that the representation of the undesired signal in the IF signal be significantly attenuated compared with the desired signal. For example, if input signals 1202, 1204 represent independent voice messages, then the simultaneous down-conversion of both input signals 1202, 1204 to f1F using a conventional mixer may result in neither message being clearly recovered.
The undesired input signal and it's down-converted representation are often referred to as an image signal. For example, referring to FIG.5B, if it is desired that only the input signal 1202 be represented by the IF signal 1210, then the input signal 1204 may be referred to as the image signal of the desired input signal 1202. Furthermore, f2 is referred to the "image frequency", even when no signal is currently present at this frequency. This illustration is for example only, the input signal 1204 could be chosen as the desired input signal. In which case, input signal 1202 would be the image signal and f, would be the image frequency, as will be understood by those skilled in the arts based on the discussion herein.
FIG. 13A illustrates a block diagram of an image rejection mixer 1301 according to the present invention. Image rejection mixer 1301 down-converts a desired input signal but significantly attenuates the down-conversion of the image input signal. FIG. 13A illustrates an antenna 1304 and a the image reject mixer 1301. Image rejection mixer 1301 comprises: input signal splitter 1308, path 1310, path 1324, and summer 1338. Path 1310 comprises: UFT module 1314, and phase shifter 1318. Path 1324 comprises: phase shifter 1328, UFT module 1326, and gain balance module 1327.
Antenna 1304 receives an input signal 1302. Input signal 1302 may contain a desired input signal FD and an image signal F„ as illustrated by FD 1344 and F, 1346 in FIG. 13B. Preferably, FD and F, are separated by 2fIF, where fIF is the frequency of the IF signal 1342 generated by image reject mixer 1301. The operation of image reject mixer 1301 is as follows. Splitter 1308 receives input signal 1302 from antenna 1304. Splitter 1308 splits the input signal 1302 into two signals that are routed to two paths, path 1310 and path 1324. Preferably, the splitter output signals are approximately equal amplitude and equal phase to each other. A variety of equal-amplitude and equal-phase power splitters are readily available as will be understood by those skilled in the relevant arts. As stated above, input signal 1302 contains a desired signal FD and image signal F,. Therefore, splitter 1308 generates a desired signal FD1 and a image signal F„ that exist at node 1312, and a desired signal FD2 and image signal FI2 that exist at node 1323.
Splitter 1334 receives a control signal Fc 1348. Fc is preferably a sinewave with frequency fc= (fD + f,)/(2-N), where N is an integer (1,2,3....). Splitter 1334 generates control signals Fc, and FC2 at nodes 1332 and 1330, respectively. Splitter 1334 is preferably equal amplitude and equal phase splitter; a variety of which are available as will be apparent to those skilled in the arts based on the discussion herein. FC1 will be used by UFT module 1314 to down-convert FDI and F„, and FC2 will be used by UFT module 1326 to down-convert FD2 and FI2 as will be described below. The down-conversion by UFT modules 1314/1326 is fully described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module." The operation of path 1310 will now be described in detail, after which path 1324 will be described. Finally, summer 1338 will be described.
As illustrated in FIG. 13A, path 1310 contains UFT module 1314 and phase shifter 1318. UFT module 1314 accepts desired signal FD1, image signal F„, and control signal FC1. UFT module 1314 down-converts the FD1 and F„ to the lower intermediate frequency
(f1F). The down-conversion of an input signal to an LF signal is fully described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module." As such, FD, and F„ are down-converted to a lower frequency, f1F.
In an embodiment, the universal frequency translator (UFT) down-converts an input signal. The UFT may down-convert the input signal to an IF signal, or to a demodulated baseband signal. In particular, the rate of a control signal determines whether the input signal is down-converted to an IF signal, or down-converted to a demodulated baseband signal. Other down-conversion options are also possible using the UFT 118. Generally, relationships between the input signal, the rate of the control signal, and the down-converted output signal are illustrated below:
(Freq. of input signal) = N«(Freq. of control signal) ± (Freq. of down-converted output signal)
For the examples contained herein, for illustrative purposes only and without limitation, only the "+" condition will be discussed. The value of N represents a sub- harmonic or harmonic of the input signal (e.g.,N = 0.5, 1, 2, 3, . . . ).
The operation of path 1310 will now be described in detail, after which path 1324 will be described. Finally, summer 1338 will be described.
Phase shifter 1318 receives the down-converted signals FD1 and F,,, and phase shifts FD, and F„ by approximately 90 degrees. A variety of 90 degree phase shifters are readily available as will be apparent to those skilled the relevant arts.
Path 1324 will now be described. As discussed above, Path 1324 comprises UFT module 1326, phase shifter 1328, and gain balance module 1327. Phase shifter 1328 accepts control signal FC2 from splitter 1334. As discussed above, Fc preferably comprises a sinewave with frequency fc= (fD + f,)/(2-N), where N is an integer. For a selected value of N, phase shifter 1328 shifts the phase of control signal FC2 by an amount of 90-M/N degrees, where M is an odd integer (M=l, 3, 5....).
UFT module 1326 accepts desired signal FD2, image signal FI2, and phase shifted control signal FC2. UFT module 1326 down-converts the FD2 and F,2 to the lower intermediate frequency (f1F) using the phase shifted control signal from phase shifter 1328.
As such, FD2 and FI2 are down-converted to a lower frequency, fIF.
Gain Balance module 1327 accepts the down-converted signals FD2 and F,2 and adjusts the power level of FD2 and F,2 such that the power of FD2 and F[2 at node 1337 is approximately equal to that of FD, and F„ at node 1320. This improves the cancellation of F„ and FI2 by summer 1338. In one embodiment, gain balance module is an attenuator with an attenuation that is similar to the attenuation caused by phase shifter 1318. In an alternate embodiment, gain balance module 1327 is an inverter amplifier that can be used change the selected signal that adds in-phase at summer 1338.
The operation of summer 1338 will now be described. Summer 1338 receives down-converted signals FD, and F„ from path 1310, and down-converted signals FD2 and
FI2 from path 1324. Summer 1338 sums these four signal to generate F!F 1342. Because of the relative phase relationship of the four signals, FD1 and FD2 substantially add in-phase, and F„ and FI2 substantially cancel. Therefore, FIF 1342 substantially comprises the desired signal FD, and the undesired image signal F, is substantially attenuated when compared with that of FD.
The relative phase relationships between FD1, FD2, Fn, FI2 will now be described using FIG. 13C. FIG. 13C lists the phase relationship for the above mentioned signals at various nodes in image reject mixer 1301 relative to the phase of FD, at node 1312. This is done for illustrative purposes only, as any phase reference could be chosen. ' At node 1312, FD, and Fπ are shifted by 0 degrees. Likewise at node 1323, FD2 and
Fl2 are phase shifted by 0 degrees. This occurs because splitter 1308 is preferably an equal phase splitter that causes negligible phase shift.
At node 1316, down-converted FD, and down-converted F„ are phase shifted by 0 degrees. At node 1325, down-converted FD2 and down-converted FI2 are phase shifted by - 90 degrees, and +90 degrees, respectively. This occurs because the control signal FC2 is phase shifted by the amount of (90- M/N), where N is associated with the control signal Fc as described above. This phase shifted control signal operates UFT module 1326, which down-converts FD2 and F12 and implements the described phase shift.
At node 1320, down-converted FD, and down-converted F,, are phase shifted by - 90 degrees, and -90 degrees respectively by phase shifter 1318. At node 1337, down-converted FD2 and down-converted FI2 maintain the phase relationship of -90 degrees and +90 degrees.
The reason for the cancellation of down-converted F„ and down-converted FI2 in summer 1338 can now be seen. At node 1320, down-converted F„ has a relative phase shift of -90 degrees. In contrast, down-converted FI2 at node 1337 has a relative phase shift of +90 degrees. Therefore, when down-converted F„ and down-converted FI2 are combined in summer 1338 there is signal cancellation because down-converted F„ and down-converted FI2 are 180 degrees out of phase.
In contrast, summer 1338 combines down-converted FD, and down-converted FD2 in an additive manner because down-converted FD1 at node 1320 and down-converted FD2 at node 1337 have approximately the same relative phase shift of -90 degrees. Therefore,
F,F 1342 substantially contains the down-converted representation of the desired signal FD, only. The level of signal rejection of the image signal F, is theoretically infinite and only limited by component mismatches.
FIGs. 14A-14B illustrate a detailed schematic diagram that further describes one embodiment of image rejection mixer 1301. Splitter 1401 is one embodiment of splitter
1308. UFTs 1402 and 1404 are one embodiment of UFT 1314 and UFT 1326, respectively. In one embodiment, UFT 1402 comprises a CMOS chip 1403, and UFT 1404 comprises a CMOS chip 1405. Signals 1414 and 1416 connect FIGs. 14A and 14B for illustration purposes. Signal 1420 comprises down-converted FD1 and down-converted F„ at node 1316 in FIG. 13 A, and down-converted signal 1422 comprises down-converted
FD2 and down-converted FI2 at node 1325. In one embodiment, amplifier 1410 is included in path 1310, and amplifier 1412 is included in path 1324. Amplifiers 1410 and 1412 are optional to improve the signal strength and are not necessary to practice the present invention. In one embodiment, phase shifter 1318 comprises phase shifter 1414. In one embodiment, gain balance module 1327 comprises gain balance module 1416. 5. Multi-mode and Multi-band Receiver
5.1 Overview of the Multi-mode/Multi-band Receiver
An embodiment of the invention is directed to a receiver having multi-mode and multi-band functionality and capabilities. According to the invention, the receiver is capable of selectively operating over a plurality of bands and channels. In an embodiment, the receiver operates in the following modes: (1) single band/channel mode; or (2) multiple band channel mode.
In the single band/channel mode, the receiver is configured to receive information in a particular channel of a particular frequency band. The receiver may be dynamically reconfigured to listen to other channels and/or other bands.
In the multiple band/channel mode, the receiver is configured to receive information in one or more channels in one or more frequency bands. For example, and without limitation, the receiver could be configured to receive information from a plurality of channels of a single band, or one or more channels of a plurality of bands. A channel in a band that is being monitored (i.e., a channel in a band that the receiver is listening to) is herein referred to as a channel/band combination.
The receiver preferably listens to each channel/band combination for a finite period of time. After the time period of a given channel/band combination expires, the receiver listens to another channel/band combination for a limited amount of time. In an embodiment, the receiver listens to the channel/band combinations in a round robin manner. The receiver listens to each channel/band combination for the same time duration. In other embodiments, the receiver listens to the channel/band combinations in other orders. For example, a user may specify the order in which the channel/band combinations are listened to by the receiver. The user may specify that some channel/band combinations are listened to more often than others. The user may specify that some channel/band combinations are listened to for durations different than the durations associated with other channel/band combinations.
In an embodiment, as shown in FIG. 19, the receiver 1904 is a component of a transceiver 1902. The transceiver 1902 also includes a transmitter 1906. In an embodiment, the transceiver 1902 is an FRS unit that is enabled for multi- mode and multi-band operation, where the bands of operation include bands other than that associated with FRS. It is noted that this FRS embodiment is discussed herein for illustrative purposes only. The invention is not limited to this embodiment. As will be apparent to persons skilled in the relevant art(s) based on the discussion herein, the invention is applicable to other applications of receivers and transceivers.
Transmitters are described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module."
In an embodiment, the receiver is operable at a plurality of frequency bands. For example, the receiver is operable at least all U.S. frequency allocations from 10 KHz to 4
GHz, as illustrated in FIGS. 28A-28C. FIG. 28D illustrates the orientation of FIGS. 28A- 28C. As indicated in FIG. 28D, for illustrative purposes, FIG. 28A partially overlaps with FIG. 28B, which partially overlaps with FIG. 28C. It should be understood that this embodiment is described for illustrative purposes. The invention is not limited to these bands. As will be appreciated by persons skilled in the relevant art(s) based on the discussion herein, embodiments of the invention are applicable at other frequency ranges.
5.2 Structure of the Multi-mode/Multi-band Receiver
FIG. 15 is a block diagram of a receiver 1502 according to an embodiment of the invention. The receiver 1502 includes one or more input filters and/or Z match modules 1506, an input selector 1516, a universal frequency translator 1518, an output selector
1520, one or more output filters 1522, one or more decoders 1532, a control signal generator 1542, and a controller 1544.
In an embodiment, the input filters and/or Z match (impedance match) modules 1506 include filter and/or Z match modules 1508, 1510, 1512, 1514 (four such modules are shown in FIG. 15, but the invention is not limited to this embodiment). Each input filter and/or Z match module 1508, 1510, 1512, 1514 operates to select or pass a frequency band. Accordingly, each input filter and/or Z match module 1508, 1510, 1512, 1514 operates as a band select filter. Preferably, each input filter and/or Z match module 1508, 1510, 1512, 1514 is configured to pass a frequency band of interest. Where necessary, each input filter and/or Z match module 1508, 1510, 1512, 1514 also operates to impedance match the input to downstream circuitry. A variety of filters and Z match modules operable for use with the present invention will be apparent to persons skilled in the relevant art(s) based on the discussion herein. Filters are also described herein in the sections entitled "Down-conversion Using a Universal Frequency
Translation Module" and "Unified Down-conversion and Filtering."
In an alternative embodiment, the receiver 1502 includes a single filter and/or Z match module that is adjustable over a plurality of frequency bands. In another embodiment, the receiver 1502 includes a plurality of filters and/or Z match modules that are adjustable over a plurality of frequency bands. Reference is made to the section included herein entitled "Unified Down-conversion and Filtering."
In an embodiment, the input selector 1516 operates to select one of a plurality of input signals. The selected input signal is passed to an output. In an embodiment, the input selector 1516 includes a switchl 17. The switch 1517 includes a plurality of input nodes and an output node. The switch 1517 connects one of the input nodes to the output node. A variety of switching devices or other types of devices capable of performing the functionality of the input selector 1516 will be apparent to persons skilled in the relevant art(s) based on the discussion herein.
In an embodiment, the universal frequency translator (UFT) 1518 down-converts an input signal 1519. The UFT 1518 may down-convert the input signal 1519 to an IF signal, or to a demodulated baseband signal. In particular, the rate of a control signal 1550 determines whether the input signal 1519 is down-converted to an IF signal, or down- converted to a demodulated baseband signal. Other down-conversion options are also possible using the UFT 1518. Generally, relationships between the input signal 1519, the rate of the control signal 1550, and the down-converted output signal 1521 are illustrated below:
(Freq. of input signal 1519) = «»(Freq. of control signal 1550) ± (Freq. of down-converted output signal 1521) For the examples contained herein, for illustrative purposes only and without limitation, only the "+" condition will be discussed. The value of n represents a harmonic or sub- harmonic of the input signal 1519 (e.g., n = 0.5, 1, 2, 3, . . . ).
The UFT 1518 is further described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module." The control signal generator 1542 generates a control signal 1550. The frequency of the control signal 1550 is adjustable. In an embodiment, the control signal generator 1542 includes a voltage controlled oscillator (VCO). VCO and other types of devices operable for performing the functionality of the control signal generator 1542 will be apparent to persons skilled in the relevant art(s) based on the discussion herein. In embodiments, the control signal generator 1542 may include circuitry to modify characteristics of the control signal 1550, such as adjusting the pulse widths of the control signal 1550. Such aspects are described herein in the section entitled "Down-conversion Using a Universal Frequency Translation Module."
In an embodiment, the output selector 1520 operates to route an input signal to one of a plurality of output nodes. In an embodiment, the output selector 1520 includes a switchl23. The switch 1523 includes an input node and a plurality of output nodes. The switch 1523 connects one of the output nodes to the input node. A variety of switching devices or other types of devices capable of performing the functionality of the output selector 1520 will be apparent to persons skilled in the relevant art(s) based on the discussion herein.
In an embodiment, the output filters 1522 include filters 1524, 1526, 1528, 1530 (four such modules are shown in FIG. 15, but the invention is not limited to this embodiment). Each filter 1524, 1526, 1528, 1530 operates to select or pass a frequency channel. Accordingly, each filter 1524, 1526, 1528, 1530 operates as a channel select filter. Preferably, each filter 1524, 1526, 1528, 1530 is configured to pass a frequency channel of interest. A variety of filters operable for use with the present invention will be apparent to persons skilled in the relevant art(s) based on the discussion herein. Filters are also described herein in the section entitled "Unified Down-conversion and Filtering."
In an alternative embodiment, the receiver 1502 includes a single output filter that is adjustable over a plurality of frequency bands. In another embodiment, the receiver
1502 includes a plurality of output filters modules that are adjustable over a plurality of frequency bands. Reference is made, for example, to the section included herein entitled "Unified Down-conversion and Filtering."
In an embodiment, the receiver 1502 includes decoders 1532. Decoders 1532 preferably include a plurality of decoders 1534, 1536, 1538, 1540 (four such devices are shown in FIG. 15, but the invention is not limited to this example). Decoders 1534, 1536,
1538, 1540 decode an input signal to obtain an output signal 1548. The decoders 1534, 1536, 1538, 1540 are preferably configured to operate with signals of interest. A variety of decoders operable for use with the present invention will be apparent to persons skilled in the relevant art(s) based on the discussion herein. The operation of many if not all of the components of the receiver 1502 is adjustable. Such adjustability is discussed above, and further discussed below. According to an embodiment, a controller 1544 issues commands to the components of the receiver 1502. Such commands control the operation of such components. In an embodiment, the controller 1544 is implemented using a microprocessor and/or a digital signal processor (DSP). The controller 1544 may receive instructions and/or data from users 1546.
The operation of the receiver 1502 shall now be described.
The receiver 1502 receives input signals 1504 over some communication medium. The communication medium may be any communication medium, including but not limited to a wireless medium or a wired medium, or a combination thereof. The input signals 1504 may include information present in a plurality of channels of a plurality of frequency bands. For example, the input signals 1504 may include, without limitation, information present in one or more AM channels, one or more FM channels, one or more CB channels, one or more TV channels, one or more FRS channels, one or more Weatherband channels, local area networks, etc.. The input signals 1504 are received by the input filters and/or Z match modules
1508, 1510, 1512, 1514. Each of the input filters and/or Z match modules 1508, 1510, 1512, 1514 are configured to pass a frequency band of interest. For example, the input filter and/or Z match module 1508 may be configured to pass the AM band. The input filter and/or Z match module 1510 may be configured to pass a band of frequencies associated with a local area network (LAN). The input filter and/or Z match module 1512 may be configured to pass the FRS band. The input filter and/or Z match module 1514 may be configured to pass the Weather band. The input filters and/or Z match modules 1508, 1510, 1512, 1514 pass those input signals 1504 that fall within their respective bands.
The filter and/or Z match modules 1508, 1510, 1512, 1514 generate filtered signals. These filtered signals are received by the input selector 1516. At any instance of time, the input selector 1516 routes one of these filtered signals to the universal frequency translator (UFT) 1518. Switching and routing by the input selector 1516 is controlled by the controller 1544. The filtered signal that is routed to the UFT 1518 corresponds to a channel/band combination that is currently being processed or monitored (this channel/band combination is referred to as the "current channel/band"). The UFT 1518 down-converts the filtered signal that it receives from the input selector 1516 to a lower frequency suitable for down-stream processing. The operation of the UFT 1518 is controlled by the controller 1544. For example, the controller 1544 establishes the frequency of the control signal 1550 generated by the control signal generator 1542, which controls the down-conversion operation performed by the UFT 1518.
The output selector 1520 routes the down-converted signal to an output filter 1522 associated with the current channel/band. Switching and routing performed by the output selector 1520 is controlled by the controller 1544. Assume, for example purposes, that the filter 1526 is associated with the current channel/band. In this case, the output selector 1520 routes the down-converted signal to the filter 1526.
The filter 1526 is configured to pass a channel within the band of the "current channel/band." The channel filtered signal is passed to the decoder 1536 coupled to the filter 1526.
The decoder 1536 decodes the channel filtered signal to obtain the output signal 1548. The output signal 1548 is thereafter processed in an application dependent manner.
FIG. 16 illustrates a receiver 1602 according to an alternative embodiment of the invention. The receiver 1602 includes a unified down-converting and filtering (UDF) module 1606.
The UDF module 1606 performs frequency selectivity and frequency translation as a single unified (i.e., integrated) operation. By performing frequency selectivity and translation as a single unified operation, the invention achieves high frequency selectivity prior to frequency translation. The invention achieves high frequency selectivity at any input frequency (the input frequency refers to the frequency of the input spectrum being filtered and translated), including but not limited to RF (radio frequency) and greater frequencies. It should be understood that the invention is not limited to this example of RF and greater frequencies. The invention is intended, adapted, and capable of working with lower than radio frequencies.
The effect achieved by the UDF module 1606 is to perform the frequency selectivity operation prior to the performance of the frequency translation operation. Thus, the UDF module 1606 effectively performs input filtering.
According to embodiments of the present invention, such input filtering involves a relatively narrow bandwidth. For example, in the embodiment of FIG. 16, such input filtering represents channel select filtering, where the filter bandwidth may be, for example and without limitation, 50 KHz to 150 KHz. It should be understood, however, that the invention is not limited to these frequencies. The invention is intended, adapted, and capable of achieving filter bandwidths of less than and greater than these values. The UDF module 1606 of the present invention includes a number of advantages.
For example, high selectivity at high frequencies is realizable using the UDF module 1606. This feature of the invention is evident by the high Q factors that are attainable. For example, and without limitation, the UDF module 1606 can be designed with a filter center frequency fc on the order of 900 MHz, and a filter bandwidth on the order of 50 KHz. This represents a Q of 18,000, as indicated by the equation
(900 - 106 ) ÷ ( 50 « 103 ) = 18,000 It should be understood that the invention is not limited to filters with high Q factors. The filters contemplated by the present invention may have lesser or greater Qs, depending on the application, design, and/or implementation. Also, the scope of the invention includes filters where Q factor as described herein is not applicable.
The invention exhibits additional advantages. For example, the filtering center frequency fc and other filtering characteristics of the UDF module 1606 can be electrically adjusted, either statically or dynamically.
Also, the frequency translation characteristics of the UDF module 1606 can be electrically adjusted, either statically or dynamically.
Also, the UDF module 1606 can be designed to amplify input signals. Further, the UDF module 1606 can be implemented without large resistors, capacitors, or inductors. Also, the UDF module 1606 does not require that high tolerances be maintained on its individual components, i.e., its resistors, capacitors, inductors, etc. As a result, the architecture of the UDF module 1606 is friendly to integrated circuit design techniques and processes.
The UDF module 1606 operationally replaces the band select filtering, frequency translation, and channel select filtering operations performed by the input filters and/or Z match modules 1506, the UFT 1518, and the output filters 1522 of the receiver 1502 of FIG. 15. The output of the UDF module 1606 is a channel filtered and down-converted signal corresponding to the current channel/band. The filtering and down-conversion characteristics of the UDF module 1606 are adjusted pursuant to the current channel/band (so as to appropriately process the current channel/band) based on commands issued by the controller 1612 to the UDF 1606 and the control signal generator 1610. The channel filtered and down-converted signal generated by the UDF module
1606 is received by decoder(s) 1616. The receiver 1602 may include an output selector (not shown), similar to that described with respect to FIG. 15, to route the channel filtered and down-converted signal to one of the decoders 1616 associated with the current channel/band. Alternatively, the decoders 1616 may represent an adjustable decoder whose operation is controlled by the controller 1612. The decoder then decodes the channel filtered and down-converted signal to produce the output signal 1618. The output signal 1618 is thereafter processed in an application dependent manner.
The UDF module is described in further detail in the section included herein entitled "Unified Down-conversion and Filtering."
5.3 Operation of the Multi-mode/Multi-band Receiver
The operation of the receiver 1904 is further described below. The receiver 1904 may represent either the receiver 1502 of FIG. 15, or the receiver 1602 of FIG. 16. Other embodiments of the receiver 1904 will be apparent to persons skilled in the relevant art(s) based on the discussion herein. For illustrative purposes, and without limitation, the receiver 1904 is considered to be a component of a transceiver 1902. The transceiver 1902 also includes a transmitter 1906. In an embodiment, the transceiver 1902 is an FRS unit enabled for multi-mode and multi-band operation, although the invention is not limited to this embodiment.
5.3.1 Exemplary Scenario Using the Multi-mode/Multi-band Receiver
Consider an exemplary scenario 2002 shown in FIG. 20. A user 2004 has the FRS unit 1902, which is coupled to a computer 2018 via a wireless or wired connection (alternatively, the computer 2018 may be integrated with the FRS unit 1902). The user 2004 is using the FRS unit 1902 to communicate with user 2006 (FCC rules permitting), who may be a family member. User 2006 includes a second FRS unit 2007, and communicates with user 2004 via FRS channel 2024.
The user 2004 also wishes to communicate with user 2020 (FCC rules permitting), who may be another family member. The user 2020 includes a third FRS unit 2022, and communicates with user 2004 via FRS channel 2026. The user 2004 also wishes to receive an FM channel 2030 from FM station 2008, an FM channel 2032 from FM station 2010, a weather channel 2034 from weather station 2012, a TV channel 2036 from TV station 2014, and network communication 2038 from a local area network (LAN) 2016. Such network communication 2038 may be routed to and processed by computer 2018. The invention enables the user 2004 to receive all of these signals (and others) using the FRS unit 1902.
Referring to FIG. 15, the filter and/or Z match modules 1508 and 1510 may be configured for the FM band. The filters 1524 and 1526 may be configured for FM channels 2030 and 2032, respectively. Also, decoders 1534 and 1536 may be configured for FM channels 2030 and 2032, respectively. The filter and/or Z match module 1512 may be configured for the weather band, and filter 1528 and decoder 1538 may be configured for the weather channel 2034. The filter and/or Z match module 1514 may be configured for an appropriate TV band, and the filter 1530 and decoder 1540 may be configured for TV channel 2036. Other filter and/or Z match modules 1506, output filters 1522, and decoders 1532 may be similarly configured for network communication 2038, FRS channel 2026, and FRS channel 2024.
When user 2004 wishes to receive FM channel 2030, the user 2004 can enter an appropriate command(s) into the FRS unit 1902 to cause the FRS unit 1902 to enable and/or adjust the components contained therein for operation with the FM channel 2030.
For example, the input selector 1516 will switch to connect the filter and or Z match module 1508 to the UFT 1518. The output selector 1520 will switch to connect the UFT 1518 to the filter 1524. Also, the control signal generator 1542 will generate a control signal 1550 having a frequency appropriate for down-converting the FM channel 2030. The user 2004 may issue such commands by, for example, pressing keys on a keypad of the FRS unit 1902. Other means for issuing commands are envisioned, such as voice activation.
The user 2004 can easily switch to any of the other sources of information of interest. For example, if the user 2004 wishes to receive the TV channel 2036, the user 2004 can enter an appropriate command into the FRS unit 1902 to cause the FRS unit
1902 to enable and/or adjust the components contained therein for operation with the TV channel 2036. For example, the input selector 1516 will switch to connect the filter and/or Z match module 1514 to the UFT 1518. The output selector 1520 will switch to connect the UFT 1518 to the filter 1530. Also, the control signal generator 1542 will generate a control signal 1550 having a frequency appropriate for down-converting the TV channel
2036. The user 2004 may issue such commands by, for example, pressing keys on a keypad of the FRS unit 1902. Other means for issuing commands are envisioned, such as voice activation.
Other modes of operation are envisioned and are within the scope and spirit of the present invention. For example, in an embodiment, the receiver 1502 (or 1602) has a scan mode. In the scan mode, the controller 1544 automatically scans among the programmed channel/band combinations. Specifically, the components within the FRS unit 1902 are adjusted for operation with a channel/band combination. After some time period, which may be pre-programmed, user programmed, dynamically programmed, random, fixed, etc., the components within the FRS unit 1902 are adjusted for operation with a different channel/band combination. Such scanning operation continues until receipt of some command. It is noted that the scanning mode is not limited to programmed channel/band combinations. The receiver 1502 can be instructed to scan throughout the frequency spectrum in any order and/or increment. Such functionality is achieved, in an embodiment, by taking advantage of the dynamic adjustability of the components of the receiver 1502, as described above. Also during the scan mode, or the multiple band/channel mode, the receiver can be instructed to recognize and act upon particular content. For example, and without limitation, the receiver can be instructed to listen and recognize particular content while monitoring a weather band. Such content may be a storm warning, for example. The receiver can be instructed to act in predefined ways upon receipt and recognition of such content. For example, while monitoring a weather band, if a storm warning is received, then the receiver may be programmed to issue an audible alarm and/or to switch to the weather band until further user command to enable the user to receive weather updates.
Channel/band combinations can be programmed in the receiver 1502. For example, the FM channel 2030 is programmed in the receiver 1502 by adjusting or otherwise establishing the filter and/or Z match 1508 for operation in the FM band, by adjusting or otherwise establishing the filter 1524 and the decoder 1534 for operation with the FM channel 2030, programming the controller 1544 with information sufficient for generating a control signal 1550 (using the control signal generator 1542) having a frequency suitable for down-converting the FM channel 2030, and also programming the controller 1544 with information to control the input selector 1516 and the output selector
1520 when operating with the FM channel 2030.
Channel/band combinations can be pre-programmed, user programmed, downloaded from an information source such as the Internet or a computer, or via any well known programming means. The operation of the FRS unit 1902 is further described below.
5.3.2 Single Band/Channel Operation of the Multi-mode/Multi-band Receiver
The invention supports a variety of modes, as indicated above. Additional modes of operation will be apparent to persons skilled in the relevant art(s) based on the discussion herein. One of the modes supported by the invention is a single band/channel mode. In this mode, the receiver is configured to receive information in a particular channel of a particular frequency band. The receiver may be dynamically reconfigured to listen to other channels and/or other bands. FIG. 17 illustrates a flowchart 1702 that depicts in greater detail the operation of the receiver when in the single band/channel mode. It is noted that the ordering of the steps shown in FIG. 17 is not mandatory. Other orderings of the steps of FIG. 17 are possible and within the scope and spirit of the present invention. Such other orderings will be apparent to persons skilled in the relevant art(s) based on the discussion herein. In step 1704, a band is selected.
In step 1706, a channel within the selected band is selected. The selected channel/band combination represents the channel and band that are to be monitored/received by the receiver. The band and channel can be selected in steps 1704 and 1706 using any of the procedures discussed above, such as having a user enter an appropriate command, during the scan function, due to an interrupt or time-based command, etc..
In step 1708, with respect to the embodiment of FIG. 15, the controller 1544 selects the input filter and/or Z match module 1506, the output filter 1522, and the decoder 1532 that are configured for operation with the selected channel/band. Alternatively, with respect to the embodiment of FIG. 16, the controller 1612 instructs/adjusts the UDF 1606 and selects the decoder 1616 for appropriate operation with the selected channel/band.
In step 1710, the controller 1544/1612 causes the control signal generator 1542/1610 to generate a control signal 1550/1608 having a frequency suitable for down- converting the selected channel/band. Steps 1704- 1710 may be repeated for another channel/band.
5.3.3 Multiple Band/Channel Operation of the Multi-mode/Multi-band Receiver
The receiver also supports a multiple band/channel mode. As noted above, in the multiple band/channel mode, the receiver is configured to receive information in one or more channels in one or more frequency bands. For example, and without limitation, the receiver could be configured to receive information in a plurality of channels of a single band, or one or more channels of a plurality of bands. A channel in a band that is being monitored (i.e., a channel in a band that the receiver is listening to) is herein referred to as a channel/band combination. The receiver preferably listens to each channel/band combination for a finite period of time. After the time period of a given channel/band combination expires, the receiver listens to another channel/band combination for a limited amount of time.
In an embodiment, the receiver listens to the channel/band combinations in a round robin manner. The receiver listens to each channel/band combination for the same time duration. In other embodiments, the receiver listens to the channel/band combinations in other orders. For example, a user may specify the order in which the channel/band combinations are listened to by the receiver. The user may specify that some channel/band combinations are listened to more often than others. The user may specify that some channel/band combinations are listened to for durations different than the durations associated with other channel/band combinations.
FIG. 18 illustrates a flowchart which depicts in greater detail the operation of the receiver when operating in the multiple band/channel mode. In step 1804, one or more bands are selected.
In step 1806, for each of the selected bands, one or more channels are selected. The selected channel/band combinations represent the channels and bands that are to be monitored/received by the receiver. The bands and channels can be selected in steps 1804 and 1806 using any of the procedures discussed above, such as having a user enter appropriate commands, during the scan function, due to an interrupt or time-based command, etc.. As discussed above, in some scan modes, the receiver is instructed to search over the entire frequency spectrum, or a specified portion of the spectrum. In this case, the channel/band combinations represent frequencies in the specified portion of the spectrum.
In step 1808, one of the channel/band combinations is selected for monitoring. In step 1810, with respect to the embodiment of FIG. 15, the controller 1544 selects the input filter and/or Z match module 1506, the output filter 1522, and the decoder
1532 that are configured for operation with the selected channel/band combination. Alternatively, with respect to the embodiment of FIG. 16, the controller 1612 instructs/adjusts the UDF 1606 and selects the decoder 1616 for appropriate operation with the selected channel/band combination.
In step 1812, the controller 1544/1612 causes the control signal generator 1542/1610 to generate a control signal 1550/1608 having a frequency suitable for down- converting the selected channel/band combination.
In step 1814, the selected channel/band combination is monitored.
In step 1816, the controller 1544/1612 determines whether a time duration associated with the selected channel/band combination has expired. The time duration may differ for different channel/band combinations, or may be the same for all. If the time duration has not expired, then the receiver continues to monitor the selected channel/band combination. This is represented by the return to step 1814. If the time duration has expired, then another channel/band combination is selected. This is represented by the return to step 1808.
6. Multi-mode and Multi-band Transmitter
Another embodiment of the present invention is directed toward a multi-mode, multi-band communication system that can transmit and/or receive one or more information signals on one or more transmission frequencies using one or more modulation schemes. The invention described herein is directed to the transmission subsystem of the communications system. According to embodiments of the invention, the up-conversion section is implemented using a universal frequency translator (UFT).
The transmission subsystem is hereafter referred to as the subsystem, and those skilled in the relevant art(s) will appreciate that the subsystem can be integrated with receiver subsystems, such as, and without limitation, the receiver subsystem described herein in the section entitled "Multi-mode and Multi-band Receiver." The block diagram of FIG. 21 illustrates an embodiment of the present invention.
The subsystem is comprised of an information signal conditioning module 2102, a signal selection module 2104, a modulation and frequency selection module 2106, a universal frequency translator (UFT) module 2108, a bias/reference module 2110, a frequency band selection module 2112, an optional output conditioning module 2114, and a control module 2116. The description provided below is for an implementation of the embodiment wherein a single signal is up-converted and transmitted at any time. Those skilled in the relevant art(s) will understand, based on the teachings contained herein, that more than one information signal can be modulated, up-converted, and transmitted simultaneously and be within the spirit and scope of the invention. Looking to the structural diagram of FIG. 21 , it is seen that one or more information signals 2120 are received by information signal conditioning module 2102 and one or more conditioned information signals 2122 are output. The one or more conditioned information signals 2122 are routed to signal selection module 2104. Signal selection module 2104 determines which of the one or more information signals 2120 are to be transmitted at any time. In other words, signal selection module 2104 selects one of the information signals 2120 for transmission. Selected information signal 2124 is output from signal selection module 2104 and routed to modulation and frequency selection module 2106. The purpose of modulation and frequency selection module 2106 is to ensure that the desired modulation scheme and desired output frequency are achieved. Modulation and frequency selection module 2106 outputs an oscillating signal
2126. UFT module 2108 receives oscillating signal 2126 and a bias/reference signal 2128 from bias/reference signal module 2110. The output of UFT module 2108 is a substantially rectangular signal 2130 comprised of a plurality of harmonics. Rectangular signal 2130 is routed to frequency band selection module 2112 which outputs one or more desired output signals 2132 (each of which correspond to one of the harmonics of rectangular signal 2130), which are then routed to optional output conditioning module 2114. An output signal 2134 is generated by optional output conditioning module 2114 and is routed to appropriate transmission devices, such as one or more antennas (not shown). The overall operation of the subsystem is controlled by control module 2116, which outputs a format control signal 2136, a buffer control signal 2138, a signal selection control signal 2140, a modulation control signal 2142, a frequency control signal 2144, a band selection control signal 2146, and a filter control signal 2148. The subsystem will now be described in greater detail. Referring to FIG. 2, it is seen that information signals 2120 are received by information signal conditioning module 2102. For ease of explanation, and not of limitation, it is assumed that any required amplification or filtering of information signals 2120 will have been achieved prior to acceptance by information signal conditioning module 2102. Additionally, information signal conditioning module 2102 receives format control signal 2136 and buffer control signal 2138.
An example of the operation of information signal conditioning module 2102 follows. It is provided for illustrative purposes only, and is not meant to be limiting. A format module 2202a receives an information signal 2120a, and, based on instructions contained in format control signal 2136, converts information signal 2120a from digital to analog, from analog to digital, or allows it to pass unchanged. If this signal is digital, it may be passed to a buffer memory 2204a which also receives buffer control signal 2138. Based on buffer control signal 2138, digital information signal 2120a is either passed directly out of information signal conditioning module 2102 as a conditioned information signal 2122a, or it is temporarily stored in buffer memory 2204a. A condition under which a digital information signal 2120a might be stored in buffer memory 2204a is when another information signal (e.g., information signal 2120b) is being modulated, up- converted, and transmitted. In this manner, multiple information signals can be transmitted sequentially with minimal loss of information. If the signal is analog, it will pass directly out of information signal conditioning module 2102 as conditioned information signal 2122a.
Signal selection module 2104 receives conditioned information signals 2122 and signal selection control signal 2140. Based on the control given, signal selection module
2104 selects which conditioned information signal 2122 is to be output as selected information signal 2124. The operation of signal selection module 2104 underscores the highly integrated nature of control module 2116. As an example, signal selection module 2104 should not select a conditioned information signal 2122 that is being stored in buffer memory 2204, until that signal is ready to be transferred.
Those skilled in the relevant art(s) will understand that the functions performed by information signal conditioning module 2102 are not required elements in the invention. For example, if information signals 2120 are all in the proper format (i.e., no A-to-D or D- to-A conversion is required), and there is no requirement for them to be buffered (e.g., they are all analog), signal selection module 2104 will receive information signals 2120 directly. Similarly, depending on system requirements, format modules 2202 may be eliminated while retaining buffer memories 2204 (i.e., the signals are already in a desired digital format), or buffer memories 2204 may be eliminated while retaining format modules 2202. Both the inclusion or elimination of any of the functions performed by the information signal conditioning module 2102 is within the spirit and scope of the invention. FIG. 23 illustrates an exemplary structure of modulation and frequency selection module 2106 and of bias/reference signal module 2110. Modulation and frequency selection module 2106 is preferably comprised of a modulation selector 2306, an oscillating signal generator 2308, and a frequency selector 2330. Bias/reference signal module 2110 is preferably comprised of a summer 2310 and an impedance 2312. Selected information signal 2124 is received by modulation selector 2306. The operation of modulation selector 2306 is controlled by modulation control signal 2142. The purpose of modulation selector 2306 is to effect the proper modulation of selected information signal 2124. Thus, a switch 2314 is coupled to a contact 2318 when amplitude modulation (AM) is desired, to a contact 2320 when phase modulation (PM) is desired, and to a contact 2322 when frequency modulation (FM) is desired. For ease of illustration and not limiting, only single modulation is discussed herein. However, those skilled in the relevant art(s) will understand, based on the teachings contained herein, that more elaborate, multiple modulation schemes, such as, and without limitation, In- phase/Quadrature-phase ("I Q") modulation, quadrature amplitude modulation (QAM), AM on angle modulation (i.e., FM or PM), etc., are covered by the spirit and scope of the invention.
When AM is desired, switch 2314 is coupled to contact 2318, and selected information signal 2124 is routed to bias/reference signal module 2110 where it is summed with a bias signal 2338 by summer 2310. To avoid bias/reference signall28 being shorted directly to ground, impedance 2312 is placed in series between the source of bias/reference signal 2128 and UFT module 2108.
When PM is desired, switch 2314 is coupled to contact 2320, and selected information signal 2124 is routed to oscillating signal generator 2308. Selected information signal 2124 is then coupled to a phase modulator 2326. Similarly, when FM is desired, switch 2314 is coupled to contact 2322, and selected information signal 2124 is routed to oscillating signal generator 2308 where it is coupled to a frequency modulator 2328. The operation of frequency selector 2330 is controlled by frequency control signal 2144. Frequency selector 2330 controls the operation of frequency modulator 2328, phase modulator 2326, and an oscillator 2324 such that the frequency of oscillating signal 2126 is a desired sub-harmonic of the frequency of desired output signal 2134. Oscillating signal generator 2308 also includes a switch 2316 that is ganged together with switch 2314 such that when switch 2314 is coupled to contact 2318 (for AM), switch 2316 is coupled to contact 2332. Thus, for AM, oscillating signal 2126 is an unmodulated oscillating signal having a frequency that is a sub-harmonic of the frequency of the desired output signal 2134, and bias/reference signal 2128 is a function of selected information signal 2124.
Similarly, when switch 2314 is coupled with contact 2320 (for PM), switch 2316 is coupled to contact 2334, and oscillating signal 2126 is the output of phase modulator 2326 and is a phase modulated oscillating signal having a frequency that is a sub-harmonic of the frequency of the desired output signal 2134. For PM, bias/reference signal 2128 is comprised of bias signal 2338.
When FM is desired, switch 2314 is coupled to contact 2322 and switch 2316 is coupled to contact 2336. Thus, oscillating signal 2126 is the output of frequency modulator 2326 and is a frequency modulated oscillating signal having a frequency that is a sub-harmonic of the frequency of the desired output signal 2134. For FM, bias/reference signal 2128 is comprised of bias signal 2338.
Those skilled in the relevant art(s) will understand, based on the teachings contained herein, that if additional modulation schemes are desired, they may be added.
In addition, those skilled in the relevant art(s) will understand, based on the teachings contained herein, that if the intended operation of a communication system in general, and the transmitter subsystem in particular, is not intended to include one or more modulation schemes described above, then modulation and frequency selection module 2106 and bias/reference signal module 2110 can be designed without the unneeded circuits. As an example of an alternative implementation, if the subsystem is to be used only to transmit FM signals, modulation selector 2306, summer 2310, oscillator 2324, phase modulator 2326, switch 2316, and contacts 2332, 2334, 2336, as well as modulation control signal 2142 can be eliminated. In this alternative implementation, selected information signal 2124 is routed directly to frequency modulator 2328, the output of which is oscillating signal 2126. Note that frequency modulator 2328 is still controlled by frequency control signal 2144.
Those skilled in the relevant art(s) will recognize that alternative circuit designs exist that will accomplish the intent of the above descriptions, and fall within the scope and spirit of the invention.
The output of modulation and frequency selection module 2106 is oscillating signal 2126, which is routed to UFT module 2108. An exemplary structure of UFT 2108 is seen in FIG. 24. UFT module 2108 is preferably comprised of a square wave generator 2402, a pulse shaper 2404, and a switch 2406. The use of UFT module 2108 as a transmitter is further described herein in the section entitled "Frequency Up-conversion."
FIG. 24 illustrates oscillating signal 2126 being accepted by square wave generator 2402 to create a square wave 2408 from the periodic waveform of oscillating signal 2126. Square wave generators useful for operation with the invention are well known. Square wave 2408 has substantially the same frequency and modulation (if any) as does oscillating signal 2126. Square wave 2408 is then routed to pulse shaper 2404 to create a string of pulses 2410. In one embodiment, string of pulses 2410 has substantially the same frequency and modulation (if any) as does oscillating signal 2126. In one implementation, pulse shaper 2404 is a mono-stable multi-vibrator. In an alternate embodiment, the frequency of string of pulses 2410 is not the same as the frequency of oscillating signal 2126. The string of pulses 2410 controls switch 2406 to create rectangular signal 2130.
Preferably, pulse shaper 2404 is designed such that each pulse in string of pulses 2410 has a pulse width "τ" that is substantially equal to (n/2)»T, where "T" is the period of desired output signal 2134, and "n" is any odd number.
Another input to UFT module 2108 is bias/reference signal 2128, which, in this embodiment, is connected to the opposite terminal of switch 2406 from rectangular signal
2130. When string of pulses 2410 controls switch 2406 (i.e., causes switch 2406 to close and open), bias/reference signal 2128 is gated to a second potential (e.g., ground, not shown), thereby creating rectangular signal 2130.
In one implementation of the invention, switch 2406 is a field effect transistor (FET). A specific implementation wherein the FET is a complementary metal oxide semiconductor (CMOS) FET is shown in FIG 25. A CMOS FET has three terminals: a gate 2502, a source 2504, and a drain 2506. String of pulses 2410 is connected to gate 2502, bias/reference signal 2128 is connected to source 2504, and rectangular signal 2130 is connected to drain 2506. Those skilled in the relevant art(s) will appreciate that the source and drain of a FET are interchangeable, and that bias/reference signal 2128 could be at drain 2506, with rectangular waveform 2130 being at source 2504. The output of UFT module 2108 is rectangular signal 2130 that contains a plurality of harmonics. Rectangular signal 2130 is sometimes referred to as a harmonically rich signal. Rectangular signal 2130 is accepted by frequency band selection module 2112 which filters out any undesired harmonic frequencies and outputs desired output signals 2132 which are the harmonics of rectangular signal 2130 that were not filtered out by frequency band selection module 2112. Desired output signals 2132 are modulated signals at the desired output frequency.
An exemplary structure for frequency band selection module 2112 is shown in FIG. 26. Rectangular signal 2130 is received by frequency band selection module 2112. To accommodate the wide range of possible output frequencies for output signal 2134 (for example, and not meant to be limiting, output signal 2134 may have frequencies ranging from 10 KHz to 3.5 GHz), a frequency band selector 2606 and a parallel network of filter circuits 2618 are shown. It will be apparent to those skilled in the relevant art(s), based on the teachings contained herein, that it would be within the spirit and scope of the invention if the desired output frequency range were to be accommodated by a single filter circuit. In the implementation shown here, frequency band selection module 2112 is comprised of a frequency band selector 2606 and one or more filter circuits 2618. Frequency band selector 2606 is further comprised of a switch 2608 and one or more contacts 2610. The purpose of frequency band selection module 2112 is to accommodate the wide range of possible output frequencies for output signal 2134. Those skilled in the relevant art(s) will understand, based on the teachings contained herein, that the exact number of filter circuits 2618 will depend, mter alia, on the actual desired frequency range of output signal 2134 and the components and design of each filter.
In an exemplary scenario, frequency band selector 2606, being controlled by band selection control signal 2146, will, for example, be coupled to contact 2610a for desired output frequencies between 10 KHz and 100 KHz (referred to herein as "Band 1"), coupled to contact 2610b for desired output frequencies between 100 KHz and 10 MHz (referred to herein as "Band 2"), coupled to contact 2610c for desired output frequencies between 10 MHz and 500 MHz (referred to herein as "Band 3"), and coupled to contact 2610m for desired output frequencies above 1 GHz (referred to herein as "Band m"). These examples are provided for illustrative purposes only, and are not meant to be limiting. Each band is then filtered by its respective filter circuit. That is, "Band 1" is filtered by filter circuit 2618a, "Band 2"is filtered by filter circuit 2618b, "Band 3"is filtered by filter circuit 2618c, and "Band m"is filtered by filter circuit 2618m. In this manner, part selection and design of filter circuits 2618 can be substantially tailored for their respective frequency band.
Filter circuits 2618 are controlled by filter control signal 2148 to specifically tune each filter for the specific output frequency. In the example above, if the desired output frequency is 467.6125 MHz (i.e., channel 10 of the Family Radio Service), switch 2608 would couple with contact 2610c, and filter circuit 2618c would respond to filter control signal 2148 to tune its components to band pass only the desired frequency. This example is provided for illustrative purposes only, and is not meant to be limiting. The outputs of filter circuits 2618 are desired output signals 2132. Desired output signals 2132 are then routed to optional output conditioning module 2114, an embodiment of which is shown in FIG. 27. Optional output condition module 2114 is preferably comprised of one or more drivers 2702 and one or more power amplifiers 2704. Those skilled in the relevant art(s) will understand, based on the teachings contained herein, that the requirement for drivers 2702 and/or power amplifiers 2704 is dependent on a number of factors. In the above implementation, the frequency of oscillating signal 2126 is a sub- harmonic of the frequency of desired output signal 2132. It will be understood by those skilled in the relevant art(s) that the selection of the frequencies will have an impact on the amplitude of the desired output signal 2132, and will be a determinative factor as to whether or not drivers 2702 and/or power amplifiers 2704 will be needed. A more thorough discussion of this is described herein in the section entitled "Frequency Up- conversion."
The output of power amplifiers 2704 is output signal 2134. Output signal 2134 is then routed to appropriate transmission devices, such as one or more antennas (not shown). 7. Down-conversion Using a Universal Frequency Translation Module.
The following discussion describes down-converting using a Universal Frequency Translation Module. An aliasing module for down-conversion uses a universal frequency translation (UFT) module which down-converts an EM input signal In particular embodiments, the aliasing module includes a switch and a capacitor The electronic alignment of the circuit components is flexible. That is, in one implementation, the switch is in series with the input signal and the capacitor is shunted to ground (although it may be other than ground in configurations such as differential mode). In a second implementation, the capacitor is in series with the input signal and the switch is shunted to ground (although it may be other than ground in configurations such as differential mode).
The aliasing module with the UFT module can be easily tailored to down-convert a wide variety of electromagnetic signals using aliasing frequencies that are well below the frequencies of the EM input signal.
In one implementation, the aliasing module down-converts the input signal to an intermediate frequency (IF) signal. In another implementation, the aliasing module down- converts the input signal to a demodulated baseband signal. In yet another implementation, the input signal is a frequency modulated (FM) signal, and the aliasing module down-converts it to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal. Each of the above implementations is described below.
In an embodiment, the control signal includes a train of pulses that repeat at an aliasing rate that is equal to, or less than, twice the frequency of the input signal In this embodiment, the control signal is referred to herein as an aliasing signal because it is below the Nyquist rate for the frequency of the input signal. Preferably, the frequency of control signal is much less than the input signal 6404.
The train of pulses controls the switch to alias the input signal with the control signal to generate a down-converted output signal. More specifically, in an embodiment, the switch closes on a first edge of each pulse and opens on a second edge of each pulse. When the switch is closed, the input signal is coupled to the capacitor, and charge is transferred from the input signal to the capacitor. The charge stored during successive pulses forms down-converted output signal. It should be noted that the pulse aperture may also be referred to as the pulse width as will be understood by those skilled in the art(s). The pulses repeat at an aliasing rate, or pulse repetition rate of the aliasing signal. The aliasing rate is determined as described below. As noted above, the train of pulses (i.e., the control signal) control the switch to alias the analog AM carrier signal (i.e., the input signal) at the aliasing rate of the aliasing signal. Specifically, in this embodiment, the switch closes on a first edge of each pulse and opens on a second edge of each pulse. When the switch is closed, the input signal is coupled to the capacitor, and charge is transferred from the input signal to the capacitor. The charge transferred during a pulse is referred to herein as an under-sample. Exemplary under-samples form the down-converted signal portion that coπesponds to the analog AM carrier signal portion and the train of pulses. The charge stored during successive under- samples of the AM carrier signal form the down-converted signal that is an example of the down-converted output signal. The aliasing rate of the control signal determines whether the input signal is down- converted to an IF signal, down-converted to a demodulated baseband signal, or down- converted from an FM signal to a PM or an AM signal. Generally, relationships between the input signal, the aliasing rate of the control signal, and the down-converted output signal are illustrated below:
(Freq. of input signal) = «»(Freq. of control signal) ±
(Freq. of down-converted output signal)
For the examples contained herein, only the "+" condition will be discussed. The value of n represents a harmonic or sub-harmonic of the input signal (e.g., n = 0.5, 1, 2, 3, . . . ). When the aliasing rate of the control signal is off-set from the frequency of the input signal, or off-set from a harmonic or sub-harmonic thereof, the input signal is down- converted to an IF signal. This is because the under-sampling pulses occur at different phases of subsequent cycles of the input signal. As a result, the under-samples form a lower frequency oscillating pattern. If the input signal includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the down-converted IF signal. For example, to down-convert a 901 MHz input signal to a 1 MHz IF signal, the frequency of the control signal 6406 would be calculated as follows:
(Freqjnput - Freq1F)/« = FreqcoMrol (901 MHz - 1 MHz)/« = 900/n
For n = 0.5, 1, 2, 3, 4, etc., the frequency of the control signal would be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc.
Alternatively, when the aliasing rate of the control signal is substantially equal to the frequency of the input signal, or substantially equal to a harmonic or sub-harmonic thereof, the input signal is directly down-converted to a demodulated baseband signal.
This is because, without modulation, the under-sampling pulses occur at the same point of subsequent cycles of the input signal. As a result, the under-samples form a constant output baseband signal. If the input signal includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the demodulated baseband signal. For example, to directly down-convert a 900 MHz input signal to a demodulated baseband signal (i.e., zero IF), the frequency of the control signal would be calculated as follows:
(Freqinput - FreqIF)/« = Freqcontrol (900 MHz - 0 MHz)//7 = 900 MHz/«
For n = 0.5, 1, 2, 3, 4, etc., the frequency of the control signal 6406 should be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc.
Alternatively, to down-convert an input FM signal to a non-FM signal, a frequency within the FM bandwidth must be down-converted to baseband (i.e., zero IF). As an example, to down-convert a frequency shift keying (FSK) signal (a sub-set of FM) to a phase shift keying (PSK) signal (a subset of PM), the mid-point between a lower frequency F, and an upper frequency F2 (that is, [(F, + F2) ÷ 2]) of the FSK signal is down- converted to zero IF. For example, to down-convert an FSK signal having F, equal to 899 MHz and F2 equal to 901 MHz, to a PSK signal, the aliasing rate of the control signal would be calculated as follows:
Frequency of the input = (F, + F2) ÷ 2
= (899 MHz + 901 MHz) ÷ 2 = 900 MHz
Frequency of the down-converted signal = 0 (i.e., baseband)
(Freqinput - FreqIF)/n = Freqcomro, (900 MHz - 0 MHz)/« = 900 MHz/«
For n = 0.5, 1, 2, 3, etc., the frequency of the control signal 6406 should be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc. The frequency of the down-converted PSK signal is substantially equal to one half the difference between the lower frequency F, and the upper frequency F2.
As another example, to down-convert a FSK signal to an amplitude shift keying
(ASK) signal (a subset of AM), either the lower frequency F, or the upper frequency F2 of the FSK signal is down-converted to zero IF. For example, to down-convert an FSK signal having F, equal to 900 MHz and F2 equal to 901 MHz, to an ASK signal, the aliasing rate of the control signal should be substantially equal to:
(900 MHz - 0 MHz)/« = 900 MHz/n, or (901 MHz - 0 MHz)/« = 901 MHz/n.
For the former case of 900 MHz/«, and for n = 0.5, 1, 2, 3, 4, etc., the frequency of the control signal 6406 should be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc. For the latter case of 901 MHz/n, and for n = 0.5, 1, 2, 3, 4, etc., the frequency of the control signal 6406 should be substantially equal to 1.802 GHz, 901 MHz, 450.5 MHz, 300.333 MHz, 225.25 MHz, etc. The frequency of the down-converted AM signal is substantially equal to the difference between the lower frequency F, and the upper frequency F2 (i.e., 1 MHz). In an embodiment, the pulses of the control signal have negligible apertures that tend towards zero. This makes the UFT module a high input impedance device. This configuration is useful for situations where minimal disturbance of the input signal may be desired. In another embodiment, the pulses of the control signal have non-negligible apertures that tend away from zero. This makes the UFT module a lower input impedance device. This allows the lower input impedance of the UFT module to be substantially matched with a source impedance of the input signal. This also improves the energy transfer from the input signal to the down-converted output signal, and hence the efficiency and signal to noise (s/n) ratio of UFT module.
When the pulses of the control signal have non-negligible apertures, the aliasing module is refeπed to interchangeably herein as an energy transfer module or a gated transfer module, and the control signal is referred to as an energy transfer signal. Exemplary systems and methods for generating and optimizing the control signal and for otherwise improving energy transfer and/or signal to noise ratio in an energy transfer module are described below.
7.1 Optional Energy Transfer Signal Module
An energy transfer system that includes an optional energy transfer signal module which can perform any of a variety of functions or combinations of functions including, but not limited to, generating an energy transfer signal.
In an embodiment, the optional energy transfer signal module includes an aperture generator. The aperture generator generates non-negligible aperture pulses from an input signal. The input signal can be any type of periodic signal, including, but not limited to, a sinusoid, a square wave, a saw-tooth wave, etc. Systems for generating the input signal are described below.
The width or aperture of the pulses is determined by delay through a branch of the aperture generator. Generally, as the desired pulse width increases, the difficulty in meeting the requirements of the aperture generator decrease. In other words, to generate non-negligible aperture pulses for a given EM input frequency, the components used in the exemplary aperture generator do not require as fast reaction times as those that are required in an under-sampling system operating with the same EM input frequency.
The exemplary logic and implementation of the aperture generator are described for illustrative purposes only, and are not limiting. The actual logic employed can take many forms. The exemplary aperture generator includes an optional inverter, which is shown for polarity consistency with other examples provided herein.
In an embodiment, the input signal is generated externally of the optional energy transfer signal module. Alternatively, the input signal is generated internally by the optional energy transfer signal module. The input signal can be generated by an oscillator. The oscillator can be internal to the optional energy transfer signal module or external to the optional energy transfer signal module. The oscillator can be external to the energy transfer system. The output of the oscillator may be any periodic waveform.
The type of down-conversion performed by the energy transfer system depends upon the aliasing rate of the energy transfer signal, which is determined by the frequency of the pulses. The frequency of the pulses is determined by the frequency of the input signal. For example, when the frequency of the input signal is substantially equal to a harmonic or a sub-harmonic of the EM signal, the EM signal is directly down-converted to baseband (e.g. when EM signal is an AM signal or a PM signal), or converted from FM to a non-FM signal. When the frequency of the input signal is substantially equal to a harmonic or a sub-harmonic of a difference frequency, the EM signal is down-converted to an intermediate signal.
The optional energy transfer signal module can be implemented in hardware, software, firmware, or any combination thereof.
The down-converted output signal may be smoothed by filtering as desired.
7.2 Impedance Matching
The energy transfer module has input and output impedances generally defined by (1) the duty cycle of the switch module (i.e., the UFT module), and (2) the impedance of the storage module (e.g., the capacitor), at the frequencies of interest (e.g. at the EM input, and intermediate/baseband frequencies). Starting with an aperture width of approximately one-half of the period of the EM signal being down-converted as a prefeπed embodiment, this aperture width (e.g. the "closed time") can be decreased. As the aperture width is decreased, the characteristic impedance at the input and the output of the energy transfer module increases. Alternatively, as the aperture width increases from one-half of the period of the EM signal being down-converted, the impedance of the energy transfer module decreases.
One of the steps in determining the characteristic input impedance of the energy transfer module could be to measure its value. In an embodiment, the energy transfer module's characteristic input impedance is 300 ohms. An impedance matching circuit can be used to efficiently couple an input EM signal that has a source impedance of, for example, 50 ohms, with the energy transfer module's impedance of, for example, 300 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary impedance directly or the use of an impedance match circuit as described below. An impedance matched aliasing module may comprise an input impedance match module, an aliasing module, and an output impedance match module. By way of example, and not meant to be limiting, assuming that an impedance is, for example, a relatively low impedance of approximately 50 Ohms, and an input impedance is, for example, approximately 300 Ohms, an initial configuration for the input impedance match module can be configured to include an inductor and a capacitor. The configuration of the inductor and the capacitor in an "L network" is a possible configuration when going from a low impedance to a high impedance. The calculation of the values for the inductor and the capacitor is well known to those skilled in the relevant arts.
The output characteristic impedance can be impedance matched to take into consideration the desired output frequencies. One of the steps in determining the characteristic output impedance of the energy transfer module could be to measure its value. Balancing the very low impedance of the storage module at the input EM frequency, the storage module should have an impedance at the desired output frequencies that is preferably greater than or equal to the load that is intended to be driven (for example, in an embodiment, storage module impedance at a desired 1MHz output frequency is 2K ohm and the desired load to be driven is 50 ohms). An additional benefit of impedance matching is that filtering of unwanted signals can also be accomplished with the same components.
In an embodiment, the energy transfer module's characteristic output impedance is, for example, 2K ohms. An impedance matching circuit can be used to efficiently couple the down-converted signal with an output impedance of, for example, 2K ohms, to a load of, for example, 50 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary load impedance directly or the use of an impedance match circuit as described below.
When matching from a high impedance to a low impedance, a capacitor and an inductor can be configured in an "L network" matched filter. The calculation of the values for the capacitor and the inductor is well known to those skilled in the relevant arts.
The configuration of the input impedance match module and the output impedance match module are considered to be initial starting points for impedance matching, in accordance with the present invention. In some situations, the initial designs may be suitable without further optimization. In other situations, the initial designs can be optimized in accordance with other various design criteria and considerations.
As other optional optimizing structures and/or components are used, their affect on the characteristic impedance of the energy transfer module should be taken into account in the match along with their own original criteria.
7.3 Tanks and Resonant Structures
Resonant tank and other resonant structures can be used to further optimize the energy transfer characteristics of the invention. For example, resonant structures, resonant about the input frequency, can be used to store energy from the input signal when the switch is open, a period during which one may conclude that the architecture would otherwise be limited in its maximum possible efficiency. Resonant tank and other resonant structures can include, but are not limited to, surface acoustic wave (SAW) filters, dielectric resonators, diplexers, capacitors, inductors, etc.
An exemplary embodiment may comprise parallel tank circuits in a differential implementation. A first parallel resonant or tank circuit (tankl) consists of a capacitor and an inductor. A second tank circuit (tank2) also consists of a capacitor and an inductor. As is understood by one skilled in the relevant art(s), parallel tank circuits provide: low impedance to frequencies below resonance; low impedance to frequencies above resonance; and high impedance to frequencies at and near resonance. As an example, the first and second tank circuits may resonate at approximately
920 MHz. At and near resonance, the impedance of these circuits is relatively high. Therefore, both tank circuits appear as relatively high impedance to the input frequency of 950 MHz, while simultaneously appearing as relatively low impedance to frequencies in the desired output range of 50 MHz. An energy transfer signal controls a switch. When the energy transfer signal causes the switch to open and close, high frequency signal components will not pass through tankl or tank2. However, the lower signal components (50MHz in this embodiment) generated by the system will pass through tankl and tank2 with little attenuation. The effect of tankl and tank2 is to further separate the input and output signals from the same node, thereby producing a more stable input and output impedance.
The capacitors act to store the 50 MHz output signal energy between energy transfer pulses.
Further energy transfer optimization is provided by placing an inductor in series with a storage capacitor. In an example, the series resonant frequency of a circuit aπangement is approximately 1 GHz. This circuit increases the energy transfer characteristic of the system. The ratio of the impedance of the inductor and the impedance of the storage capacitor is preferably kept relatively small so that the majority of the energy available will be transferred to the storage capacitor during operation. The various resonant tanks and structures discussed can be combined or used independently as is now apparent.
7.4 Charge and Power Transfer Concepts
Concepts of charge transfer are now described. A circuit, may include a switch S and a capacitor having a capacitance "C." The switch S is controlled by a control signal , which includes pulses having apertures of duration "T." In FIG. 29, Equation 1 illustrates that the charge "q" on a capacitor having a capacitance "C," is proportional to the voltage "V across the capacitor, where: q = Charge in Coulombs C = Capacitance in Farads V = Voltage in Volts
Where the voltage "V is represented by Equation 2 and where A = Input Signal Amplitude, Equation 1 can be rewritten as Equation 3. The change in charge over time is illustrated as "Δq(t)"in Equation 4, which can be rewritten as Equation 5. Using the trigonometric identity of Equation 6, Equation 5 becomes Equation 7, which can be rewritten as
Equation 8.
Note that the sine term in Equation 8 is a function of the aperture "T" only. Thus, "Δq(t)" is at a maximum when "T" is equal to an odd multiple of π (i.e., π, 3π, 5π, . . . ). Therefore, the capacitor experiences the greatest change in charge when the aperture "T" has a value of π or a time interval representative of 180 degrees of the input sinusoid.
Conversely, when "T" is equal to 2π, 4π, 6π, . . ., minimal charge is transferred.
Equations 9, 10, and 11 solve for "q(t)" by integrating Equation 1, allowing the charge on the capacitor with respect to time to be graphed on the same axis as the input sinusoid, "sin(t)," as illustrated in the graph of FIG. 30. As the aperture "T" decreases in value or tends toward an impulse, the phase between the charge on the capacitor "C" (or
"q(t)") and "sin(t)" tend toward zero. This is illustrated in the graph of FIG. 31, which indicates that the maximum impulse charge transfer occurs near the input voltage maxima. As this graph indicates, considerably less charge is transfened as the value of "T" decreases. Power/charge relationships are illustrated in Equations 12-17 of FIG. 32, where it is shown that power is proportional to charge, and transfened charge is inversely proportional to insertion loss.
Concepts of insertion loss are illustrated in FIG. 33. Generally, the noise figure of a lossy passive device is numerically equal to the device insertion loss. Alternatively, the noise figure for any device cannot be less that its insertion loss. Insertion loss can be expressed by Equation 18 or 19. From the above discussion, it is observed that as the aperture "T" increases, more charge is transferred from the input to the capacitor, which increases power transfer from the input to the output. It has been observed that it is not necessary to accurately reproduce the input voltage at the output because relative modulated amplitude and phase information is retained in the transfened power.
7.5 Optimizing and Adjusting the Non-Negligible Aperture Width/Duration
7.5.1 Varying the Input and Output Impedances
In an embodiment of the invention, the energy transfer signal is used to vary the input impedance seen by the EM Signal and to vary the output impedance driving a load. An example of this embodiment is described below using a gated transfer module. The method described below is not limited to a gated transfer module.
When a switch is closed, the impedance looking into the circuit is substantially the impedance of a storage module, such as a storage capacitance, in parallel with the impedance of a load. When the switch is open, the impedance approaches infinity. It follows that the average impedance can be varied from the impedance of the storage module illustrated in parallel with load, to the highest obtainable impedance when switch is open, by varying the ratio of the time that the switch is open to the time the switch is closed. The switch is controlled by an energy transfer signal. Thus the impedance can be varied by controlling the aperture width of the energy transfer signal in conjunction with the aliasing rate.
An exemplary method of altering the energy transfer signal is now described, wherein a circuit receives an input oscillating signal and outputs a pulse train that is a doubler output signal. The circuit can be used to generate an energy transfer signal.
It can be shown that by varying the delay of the signal propagated by an inverter , the width of the pulses in the doubler output signal can be varied. Increasing the delay of the signal propagated by the inverter, increases the width of the pulses. The signal propagated by the inverter can be delayed by introducing a R/C low pass network in the output of the inverter. Other means of altering the delay of the signal propagated by the inverter will be well known to those skilled in the art. 7.5.2 Real Time Aperture Control
In an embodiment, the aperture width/duration is adjusted in real time. For example, a clock signal may be used to generate an energy transfer signal, which includes energy transfer pluses having variable apertures. In an embodiment, the clock signal is inverted. The clock signal may also be delayed. The inverted clock signal and the delayed clock signal are then combined by an AND gate, generating the energy transfer signal, which is "high" when the delayed clock signal and the inverted clock signal are both "high." The amount of delay imparted to the delayed clock signal substantially determines the width or duration of the variable apertures. By varying the delay in real time, the apertures are adjusted in real time.
In an alternative implementation, the inverted clock signal is delayed relative to the clock signal, and then combined with the clock signal by an AND gate. Alternatively, the clock signal may be delayed and then inverted. The result is then combined with the clock signal by an AND gate. A real time aperture control system may comprise includes an RC circuit, which includes a voltage variable capacitor and a resistor. A real time aperture control system may also include an inverter and an AND gate. Optionally, the AND gate includes an optional enable input for enabling/disabling the AND gate. A real time aperture control system may optionally include an amplifier. Operation of a real time aperture control system is described as follows. A real time aperture control system receives a clock signal, which is provided to both the inverter and to the RC circuit. The inverter outputs an inverted clock signal and presents it to an AND gate. The RC circuit delays the clock signal and outputs a delayed clock signal. The delay is determined primarily by the capacitance of the voltage variable capacitor. Generally, as the capacitance decreases, the delay decreases.
The delayed clock signal is optionally amplified by an optional amplifier, before being presented to the AND gate. Amplification is desired, for example, where the RC constant of the RC circuit attenuates the signal below the threshold of the AND gate.
The AND gate combines the delayed clock signal, the inverted clock signal, and the optional enable signal, to generate the energy transfer signal. The apertures are adjusted in real time by varying the voltage to the voltage variable capacitor. In an embodiment, the apertures are controlled to optimize power transfer. For example, in an embodiment, the apertures are controlled to maximize power transfer. Alternatively, the apertures are controlled for variable gain control (e.g. automatic gain control - AGC). In this embodiment, power transfer is reduced by reducing the apertures. As can now be readily seen from this disclosure, many of the aperture circuits presented, and others, can be modified. Modification or selection of the aperture can be done at the design level to remain a fixed value in the circuit, or in an alternative embodiment, may be dynamically adjusted to compensate for, or address, various design goals such as receiving RF signals with enhanced efficiency that are in distinctively different bands of operation, e.g. RF signals at 900 MHz and 1.8 GHz.
7.6 Adding a Bypass Network
In an embodiment of the invention, a bypass network is added to improve the efficiency of the energy transfer module. Such a bypass network can be viewed as a means of synthetic aperture widening. Components for a bypass network are selected so that the bypass network appears substantially lower impedance to transients of the switch module (i.e., frequencies greater than the received EM signal) and appears as a moderate to high impedance to the input EM signal (e.g., greater that 100 Ohms at the RF frequency).
The time that the input signal is now connected to the opposite side of the switch module is lengthened due to the shaping caused by this network, which in simple realizations may be a capacitor or series resonant inductor-capacitor. A network that is series resonant above the input frequency would be a typical implementation. This shaping improves the conversion efficiency of an input signal that would otherwise, if one considered the aperture of the energy transfer signal only, be relatively low in frequency to be optimal.
For example, a bypass network may bypass a switch module. In this embodiment the bypass network increases the efficiency of the energy transfer module when, for example, less than optimal aperture widths were chosen for a given input frequency on an energy transfer signal. The bypass network could be of a variety of configurations. The following discussion will demonstrate the effects of a minimized aperture and the benefit provided by a bypassing network. In an initial circuit having a 550ps aperture, the peak-to-peak output (Vpp) may be 2.8mVpp applied to a 50 ohm load. Changing the aperture to 270ps will result in a diminished output of 2.5mVpp applied to a 50 ohm load. To compensate for this loss, a bypass network may be added. The result of this addition is that, for example, 3.2Vpp can now be applied to the 50 ohm load.
7.7 Modifying the Energy Transfer Signal Using Feedback
In an embodiment, a system may use a down-converted signal as a feedback to control various characteristics of the energy transfer module to modify the down-converted signal.
Generally, the amplitude of the down-converted signal varies as a function of the frequency and phase differences between the EM signal and the energy transfer signal. In an embodiment, the down-converted signal is used as the feedback to control the frequency and phase relationship between the EM signal and the energy transfer signal. This can be accomplished using a logic circuit. Various implementations will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Alternate implementations fall within the scope and spirit of the present invention. In an embodiment, a state-machine is used as an example.
In an example, a state machine reads an analog to digital (A/D) converter and controls a digital to analog (D/A) converter. In an embodiment, the state machine includes
2 memory locations, Previous and Current, to store and recall the results of reading the A/D converter. In an embodiment, the state machine uses at least one memory flag.
The D/A converter controls an input to a voltage controlled oscillator (VCO). The VCO controls a frequency input of a pulse generator, which, in an embodiment, is substantially similar to a pulse generator. The pulse generator may generate an energy transfer signal.
In an embodiment, the state machine operates in accordance with a state machine flowchart 3400 in FIG. 34. The result of this operation is to modify the frequency and phase relationship between energy transfer signal and the EM signal to substantially maintain the amplitude of the down-converted signal at an optimum level. The amplitude of the down-converted signal can be made to vary with the amplitude of the energy transfer signal. In an embodiment where a switch module is a FET, wherein the gate of the FET receives the energy transfer signal, the amplitude of the energy transfer signal can determine the "on" resistance of the FET, which affects the amplitude of the down-converted signal. An optional energy transfer signal module can be an analog circuit that enables an automatic gain control function. Alternate implementations will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Alternate implementations fall within the scope and spirit of the present invention.
7.8 Other Implementations
The implementations described above are provided for purposes of illustration. These implementations are not intended to limit the invention. Alternate implementations, differing slightly or substantially from those described herein, will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternate implementations fall within the scope and spirit of the present invention.
8. Frequency Up-conversion
The present invention is directed to systems and methods of frequency up- conversion, and applications of same.
An exemplary frequency up-conversion system 3500 is illustrated in FIG. 35. The frequency up-conversion system 3500 is now described.
An input signal 3502 (designated as "Control Signal" in FIG. 35) is accepted by a switch module 3504. For purposes of example only, assume that the input signal 3502 is a FM input signal 3806, an example of which is shown in FIG. 38C. FM input signal 3806 may have been generated by modulating information signal 3802 onto oscillating signal 3804 (FIGs. 38A and 38B). It should be understood that the invention is not limited to this embodiment. The information signal 3802 can be analog, digital, or any combination thereof, and any modulation scheme can be used. The output of switch module 3504 is a harmonically rich signal 3506, shown for example in FIG. 38D as a harmonically rich signal 3808. The harmonically rich signal 3808 has a continuous and periodic waveform.
FIG. 38E is an expanded view of two sections of harmonically rich signal 3808, section 3810 and section 3812. The harmonically rich signal 3808 may be a rectangular wave, such as a square wave or a pulse (although, the invention is not limited to this embodiment). For ease of discussion, the term "rectangular waveform" is used to refer to waveforms that are substantially rectangular. In a similar manner, the term "square wave" refers to those waveforms that are substantially square and it is not the intent of the present invention that a perfect square wave be generated or needed.
Harmonically rich signal 3808 is comprised of a plurality of sinusoidal waves whose frequencies are integer multiples of the fundamental frequency of the waveform of the harmonically rich signal 3808. These sinusoidal waves are referred to as the harmonics of the underlying waveform, and the fundamental frequency is refened to as the first harmonic. FIG. 38F and FIG. 38G show separately the sinusoidal components making up the first, third, and fifth harmonics of section 3810 and section 3812. (Note that in theory there may be an infinite number of harmonics; in this example, because harmonically rich signal 3808 is shown as a square wave, there are only odd harmonics). Three harmonics are shown simultaneously (but not summed) in FIG. 38H. The relative amplitudes of the harmonics are generally a function of the relative widths of the pulses of harmonically rich signal 3506 and the period of the fundamental frequency, and can be determined by doing a Fourier analysis of harmonically rich signal 3506. According to an embodiment of the invention, the input signal 3806 may be shaped to ensure that the amplitude of the desired harmonic is sufficient for its intended use (e.g., transmission).
A filter 3508 filters out any undesired frequencies (harmonics), and outputs an electromagnetic (EM) signal at the desired harmonic frequency or frequencies as an output signal 3510, shown for example as a filtered output signal 3814 in FIG. 381.
FIG. 36 illustrates an exemplary universal frequency up-conversion (UFU) module 3601. The UFU module 3601 includes an exemplary switch module 3504, which comprises a bias signal 3602, a resistor or impedance 3604, a universal frequency translator (UFT) 3650, and a ground 3608. The UFT 3650 includes a switch 3606. The input signal 3502 (designated as "Control Signal" in FIG. 36) controls the switch 3606 in the UFT 3650, and causes it to close and open. Harmonically rich signal 3506 is generated at a node 3605 located between the resistor or impedance 3604 and the switch 3606.
Also in FIG. 36, it can be seen that an exemplary filter 3508 is comprised of a capacitor 3610 and an inductor 3612 shunted to a ground 3614. The filter is designed to filter out the undesired harmonics of harmonically rich signal 3506.
The invention is not limited to the UFU embodiment shown in FIG. 36.
For example, in an alternate embodiment shown in FIG. 37, an unshaped input signal 3701 is routed to a pulse shaping module 3702. The pulse shaping module 3702 modifies the unshaped input signal 3701 to generate a (modified) input signal 3502
(designated as the "Control Signal" in FIG. 37). The input signal 3502 is routed to the switch module 3504, which operates in the manner described above. Also, the filter 3508 of FIG. 37 operates in the manner described above.
The purpose of the pulse shaping module 3702 is to define the pulse width of the input signal 3502. Recall that the input signal 3502 controls the opening and closing of the switch 3606 in switch module 3504. During such operation, the pulse width of the input signal 3502 establishes the pulse width of the harmonically rich signal 3506. As stated above, the relative amplitudes of the harmonics of the harmonically rich signal 3506 are a function of at least the pulse width of the harmonically rich signal 3506. As such, the pulse width of the input signal 3502 contributes to setting the relative amplitudes of the harmonics of harmonically rich signal 3506.
9. Unified Down-conversion and Filtering
The present invention is directed to systems and methods of unified down- conversion and filtering (UDF), and applications of same. In particular, the present invention includes a unified down-converting and filtering
(UDF) module that performs frequency selectivity and frequency translation in a unified (i.e., integrated) manner. By operating in this manner, the invention achieves high frequency selectivity prior to frequency translation (the invention is not limited to this embodiment). The invention achieves high frequency selectivity at substantially any frequency, including but not limited to RF (radio frequency) and greater frequencies. It should be understood that the invention is not limited to this example of RF and greater frequencies. The invention is intended, adapted, and capable of working with lower than radio frequencies.
FIG. 39 is a conceptual block diagram of a UDF module 3902 according to an embodiment of the present invention. The UDF module 3902 performs at least frequency translation and frequency selectivity.
The effect achieved by UDF module 3902 is to perform the frequency selectivity operation prior to the performance of the frequency translation operation. Thus, UDF module 3902 effectively performs input filtering. According to embodiments of the present invention, such input filtering involves a relatively nanow bandwidth. For example, such input filtering may represent channel select filtering, where the filter bandwidth may be, for example, 50 KHz to 150 KHz. It should be understood, however, that the invention is not limited to these frequencies. The invention is intended, adapted, and capable of achieving filter bandwidths of less than and greater than these values.
In embodiments of the invention, input signals 3904 received by UDF module 3902 are at radio frequencies. The UDF module 3902 effectively operates to input filter these RF input signals 3904. Specifically, in these embodiments, UDF module 3902 effectively performs input, channel select filtering of RF input signal 3904. Accordingly, the invention achieves high selectivity at high frequencies.
The UDF module 3902 effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof.
Conceptually, UDF module 3902 includes a frequency translator 3908. The frequency translator 3908 conceptually represents that portion of UDF module 3902 that performs frequency translation (down conversion).
The UDF module 3902 also conceptually includes an apparent input filter 3906 (also sometimes called an input filtering emulator). Conceptually, apparent input filter 3906 represents that portion of UDF module 3902 that performs input filtering. In practice, the input filtering operation performed by UDF module 3902 is integrated with the frequency translation operation. The input filtering operation can be viewed as being performed concunently with the frequency translation operation. This is a reason why input filter 3906 is herein refened to as an "apparent" input filter 3906.
The UDF module 3902 of the present invention includes a number of advantages.
For example, high selectivity at high frequencies is realizable using UDF module 3902. This feature of the invention is evident by the high Q factors that are attainable. For example, and without limitation, UDF module 3902 can be designed with a filter center frequency fc on the order of 900 MHz, and a filter bandwidth on the order of 50 KHz.
This represents a Q of 18,000 (Q is equal to the center frequency divided by the bandwidth). It should be understood that the invention is not limited to filters with high Q factors. The filters contemplated by the present invention may have lesser or greater Qs, depending on the application, design, and/or implementation. Also, the scope of the invention includes filters where Q factor as discussed herein is not applicable.
The invention exhibits additional advantages. For example, the filtering center frequency fc of UDF module 3902 can be electrically adjusted, either statically or dynamically.
Also, UDF module 3902 can be designed to amplify input signals.
Further, UDF module 3902 can be implemented without large resistors, capacitors, or inductors. Also, UDF module 3902 does not require that tight tolerances be maintained on the values of its individual components, i.e., its resistors, capacitors, inductors, etc. As a result, the architecture of UDF module 3902 is friendly to integrated circuit design techniques and processes.
The features and advantages exhibited by UDF module 3902 are achieved at least in part by adopting a new technological paradigm with respect to frequency selectivity and translation. Specifically, according to the present invention, UDF module 3902 performs the frequency selectivity operation and the frequency translation operation as a single, unified (integrated) operation. According to the invention, operations relating to frequency translation also contribute to the performance of frequency selectivity, and vice versa. According to embodiments of the present invention, the UDF module generates an output signal from an input signal using samples/instances of the input signal and samples/instances of the output signal. More particularly, first, the input signal is under-sampled. This input sample includes information (such as amplitude, phase, etc.) representative of the input signal existing at the time the sample was taken.
As described further below, the effect of repetitively performing this step is to translate the frequency (that is, down-convert) of the input signal to a desired lower frequency, such as an intermediate frequency (LF) or baseband.
Next, the input sample is held (that is, delayed).
Then, one or more delayed input samples (some of which may have been scaled) are combined with one or more delayed instances of the output signal (some of which may have been scaled) to generate a current instance of the output signal.
Thus, according to a prefeπed embodiment of the invention, the output signal is generated from prior samples/instances of the input signal and/or the output signal. (It is noted that, in some embodiments of the invention, cuπent samples/instances of the input signal and/or the output signal may be used to generate current instances of the output signal.). By operating in this manner, the UDF module preferably performs input filtering and frequency down-conversion in a unified manner.
FIG. 41 illustrates an exemplary implementation of a unified down-converting and filtering (UDF) module 4122. The UDF module 4122 performs the frequency translation operation and the frequency selectivity operation in an integrated, unified manner as described above, and as further described below.
In the example of FIG. 41, the frequency selectivity operation performed by UDF module 4122 comprises a band-pass filtering operation according to EQ. 20, below, which is an exemplary representation of a band-pass filtering transfer function.
VO = (α, • X • VI) - (β, • z 1 • VO) - (β0 • z 2 • VO) EQ. 20
It should be noted, however, that the invention is not limited to band-pass filtering.
Instead, the invention effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof. As will be appreciated, there are many representations of any given filter type. The invention is applicable to these filter representations. Thus, EQ. 20 is referred to herein for illustrative purposes only, and is not limiting.
The UDF module 4122 includes a down-convert and delay module 4124, first and second delay modules 4128 and 4130, first and second scaling modules 4132 and 4134, an output sample and hold module 4136, and an (optional) output smoothing module 4138.
Other embodiments of the UDF module will have these components in different configurations, and/or a subset of these components, and/or additional components. For example, and without limitation, in the configuration shown in FIG. 41, output smoothing module 4138 is optional. As further described below, in the example of FIG. 41 , down-convert and delay module 4124 and first and second delay modules 4128 and 4130 include switches that are controlled by a clock having two phases, φ, and φ2. φ, and φ2 preferably have the same frequency, and are non-overlapping (alternatively, a plurality such as two clock signals having these characteristics could be used). As used herein, the term "non-overlapping" is defined as two or more signals where only one of the signals is active at any given time.
In some embodiments, signals are "active" when they are high. In other embodiments, signals are active when they are low.
Preferably, each of these switches closes on a rising edge of φ, or φ2, and opens on the next coπesponding falling edge of φ, or φ2. However, the invention is not limited to this example. As will be apparent to persons skilled in the relevant art(s), other clock conventions can be used to control the switches.
In the example of FIG. 41, it is assumed that α, is equal to one. Thus, the output of down-convert and delay module 4124 is not scaled. As evident from the embodiments described above, however, the invention is not limited to this example. The exemplary UDF module 4122 has a filter center frequency of 900.2 MHz and a filter bandwidth of 570 KHz. The pass band of UDF module 4122 is on the order of 899.915 MHz to 900.485 MHz. The Q factor of UDF module 4122 is approximately 1879 (i.e., 900.2 MHz divided by 570 KHz).
The operation of UDF module 4122 shall now be described with reference to a Table 4002 (FIG. 40) that indicates exemplary values at nodes in UDF module 4122 at a number of consecutive time increments. It is assumed in Table 4002 that UDF module 4122 begins operating at time t-1. As indicated below, UDF module 4122 reaches steady state a few time units after operation begins. The number of time units necessary for a given UDF module to reach steady state depends on the configuration of the UDF module, and will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. At the rising edge of φ, at time t-1, a switch 4150 in down-convert and delay module 4124 closes. This allows a capacitor 4152 to charge to the current value of an input signal, VI,. „ such that node 4102 is at VI,. ,. This is indicated by cell 4004 in FIG. 40. In effect, the combination of switch 4150 and capacitor 4152 in down-convert and delay module 4124 operates to translate the frequency of the input signal VI to a desired lower frequency, such as IF or baseband. Thus, the value stored in capacitor 4152 represents an instance of a down-converted image of the input signal VI.
The manner in which down-convert and delay module 4124 performs frequency down-conversion is further described elsewhere in this application in the section entitled "Down-conversion Using a Universal Frequency Translation Module." Also at the rising edge of φ, at time t-1, a switch 4158 in first delay module 4128 closes, allowing a capacitor 4160 to charge to VO,_ ,, such that node 4106 is at NO,.,. This is indicated by cell 4006 in Table 4002. (In practice, VO,., is undefined at this point. However, for ease of understanding, VO,. , shall continue to be used for purposes of explanation.) Also at the rising edge of φ, at time t-1, a switch 4166 in second delay module
4130 closes, allowing a capacitor 4168 to charge to a value stored in a capacitor 4164. At this time, however, the value in capacitor 4164 is undefined, so the value in capacitor 4168 is undefined. This is indicated by cell 4007 in table 4002.
At the rising edge of φ2 at time t- 1, a switch 4154 in down-convert and delay module 4124 closes, allowing a capacitor 4156 to charge to the level of capacitor 4152.
Accordingly, capacitor 4156 charges to VI, ,, such that node 4104 is at VI,.,. This is indicated by cell 4010 in Table 4002.
The UDF module 4122 may optionally include a unity gain module 4190A between capacitors 4152 and 4156. The unity gain module 4190A operates as a cuπent source to enable capacitor 4156 to charge without draining the charge from capacitor
4152. For a similar reason, UDF module 4122 may include other unity gain modules 4190B-4190G. It should be understood that, for many embodiments and applications of the invention, these unity gain modules 4190A-4190G are optional. The structure and operation of unity gain modules 4190 will be apparent to persons skilled in the relevant art(s).
Also at the rising edge of φ2 at time t- 1 , a switch 4162 in first delay module 4128 closes, allowing a capacitor 4164 to charge to the level of capacitor 4160. Accordingly, capacitor 4164 charges to VO,.,, such that node 4108 is at VO,.,. This is indicated by cell 4014 in Table 4002.
Also at the rising edge of φ2 at time t-1, a switch 4170 in second delay module 4130 closes, allowing a capacitor 4172 to charge to a value stored in a capacitor 4168. At this time, however, the value in capacitor 4168 is undefined, so the value in capacitor 4172 is undefined. This is indicated by cell 4015 in table 4002.
At time t, at the rising edge of φ,, switch 4150 in down-convert and delay module 4124 closes. This allows capacitor 4152 to charge to VI,, such that node 4102 is at VI,. This is indicated in cell 4016 of Table 4002. Also at the rising edge of φ, at time t, switch 4158 in first delay module 4128 closes, thereby allowing capacitor 4160 to charge to VO,. Accordingly, node 4106 is at VO,. This is indicated in cell 4020 in Table 4002.
Further at the rising edge of φ, at time t, switch 4166 in second delay module 4130 closes, allowing a capacitor 4168 to charge to the level of capacitor 4164. Therefore, capacitor 4168 charges to VO,.,, such that node 4110 is at VO,.,. This is indicated by cell
4024 in Table 4002.
At the rising edge of φ2 at time t, switch 4154 in down-convert and delay module 4124 closes, allowing capacitor 4156 to charge to the level of capacitor 4152. Accordingly, capacitor 4156 charges to VI„ such that node 4104 is at VI,. This is indicated by cell 4028 in Table 4002.
Also at the rising edge of φ2 at time t, switch 4162 in first delay module 4128 closes, allowing capacitor 4164 to charge to the level in capacitor 4160. Therefore, capacitor 4164 charges to VO„ such that node 4108 is at VO,. This is indicated by cell 4032 in Table 4002. Further at the rising edge of φ2 at time t, switch 4170 in second delay module 4130 closes, allowing capacitor 4172 in second delay module 4130 to charge to the level of capacitor 4168 in second delay module 4130. Therefore, capacitor 4172 charges to VO,_ ,, such that node 4112 is at VO,_ ,. This is indicated in cell 4036 of FIG. 40.
At time t+1, at the rising edge of φ,, switch 4150 in down-convert and delay module 4124 closes, allowing capacitor 4152 to charge to VI,+1. Therefore, node 4102 is at VI,+1, as indicated by cell 4038 of Table 4002.
Also at the rising edge of φ, at time t+1, switch 4158 in first delay module 4128 closes, allowing capacitor 4160 to charge to VO,+1. Accordingly, node 4106 is at VO,+„ as indicated by cell 4042 in Table 4002.
Further at the rising edge of φ, at time t+1, switch 4166 in second delay module 4130 closes, allowing capacitor 4168 to charge to the level of capacitor 4164.
Accordingly, capacitor 4168 charges to VO„ as indicated by cell 4046 of Table 4002.
In the example of FIG. 41, first scaling module 4132 scales the value at node 4108 (i.e., the output of first delay module 4128) by a scaling factor of -0.1. Accordingly, the value present at node 41 14 at time t+1 is -0.1'VO,. Similarly, second scaling module 4134 scales the value present at node 4112 (i.e., the output of second scaling module 4130) by a scaling factor of -0.8. Accordingly, the value present at node 4116 is -0.8»VO,_, at time t+1.
At time t+1, the values at the inputs of summer 4126 are: VI, at node 4104, -0.1'VO, at node 4114, and -0.8»VO,_, at node 4116 (in the example of FIG. 41, the values at nodes 4114 and 4116 are summed by a second summer 4125, and this sum is presented to summer 4126). Accordingly, at time t+1, summer 4126 generates a signal equal to VI, - 0.1'VO, - 0.8»VO,.,.
At the rising edge of φ, at time t+1, a switch 4191 in output sample and hold module 4136 closes, thereby allowing a capacitor 4192 to charge to VO,+,. Accordingly, capacitor 4192 charges to VO,+,, which is equal to the sum generated by adder 4126. As just noted, this value is equal to: VI, - 0.1»VO, - 0.8»VO,_,. This is indicated in cell 4050 of Table 4002. This value is presented to optional output smoothing module 4138, which smooths the signal to thereby generate the instance of the output signal VO,+1. It is apparent from inspection that this value of VO,+, is consistent with the band pass filter transfer function of EQ. 20. 10. Integrated Communication System
Additionally, it will be apparent to those skilled in the relevant art(s) based on the teachings contained herein that an integrated communication system will result by combining any two of the embodiments described above, or by combining all three of the embodiments described above. This integrated communication system can be employed, for example, in a transceiver used in a family radio system.
11. Conclusion
The various embodiments and implementations described above are provided for purposes of illustration. These embodiments and implementations are not intended to limit the invention. Alternate embodiments and implementations, such as but not limited to software, software/hardware, and firmware implementations of the system and components of the system, are possible and are covered by the invention. Embodiments and implementations, differing slightly or substantially from those described herein, including but not limited to, combinations of modulation techniques in an "I/Q" mode, fall within the scope and spirit of the present invention, and will be apparent to those skilled in the relevant art(s) based on the teachings contained herein. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

What Is Claimed Is:
1. A down-converter, comprising: a resonant tank circuit to receive an input signal having an input frequency; an aliasing module coupled to said resonant tank circuit; a local oscillator coupled to said aliasing module.
2. The down-converter of claim 1, further comprising: an output impedance match module coupled to said aliasing module.
3. The down-converter of claim 1, wherein said aliasing module comprises: a sine-wave to square wave converter module, a pulse shaper module coupled to said sine-wave to square wave converter module, and a switch module coupled to said pulse shaper module.
4. The down-converter of claim 3, wherein said sine-wave to square wave converter module accepts an oscillating signal originating from said local oscillator said oscillating signal having an aliasing frequency.
5. The down-converter of claim 4, wherein said switch module gates a filtered input signal from said resonant tank circuit at a rate that is a function of said aliasing frequency.
6. The down-converter of claim 4, wherein said aliasing frequency is a subharmonic of said input frequency.
7. A system for down-converting an electromagnetic (EM) signal wherein the EM signal is comprised of a desired signal and an undesired signal, the desired signal having a frequency of fD, and the undesired signal being an image signal having a frequency of f„ comprising: a first universal frequency translator (UFT) aliasing the EM signal according to a first control signal and outputting a first down-converted signal; a second UFT aliasing the EM signal according to a second control signal and outputting a second down-converted signal; a phase shifting module receiving said first down-converted signal and outputting a first shifted down-converted signal; a combining module receiving said first shifted down-converted signal and said second down-converted signal and outputting an image rejected down-converted signal.
8. The system of claim 7, wherein said first control signal has a frequency fcl, wherein fcl is substantially equal to (fD + f,) ÷ (2»N), wherein N is any integer.
9. The system of claim 7, wherein said second control signal is out of phase with said first control signal by a phase angle that is substantially equal to (π/2)»(M).
10. The system of claim 7, wherein said first shifted down-converted signal and said first down-converted signal are out of phase by a phase angle that is substantially equal to π/2.
11. The system of claim 7, wherein said first signal is a shaped control signal, said shaped control signal being a string of pulses, wherein each pulse in said string of pulses has a non-negligible aperture that tends away from zero time in duration; and said second signal is a phase-shifted shaped control signal, said phase-shifted shaped control signal being a phase-shifted string of pulses, wherein each pulse in said phase-shifted string of pulses has a non-negligible aperture that tends away from zero time in duration.
12. The system of claim 11, wherein said phase shifted shaped control signal is out of phase with said shaped control signal by a phase angle that is substantially equal to π/2.
13. A high efficiency transmitter comprising: one or more circuits to amplify, filter, and process a voice signal, thereby creating a frequency modulated (FM) signal; a universal frequency translator that accepts said FM signal and a reference signal and outputs a rectangular waveform containing a plurality of harmonics; and a filter to accept said rectangular waveform and output a desired output signal, said desired output signal being comprised of one or more desired harmonics from said rectangular waveform.
14. The high efficiency transmitter of claim 13, wherein said universal frequency translator further comprises a square-up circuit, a pulse shaper, and a switch, wherein: said square-up circuit accepts said FM signal and creates an FM square wave, said pulse shaper accepts said FM square wave and creates a string of pulses, and said switch accepts said string of pulses, the opening and closing of said switch being controlled by said string of pulses, said switch also accepting said reference signal and creating said rectangular waveform.
15. A method for down-converting an electromagnetic (EM) signal comprising the steps of: (1) aliasing the EM signal with a first control signal to produce a first down- converted signal;
(2) aliasing the EM signal with a second control signal to produce a second down-converted signal;
(3) shifting said first down-converted signal to create a first shifted down- converted signal; and
(4) combining said first shifted down-converted signal and said second down- converted signal to create an image rejected down-converted signal.
16. The method of claim 15, wherein said first control signal has a first control phase and said second control signal has a second control phase, further comprising the step of: shifting said first control signal to result in said second control signal wherein the second control phase is shifted by an amount substantially equal to (π/2)»(M), where M is any odd integer.
17. The method of claim 17, wherein step (3) comprises: shifting said first down-converted signal by π/2 to create said first shifted down- converted signal.
18. The method of claim 15, wherein the EM signal is comprised of a desired signal and an undesired signal, the desired signal having a frequency of fD, and the undesired signal being an image signal having a frequency of f,, wherein said first control signal has a control frequency fc, wherein fc is substantially equal to (fD + f,) ÷ (2»N), wherein N is any integer.
19. A method for down-converting an information signal, comprising the steps of:
(1) receiving a modulated electromagnetic signal, said modulated electromagnetic signal having a frequency substantially equal to a Family Radio Service frequency;
(2) matching an impedance of a receiving circuit with an impedance of an aliasing module in a resonant tank circuit,
(3) routing said modulated electromagnetic signal through said resonant tank circuit to said aliasing module,
(4) generating an oscillating signal,
(5) shaping said oscillating signal to create an aliasing signal, said aliasing signal comprising a plurality of pulses having non-negligible apertures; and
(6) aliasing said modulated electromagnetic signal according to said aliasing signal having an aliasing rate, further comprising the step of transferring energy from said modulated electromagnetic signal at said aliasing rate, wherein said aliasing rate down-converts said modulated electromagnetic signal to one of (a) a demodulated baseband information signal, (b) an intermediate frequency signal, and (c) a non-frequency modulated signal.
20. A method for communicating, comprising the steps of:
(1) up-converting an information signal, further comprising the steps of: (a) creating a frequency modulated oscillating signal from said information signal; (b) shaping said frequency modulated oscillating signal to produce a shaped frequency modulated oscillating signal;
(c) gating a bias signal at a rate that is a function of said shaped frequency modulated oscillating signal to produce a harmonically rich signal comprised of a plurality of harmonics wherein said frequency modulated oscillating signal is a function of the information signal; and
(d) selecting one or more desired harmonics from said plurality of harmonics, each of said one or more desired harmonics being an up-converted information signal; and (2) down-converting an electromagnetic signal, further comprising the steps of:
(a) receiving a modulated electromagnetic signal;
(b) matching an impedance of a receiving circuit with an impedance of an aliasing module in a resonant tank circuit,
(c) routing said modulated electromagnetic signal through said resonant tank circuit to said aliasing module,
(d) generating an oscillating signal,
(e) shaping said oscillating signal to create an aliasing signal, said aliasing signal comprising a plurality of pulses having non-negligible apertures; and
(f) aliasing said modulated electromagnetic signal according to said aliasing signal having an aliasing rate, further comprising the step of transfemng energy from said modulated electromagnetic signal at said aliasing rate, wherein said aliasing rate down-converts said modulated electromagnetic signal to one of (i) a demodulated baseband information signal, (ii) an intermediate frequency signal, and (iii) a non- frequency modulated signal.
21. A system for communicating, comprising:
(a) an up-conversion subsystem to up-convert an information signal, further comprising
(i) a pulse shaping module to shape a modulated oscillating signal to produce a shaped modulated oscillating signal, said modulated oscillating signal being a function of the information signal; (ii) a gating module gating a bias signal at a rate that is a function of a modulated oscillating signal and producing a harmonically rich signal comprised of a plurality of harmonics; and
(iii) a selecting module selecting one or more desired harmonics from said plurality of harmonics, each of said one or more desired harmonics being an up- converted information signal; and
(b) a down-conversion subsystem to down-convert an electromagnetic signal, further comprising:
(i) a signal generator to generate an aliasing signal, said aliasing signal comprising a plurality of pulses having non-negligible apertures;
(ii) a receiving module to receive a modulated electromagnetic signal; and
(iii) an aliasing module transferring energy from said modulated electromagnetic signal at said aliasing rate and aliasing said modulated electromagnetic signal according to said aliasing signal to down-convert said modulated electromagnetic signal to one of (a) a demodulated baseband information signal, (b) an intermediate frequency signal, and (c) a non-frequency modulated signal.
22. A method for down-converting a frequency modulated (FM) signal comprising the steps of: (1) aliasing the FM signal at an aliasing rate, said aliasing rate being determined by the frequency of the FM signal;
(2) adjusting said aliasing rate to compensate for frequency changes of the FM signal; and
(3) outputting, responsive to steps (1 ) and (2), a demodulated baseband information signal.
23. The method of claim 22, wherein step (1) comprises: aliasing the FM signal at an aliasing rate that is substantially equal to a sub- harmonic of a frequency of the FM signal.
24. The method of claim 22, wherein step (1) comprises: aliasing the FM signal at an aliasing rate that is substantially equal to a frequency of the FM signal.
25. The method of claim 22, further comprising the step of: compensating for phase delays to maintain bandwidth and stability.
26. A method for directly downconverting a frequency modulated (FM) signal having a carrier frequency, comprising the steps of:
(1) aliasing the FM signal with a first local oscillator (LO) signal to create a first down-converted signal, said first LO signal having a first LO frequency and a first LO phase; (2) aliasing the FM signal with a second LO signal to create a second down- converted signal, said second LO signal having a second LO frequency and a second LO phase, wherein said second LO frequency is substantially the same as said first LO frequency, and wherein said second LO phase is shifted relative to said first LO phase;
(3) combining said first down-converted signal and said second down- converted signal to create a summation signal;
(4) integrating said summation signal to create a control signal;
(5) creating an aliasing signal from said control signal; and
(6) outputting, responsive to steps (l)-(5), a demodulated baseband information signal.
27. The method of claim 26, wherein said second LO phase is shifted relative to said first LO phase by an amount that is substantially equal to one-quarter period of the FM signal.
28. The method of claim 26, wherein said second LO phase is shifted relative to said first LO phase by an amount that is substantially equal to any multiple of a period of the FM signal plus one-quarter period of the FM signal.
29. The method of claim 26, wherein step (5) comprises: (a) compensating for phase delays to maintain stability by adjusting said control signal to create a compensated control signal; and
(b) creating said aliasing signal using said compensated control signal.
30. The method of claim 26, wherein said aliasing signal is substantially equal to a sub-harmonic of the carrier frequency of the FM signal.
31. The method of claim 26, wherein said aliasing signal is substantially equal to the carrier frequency of the FM signal.
32. A system for down-converting a frequency modulated (FM) signal having a carrier frequency, comprising: a first aliasing module to alias the FM signal with a first local oscillating (LO) signal, said first LO signal having a first LO signal frequency and a first LO signal phase, said first LO signal frequency being a function of an aliasing rate, and said first aliasing module outputting a first down-converted signal; a second aliasing module to alias the FM signal with a second LO signal, said second LO signal having a second LO signal frequency and a second LO signal phase, wherein said second LO signal frequency is substantially equal to said first LO signal frequency and said second LO signal phase is shifted relative to said first LO signal phase, said second aliasing module outputting a second down-converted signal; a summing module to combine said first down-converted signal and said second down-converted signal to create a summation signal; an integration module to integrate said summation signal and create a control signal; a voltage controlled oscillator to accept said control signal and to output an aliasing signal, wherein said aliasing signal determines said aliasing rate; and wherein said control signal is a demodulated baseband information signal.
33. The system of claim 32, further comprising a compensation module that accepts said control signal and that outputs a compensated control signal, and wherein said voltage controlled oscillator accepts said compensated control signal.
34. A method for down-converting a frequency modulated (FM) signal, comprising the steps of:
(1) aliasing the FM signal with a first local oscillator (LO) signal to create a first down-converted signal; (2) aliasing the FM signal with a second LO signal to create a second down- converted signal;
(3) generating a control signal from said first and second down-converted signals, wherein said first and second LO signals are generated from said control signal; and (4) adjusting said control signal based on frequency changes of the FM signal.
35. The method of claim 34, wherein step (3) comprises the step of:
(a) summing said first and second down-converted signals to generate a summation signal, and
(b) integrating said summation signal to generate said control signal wherein said first and second LO signals are generated from said control signal.
36. A down-converter to down-convert a frequency modulated (FM) signal, comprising: a first aliasing module to receive the FM signal and a first local oscillator (LO) signal, wherein said first aliasing module creates a first down-converted signal; a second aliasing module to receive the FM signal and a second LO signal, wherein said second aliasing module creates a second down-converted signal; a tracking module to track changes in frequency of the FM signal; and an LO signal changing module to change said first and second LO signals based on said changes in frequency.
37. The down-converter of claim 36, wherein said tracking module comprises: a summer that sums said first and second down-converted signals to generate a summation signal; and an integrator that integrates said summation signal to generate a control signal.
38. A method for communicating, comprising the steps of:
(1) selecting a radio frequency band from the electromagnetic (EM) spectrum as a band of interest;
(2) selecting a channel within said band of interest as a channel band combination;
(3) causing an input filter device to filter the EM spectrum thereby passing said channel/band combination;
(4) down-converting said channel/band combination to create a down- converted signal; and (5) causing an output filter to filter said down-converted signal to create a filtered down-converted signal.
39. The method of claim 38, wherein step (4) comprises:
(a) receiving said channel/band combination;
(b) aliasing said channel/band combination according to an aliasing signal, said aliasing signal having an aliasing frequency, said aliasing frequency being a function of a clock signal; and
(c) outputting a down-converted signal.
40. The method of claim 39, wherein said clock signal has a clock frequency, the method further comprising the step of: (6) adjusting the clock frequency for said channel/band combination so that said aliasing frequency is suitable for down-converting said channel/band combination.
41. A system for communicating, comprising: a controller that operates under the direction of a user, and that issues a first command signal and a second command signal; a control signal generator to generate a control signal according to said first command signal; and a unified down-converting and filtering (UDF) module to filter and down-convert one or more input signals based on said control signal and according to said second command signal, said UDF to thereby output a channel filtered and down-converted signal.
42. The system of claim 41, wherein one of said one or more input signals is selected as a selected input signal and said UDF module comprises: (1) a frequency translator to under-sample said selected input signal to produce an input sample of a down-converted image of said selected input signal, and to delay said input sample; and
(2) a filter, comprising:
(a) at least a portion of said frequency translator; (b) at least one delay module to delay instances of an output signal; and
(c) an adder to generate an instance of said output signal from at least one of said delayed input samples.
43. The system of claim 42, wherein said frequency translator comprises a down- convert and delay module to under-sample said selected input signal according to said control signal, wherein a frequency of said control signal is equal to a frequency of said selected input signal plus or minus a frequency of said down-converted image, divided by n, where n represents a harmonic or sub-harmonic of said input signal.
44. A method of communicating, comprising the steps of:
(1) specifying one or more radio frequency bands from the electromagnetic spectrum as bands of interest;
(2) specifying one or more channels within each of said bands of interest as channel/band combinations;
(3) selecting one of said channel/band combinations as a monitored channel/band combination; (4) causing an input filter to operate with said monitored channel/band combination, and filtering an input signal using said input filter, to create a filtered signal having a frequency within said monitored channel/band combination;
(5) down-converting said filtered signal to create a down-converted signal; (6) causing an output filter to operate with said monitored channel/band combination, and filtering said down-converted signal using said output filter; and
(7) causing said output filter to generate a filtered down-converted signal from said down-converted signal.
45. The method of claim 44, wherein step (5) comprises:
(a) receiving said filtered signal;
(b) aliasing said filtered signal according to an aliasing signal, said aliasing signal having an aliasing frequency, said aliasing frequency being a function of a clock signal; and (c) outputting said down-converted signal.
46. The method of claim 45, wherein said clock signal has a clock frequency, the method further comprising the step of:
(8) adjusting the clock frequency for said monitored channel/band combination so that said aliasing frequency is suitable for down-converting said channel/band combination.
47. The method of claim 44, further comprising the steps of:
(8) selecting a decoder to be a selected decoder, said selected decoder being configured to operate with said monitored channel/band combination; and
(9) using said selected decoder to create a decoded down-converted signal from said filtered down-converted signal.
48. The method of claim 44, further comprising the steps of: (8) repeating steps (3) through (7).
49. A system for communicating, comprising: an input filter module comprised of one or more input filters to filter one or more input signals so as to generate one or more filtered input signals; a universal frequency translator to down-convert at least one of said one or more filtered input signals to generate a down-converted signal; and an output filter module comprised of one or more output filters to filter said down- converted signal.
50. The system of claim 49, further comprising a control signal generator that outputs a control signal, wherein said universal frequency translator operates according to said control signal.
51. The system of claim 50, further comprising a decoder module comprised of one or more decoders, wherein said decoder module decodes said filtered down-converted signal to generate a decoded output signal.
52. A method of communicating, comprising the steps of: (1 ) selecting an information signal from one or more information signals as a selected information signal;
(2) determining a desired frequency for an oscillating signal;
(3) modulating said oscillating signal with said selected information signal according to a desired modulation scheme to create a modulated oscillating signal; (4) gating a bias signal at a rate that is a function of said modulated oscillating signal to create an angle modulated harmonically rich signal;
(5) enabling a filter circuit to process said angle modulated harmonically rich signal; and
(6) filtering, in said filter circuit, said angle modulated harmonically rich signal to isolate one or more desired harmonics, each of said one or more desired harmonics being a desired output signal having a desired output frequency.
53. A method of communicating, comprising the steps of:
(1) selecting an information signal from one or more information signals as a selected information signal, comprising the steps of; (a) accepting said one or more information signals, wherein said one or more information signals are unconditioned information signals,
(b) conditioning each of said unconditioned information signals to generate conditioned information signals, and (c) selecting one of said conditioned information signals as a selected information signal;
(2) determining a desired frequency for an oscillating signal;
(3) modulating said oscillating signal with said selected information signal according to a desired modulation scheme to create a modulated oscillating signal;
(4) gating a bias signal at a rate that is a function of said modulated oscillating signal to create an angle modulated harmonically rich signal, comprising the steps of;
(a) shaping said modulated oscillating signal to create a shaped modulated oscillating signal, and (b) gating a bias signal at a rate that is a function of said shaped modulated oscillating signal to create a modulated harmonically rich signal;
(5) enabling a filter circuit to process said angle modulated harmonically rich signal; and
(6) filtering, in said filter circuit, said angle modulated harmonically rich signal to isolate one or more desired harmonics, each of said one or more desired harmonics being a desired output signal having a desired output frequency.
(7) conditioning said desired output signal to generate a conditioned output signal, comprising:
(a) routing said desired output signal through a driver to generate a driven output signal, and
(b) routing said driven output signal through a power amplifier to generate an amplified output signal, said amplified output signal being said conditioned output signal;
(8) transmitting said conditioned output signal (9) repeating steps (2)-(8) for another of said one or more information signals.
54. The method of claim 52 or claim 53, wherein said desired frequency for said oscillating signal is a subharmonic of said desired output frequency.
55. A method of communicating, comprising the steps of:
(1) selecting an information signal from one or more information signals as a selected information signal; (2) determining a desired frequency for an oscillating signal;
(3) combining said selected information signal with a bias signal to create a bias/reference signal;
(4) gating said bias/reference signal at a rate that is a function of said oscillating signal to create an amplitude modulated harmonically rich signal;
(5) enabling a filter circuit to process said amplitude modulated harmonically rich signal; and
(6) filtering, in said filter circuit, said amplitude modulated harmonically rich signal to isolate one or more desired harmonics, each of said one or more desired harmonics being a desired output signal having a desired output frequency.
56. The method of claim 55, further comprising the step of:
(7) selecting another of said one or more information signals, and repeating steps (2) through (6).
57. A system for communicating, comprising: an information signal conditioning module to accept one or more information signals and to output one or more conditioned information signals, a signal selection module to accept said one or more conditioned information signals and to output a selected information signal, a modulation and frequency selection module to accept said selected information signal and to output an oscillating signal, a universal frequency translation module to accept said oscillating signal and a bias/reference signal, and to output a harmonically rich signal, and a frequency band selection module to accept said harmonically rich signal and to output one or more desired output signals.
58. A system for communicating, comprising: an information signal conditioning module comprising one or more format modules and one or more buffer memories, said one or more format modules to accept said one or more information signals and to output formatted information signals, and said one or more buffer memories to accept said formatted information signals and to output conditioned information signals; a signal selection module to accept said one or more conditioned information signals and to output a selected information signal, a modulation and frequency selection module comprising a modulation selector and an oscillating signal generator, said modulation selector to accept said selected information signal and directs said selected information signal to one of an amplitude modulation path, a phase modulation path, and a frequency modulation path, said amplitude modulation path being between said modulation selector and a bias/reference signal module, said bias/reference signal module to output said bias/reference signal, said phase modulation path and said frequency modulation path being between said modulation selector and said oscillating signal generator, said oscillating signal generator to output said oscillating signal according to a frequency control signal wherein said oscillating signal has an oscillating signal frequency that is a subharmonic of the frequency of one of said one or more desired output signals, and wherein said oscillating signal generator comprises one or more of an oscillator, a phase modulator, and a frequency modulator; a universal frequency translation module comprising a square wave generator that accepts said oscillating signal and generates a square wave, a pulse shaper that accepts said square wave and generates a string of pulses, and a switch being controlled by said string of pulses and being connected to said bias/reference signal and generating said harmonically rich signal; a frequency band selection module comprising a frequency band selector to accept said harmonically rich signal, said frequency band selector having one or more outputs connected to one or more filter circuits, said one or more filter circuits to output said one or more desired output signals; and an output conditioning module to accept said one or more desired output signals and to output an output signal.
PCT/US2000/001108 1999-01-22 2000-01-19 Down-converter using sine to square wave converter WO2000044087A2 (en)

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US11684799P 1999-01-22 1999-01-22
US11684899P 1999-01-22 1999-01-22
US11685099P 1999-01-22 1999-01-22
US60/116,848 1999-01-22
US60/116,850 1999-01-22
US60/116,847 1999-01-22
US12280599P 1999-03-03 1999-03-03
US60/122,805 1999-03-03
US09/476,330 2000-01-03
US09/476,093 2000-01-03
US09/476,091 US6704558B1 (en) 1999-01-22 2000-01-03 Image-reject down-converter and embodiments thereof, such as the family radio service
US09/476,093 US7006805B1 (en) 1999-01-22 2000-01-03 Aliasing communication system with multi-mode and multi-band functionality and embodiments thereof, such as the family radio service
US09/476,330 US6704549B1 (en) 1999-03-03 2000-01-03 Multi-mode, multi-band communication system
US09/476,091 2000-01-03
US09/476,092 US7209725B1 (en) 1999-01-22 2000-01-03 Analog zero if FM decoder and embodiments thereof, such as the family radio service
US09/476,092 2000-01-03

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FR2245130A1 (en) * 1973-09-21 1975-04-18 Jaeger Linear frequency-voltage converter - supplies charge to capacitor proportional to input frequency
EP0099265A1 (en) * 1982-07-13 1984-01-25 Westinghouse Electric Corporation Demodulator
US4816704A (en) * 1987-04-21 1989-03-28 Fiori David Frequency-to-voltage converter
EP0560228A1 (en) * 1992-03-11 1993-09-15 Sumitomo Electric Industries, Limited Mixer circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2245130A1 (en) * 1973-09-21 1975-04-18 Jaeger Linear frequency-voltage converter - supplies charge to capacitor proportional to input frequency
EP0099265A1 (en) * 1982-07-13 1984-01-25 Westinghouse Electric Corporation Demodulator
US4816704A (en) * 1987-04-21 1989-03-28 Fiori David Frequency-to-voltage converter
EP0560228A1 (en) * 1992-03-11 1993-09-15 Sumitomo Electric Industries, Limited Mixer circuit

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