WO2000048236A1 - Methods of fabricating etched structures - Google Patents

Methods of fabricating etched structures Download PDF

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Publication number
WO2000048236A1
WO2000048236A1 PCT/GB2000/000423 GB0000423W WO0048236A1 WO 2000048236 A1 WO2000048236 A1 WO 2000048236A1 GB 0000423 W GB0000423 W GB 0000423W WO 0048236 A1 WO0048236 A1 WO 0048236A1
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WO
WIPO (PCT)
Prior art keywords
layer
mask
target
sacrificial
mask layer
Prior art date
Application number
PCT/GB2000/000423
Other languages
French (fr)
Inventor
Ian Hugh White
Richard Vincent Penty
Michael Cowin
Original Assignee
University Of Bristol
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University Of Bristol filed Critical University Of Bristol
Priority to CA002367064A priority Critical patent/CA2367064A1/en
Priority to EP00902762A priority patent/EP1155440A1/en
Priority to AU24503/00A priority patent/AU765894B2/en
Publication of WO2000048236A1 publication Critical patent/WO2000048236A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G02B6/124—Geodesic lenses or integrated gratings
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

Definitions

  • the present invention relates to methods of fabricating etched structures.
  • the invention is particularly suited to the fabrication of semiconductor devices and optical devices formed by etching target materials carried by substrate layers.
  • optical devices for use in optical signal processing is very much dependent upon the method used for the fabrication of those devices .
  • Such devices include star-couplers, commonly used in fabrication of Y-branch splitters and combiners, and transmission and reflection gratings. These devices are particularly affected by the resolution of the definition of vertices produced by existing mask and etch techniques usually used for their manufacture . Due to non-perfect mask quality and the limited resolution of the photolithographic process, blunted vertices often result in a reduction in performance of the resulting component .
  • a WDM (wavelength division multiplexed) optical signal demultiplexer makes use of grating elements 10 of the type shown in Figure 1.
  • An incident wavefront 3 is split into multiple sections and a constant phase delay added to each section upon reflection by each transmission grating element 10.
  • Each section of the wavefront emerges from the grating and interferes with the other section to produce an interference pattern in the far field 5.
  • the pattern consists of a series of peaks and troughs corresponding to where constructive and destructive interference occur respectively.
  • this component can be used to spatially separate a wavelength division multiplexed signal .
  • the component separates each wavelength such that it can be detected independently of the others.
  • a previously-considered method for improving this situation uses a double mask technique.
  • Such previous methods have concentrated upon the fabrication of Y- junctions utilising dielectric masking layers to allow definition of two overlaid masking layers.
  • alternative masking materials such as dielectric, metal or InP etch stop layers must be used. These layers themselves require deposition, etch and removal, which may degrade the target material.
  • the number of processing steps is increased, and accurate overlaying of the masks can be difficult to achieve.
  • Previous reports of using the double mask technique have concentrated upon the use of Si02 and InP etch stop mask layers to achieve the two separate masking layers required to define a Y junction. For example, see Y. Shani et al .
  • a method of fabricating an etched structure in a target material comprising: forming a first mask layer on the target material, the first mask layer defining a first predetermined pattern of exposed material; depositing a sacrificial layer over the first mask layer and exposed material; forming a second mask layer on the sacrificial layer, the second mask layer defining a second predetermined pattern of exposed material; and etching the sacrificial and target material to form an etched structure in the target material defined by the combination of the first and second predetermined patterns.
  • Figure 1 illustrates an optical device
  • Figures 2 and 3 illustrate the effects of non-perfect fabrication of the device of Figure 1;
  • Figure 4 shows another optical device;
  • Figure 5 illustrates steps in a fabrication method embodying the present invention
  • Figure 6 is a scanning electron microscope image of part of the optical device of Figure 4 fabricated using a previously considered single mask technique
  • Figure 7 is a scanning electron microscope image of part of the optical device of Figure 4 fabricated using a multi-mask technique embodying the present invention
  • Figure 8 illustrates another method embodying the present invention.
  • a method embodying the present invention of fabricating an optical device will now be described in relation to the manufacture of a double grating device suitable for use in a wavelength division multiplexed optical signal transmission system.
  • the device is itself the subject of a co-pending patent application. This device is purely exemplary, since the technique is applicable to the manufacture of optical or electronic device etched into a material .
  • the exemplary device is shown in plan in Figure 4, and it can be seen that at least some of the performance of the device is dependent upon the resolution of the definition of the outer vertices of the elements, as discussed above.
  • FIG. 5 (a) to (d) A method of fabricating the device of Figure 4 is shown in Figures 5 (a) to (d) .
  • FIGs 5 (a) to (d) A plan view of the device at each step in the process, together with a cross- sectional view of the structure as viewed from perspective AA.
  • the device is formed in a layer of target material 21 which is carried by a substrate 20.
  • the target layer is a polymer layer, and the substrate could be silicon.
  • the target material 21 is spin coated with a thin layer 22 of silicone based photoresist (SBPR) and a primary window is defined by standard photolithography, thereby to produce a first mask layer 22.
  • Silicone based photoresist is chosen for the masking layer 22 since it is resistant to reactive ion etch (R.I.E) with oxygen plasma.
  • a second layer 24 of SBPR is spin coated onto the structure and a second etch window is define by standard photolithography, thereby forming a second mask layer 24.
  • the second mask layer 24 is aligned with the first mask layer so as to provide an overall mask structure.
  • the method of transfer of the pattern into the target material layer 21 is dependent on the material being processed.
  • a polymer target layer 21 is used, and so the sample is etched (R.I.E) in a oxygen plasma.
  • the removal of the exposed sacrificial polymer layer 23 can then be achieved automatically during the target layer etch process.
  • a short oxygen plasma etch would be carried out to open up all the etch windows through to the target layer 21, before a suitable etch process for the target material is undertaken.
  • the mask layers 22 and 23 SBPR
  • an ultra thin SBPR layer also allows for an improvement in the resolution obtained in the patterned etches over that obtained with metal masks using processes such as lift-off.
  • the method embodying the present invention is applicable to semiconductor devices, and also to etch patterns that requires the use of more than two mask layers .
  • the example described above has been limited to the use of two mask layers, for clarity. If more mask layers are required, then additional thin polymer layers and the mask layers themselves are added to the structure .
  • Figures 6a to 6d show scanning electron microscope (SEM) images of grating elements fabricated by a known single mask technique. As may be seen a combination of limited mask quality and limited resolution of the photolithographic process has resulted in a non-perfect double grating element.
  • the two halves of the grating element should join (31) , and the end vertices 30 should ideally be well defined and suffer from little or no rounding.
  • Such corner rounding may be estimated to be of the order of 3-4micron, which results in an error in the subsequent facet length of approximately 20%.
  • a metallic mask layer 52 upon the surface of the target material layer 51, as illustrated in figure S.
  • This metallic layer 52 might be evaporated or sputtered onto the target material layer 51 before the multi-masking layers 53, 54 and 55 are built up as previously described.
  • the final highly defined pattern may be created as normal and the final pattern then transferred into the primary metallic layer using a suitable etch process.
  • the deposition of a reflective metallic masking layer upon the surface of the target offers two advantages.
  • the target material is relatively thick and transparent to visible light there may be a reduction in the quality of a mask image that might be resolved with a microscope due to interference effects within the transparent layer structure. This would make accurate alignment of masking layers more difficult.
  • the deposition of a reflective layer onto the target material prevents light entering the target material when imaging the masks for alignment and as such eliminates the interference effects that give rise to poorly resolved images.
  • the metallic layer allows accurate alignment of masking layers on a target material that is both thick and transparent to visible light.
  • Methods embodying the present invention can provide a simplified fabrication technique for the fabrication of highly defined vertices in etched structures and devices. Such a method involves fewer process steps than current methods and allows multi-mask definition with minimal effect upon the target material .
  • the optional use of a metallic masking layer enables use of this method with a wide variety of target materials and processes, in addition to affording improved imaging where the target material is both thick and transparent .

Abstract

A method of fabricating an etched structure in a target material (21) comprises: forming a first mask layer (22) on the target material, the first mask layer defining a first predetermined pattern of exposed material; depositing a sacrificial layer (23) over the first mask layer and exposed material; forming a second mask layer (24) on the sacrificial layer, the second mask layer defining a second predetermined pattern of exposed material; and etching the sacrificial and target material to form an etched structure in the target material defined by the combination of the first and second predetermined patterns.

Description

ETHODS OF FABRICATING ETCHED STRUCTURES
The present invention relates to methods of fabricating etched structures. The invention is particularly suited to the fabrication of semiconductor devices and optical devices formed by etching target materials carried by substrate layers.
BACKGROUND OF THE INVENTION
The success of producing optical devices for use in optical signal processing is very much dependent upon the method used for the fabrication of those devices . Such devices include star-couplers, commonly used in fabrication of Y-branch splitters and combiners, and transmission and reflection gratings. These devices are particularly affected by the resolution of the definition of vertices produced by existing mask and etch techniques usually used for their manufacture . Due to non-perfect mask quality and the limited resolution of the photolithographic process, blunted vertices often result in a reduction in performance of the resulting component .
One example of such a device, a WDM (wavelength division multiplexed) optical signal demultiplexer, makes use of grating elements 10 of the type shown in Figure 1. An incident wavefront 3 is split into multiple sections and a constant phase delay added to each section upon reflection by each transmission grating element 10. Each section of the wavefront emerges from the grating and interferes with the other section to produce an interference pattern in the far field 5. The pattern consists of a series of peaks and troughs corresponding to where constructive and destructive interference occur respectively. As such this component can be used to spatially separate a wavelength division multiplexed signal . The component separates each wavelength such that it can be detected independently of the others.
The performance of such a component is dependent upon many factors such as material absorption, birefringence and dispersion. However, the quality of the definition of the grating elements 10 is also of paramount importance. Imperfect grating element formation such as rounding of the element facet vertices results in reduced grating performance. As can be seen from Figure 2 , corner rounding due to the limited resolution of the mask and the photolithographic process leads to a grating element that has an effective reflective facet length 20 which is less than the designed nominal length 18. The rounding of the corners results in scattering and loss of light into the device material.
In addition, the reduction of the facet length results in a variation of the amplitude of the diffracted gaussian field as illustrated in Figure 3. The result of this upon the image 5 in the far field of the device is a transfer of power out of the main mode into higher order interference modes, resulting in a reduction in the diftractive performance of the component.
A previously-considered method for improving this situation uses a double mask technique. Such previous methods have concentrated upon the fabrication of Y- junctions utilising dielectric masking layers to allow definition of two overlaid masking layers. However, in these double mask techniques, alternative masking materials such as dielectric, metal or InP etch stop layers must be used. These layers themselves require deposition, etch and removal, which may degrade the target material. In addition, using the previous double mask technique, the number of processing steps is increased, and accurate overlaying of the masks can be difficult to achieve. Previous reports of using the double mask technique have concentrated upon the use of Si02 and InP etch stop mask layers to achieve the two separate masking layers required to define a Y junction. For example, see Y. Shani et al . , "Buried Rib Passive Waveguide Y Junctions with Sharp Vertex on InP" , IEEE Phot. Tech Lett., 3(3), 210-212, (1991), and J.J.G.M. van der Tol et al . , "Sharp Vertices in Asymmetric Y-Junctions by Double Masking", IEEE Phot. Tech Lett., 6(2), 249-251, (1994) .
Accordingly, it is desirable to provide an improved fabrication technique that can overcome or limit the aforementioned disadvantages of the prior methods .
SUMMARY OF THE PRESENT INVENTION
According to the present invention, there is provided a method of fabricating an etched structure in a target material, the method comprising: forming a first mask layer on the target material, the first mask layer defining a first predetermined pattern of exposed material; depositing a sacrificial layer over the first mask layer and exposed material; forming a second mask layer on the sacrificial layer, the second mask layer defining a second predetermined pattern of exposed material; and etching the sacrificial and target material to form an etched structure in the target material defined by the combination of the first and second predetermined patterns. BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 illustrates an optical device;
Figures 2 and 3 illustrate the effects of non-perfect fabrication of the device of Figure 1; Figure 4 shows another optical device;
Figure 5 illustrates steps in a fabrication method embodying the present invention;
Figure 6 is a scanning electron microscope image of part of the optical device of Figure 4 fabricated using a previously considered single mask technique;
Figure 7 is a scanning electron microscope image of part of the optical device of Figure 4 fabricated using a multi-mask technique embodying the present invention; and Figure 8 illustrates another method embodying the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
A method embodying the present invention of fabricating an optical device will now be described in relation to the manufacture of a double grating device suitable for use in a wavelength division multiplexed optical signal transmission system. The device is itself the subject of a co-pending patent application. This device is purely exemplary, since the technique is applicable to the manufacture of optical or electronic device etched into a material .
The exemplary device is shown in plan in Figure 4, and it can be seen that at least some of the performance of the device is dependent upon the resolution of the definition of the outer vertices of the elements, as discussed above.
A method of fabricating the device of Figure 4 is shown in Figures 5 (a) to (d) . A plan view of the device at each step in the process, together with a cross- sectional view of the structure as viewed from perspective AA. The device is formed in a layer of target material 21 which is carried by a substrate 20. For the exemplary optical device, the target layer is a polymer layer, and the substrate could be silicon.
(a) The target material 21 is spin coated with a thin layer 22 of silicone based photoresist (SBPR) and a primary window is defined by standard photolithography, thereby to produce a first mask layer 22. Silicone based photoresist is chosen for the masking layer 22 since it is resistant to reactive ion etch (R.I.E) with oxygen plasma.
(b) An ultra-thin sacrificial polymer layer 23 is spin coated over the first mask layer 22 and thermally cured.
(c) A second layer 24 of SBPR is spin coated onto the structure and a second etch window is define by standard photolithography, thereby forming a second mask layer 24. The second mask layer 24 is aligned with the first mask layer so as to provide an overall mask structure.
(d) The method of transfer of the pattern into the target material layer 21 is dependent on the material being processed. In this example of optical device, a polymer target layer 21 is used, and so the sample is etched (R.I.E) in a oxygen plasma. The removal of the exposed sacrificial polymer layer 23 can then be achieved automatically during the target layer etch process. For alternative target layer materials, a short oxygen plasma etch would be carried out to open up all the etch windows through to the target layer 21, before a suitable etch process for the target material is undertaken. Upon completion of the etch the mask layers 22 and 23 (SBPR) can be removed, if required, in a suitable solvent.
Use of this spin-on oxygen plasma resistant SBPR in conjunction with an interleaved sacrificial polymer layer can be seen to offer advantages over previously considered methods of using a double mask technique. Use of metallic, dielectric InP or etch stop masking layers require additional process steps in deposition via evaporation, sputtering, thermal deposition or regrowth in addition to the pattern formation via etch and subsequent removal of the masking layer. By using a method according to the present invention, the elimination of the need to perform such steps can minimise possible damage to the target material.
In addition, the use of an ultra thin SBPR layer also allows for an improvement in the resolution obtained in the patterned etches over that obtained with metal masks using processes such as lift-off.
More importantly alignment of masking layers with respect to one another is simplified by the thin nature of the layers and their transparency to visible light . Indeed use of an ultra thin polymer layer 23 interleaved between the masking layers 22 and 24 enables good observation of the overall mask structure. The interleaved polymer layer 23 also acts as a protective coat to underlying mask layers and allows deposition of additional mask layers upon it's surface without interaction between mask layers. Using a combination of oxygen plasma resistant SBPR and interleaved polymer layers that can be etched by oxygen plasma allows multiple masking layers to be built up simply and once complete an oxygen plasma etch can be used to remove all exposed sacrificial polymer to reveal underlying SBPR etch windows . The component can then be etched in a suitable manner using the overlaid combination of SBPR etch windows.
It will be readily appreciated that the method embodying the present invention is applicable to semiconductor devices, and also to etch patterns that requires the use of more than two mask layers . The example described above has been limited to the use of two mask layers, for clarity. If more mask layers are required, then additional thin polymer layers and the mask layers themselves are added to the structure .
Figures 6a to 6d show scanning electron microscope (SEM) images of grating elements fabricated by a known single mask technique. As may be seen a combination of limited mask quality and limited resolution of the photolithographic process has resulted in a non-perfect double grating element. The two halves of the grating element should join (31) , and the end vertices 30 should ideally be well defined and suffer from little or no rounding. Such corner rounding may be estimated to be of the order of 3-4micron, which results in an error in the subsequent facet length of approximately 20%.
Comparing those results with the results of a method embodying the present invention, as shown in Figures 7a to 7d, it can be seen that the grating elements fabricated using the method of the invention has well defined vertices 40 and is completely formed (41) . It will be readily appreciated that utilisation of this method overcomes the limit upon the mask quality since the single mask method uses masks that are unable to define the joining of the grating elements, in contrast with the method of the invention.
To enable this method to be used in other process conditions, it would be possible to use a metallic mask layer 52 upon the surface of the target material layer 51, as illustrated in figure S. This metallic layer 52 might be evaporated or sputtered onto the target material layer 51 before the multi-masking layers 53, 54 and 55 are built up as previously described. The final highly defined pattern may be created as normal and the final pattern then transferred into the primary metallic layer using a suitable etch process. The deposition of a reflective metallic masking layer upon the surface of the target offers two advantages.
Firstly it allows the pattern to be defined in a suitable etch resistant material for differing etch processes thus allowing use with a wider range of target materials and etch process steps .
Secondly where the target material is relatively thick and transparent to visible light there may be a reduction in the quality of a mask image that might be resolved with a microscope due to interference effects within the transparent layer structure. This would make accurate alignment of masking layers more difficult. The deposition of a reflective layer onto the target material prevents light entering the target material when imaging the masks for alignment and as such eliminates the interference effects that give rise to poorly resolved images. As such the metallic layer allows accurate alignment of masking layers on a target material that is both thick and transparent to visible light.
Methods embodying the present invention can provide a simplified fabrication technique for the fabrication of highly defined vertices in etched structures and devices. Such a method involves fewer process steps than current methods and allows multi-mask definition with minimal effect upon the target material . The optional use of a metallic masking layer enables use of this method with a wide variety of target materials and processes, in addition to affording improved imaging where the target material is both thick and transparent .

Claims

CLAIMS :
1. A method of fabricating an etched structure in a target material, the method comprising: forming a first mask layer on the target material, the first mask layer defining a first predetermined pattern of exposed material; depositing a sacrificial layer over the first mask layer and exposed material; forming a second mask layer on the sacrificial layer, the second mask layer defining a second predetermined pattern of exposed material; and etching the sacrificial and target material to form an etched structure in the target material defined by the combination of the first and second predetermined patterns .
2. A method as claimed in claim 1, wherein the first mask layer is formed by spin coating a layer of mask material onto the target material, and defining etch windows in the layer of mask material by photolithography.
3. A method as claimed in claim 1 or 2, wherein the second mask layer is formed by spin coating a layer of mask material onto the target and sacrificial material, and defining etch windows in the layer of mask material by photolithography.
4. A method as claimed in claim 1, 2 or 3 , wherein the target material is a polymer material.
5. A method as claimed in claim 1, 2 or 3, wherein the target material is a semiconductor material .
6. A method as claimed in claim 1, 2 or 3 , wherein the target material is a metallic material .
7. A method as claimed in claim 1, 2 or 3, wherein the target material is a glass material .
8. A method as claimed in any one of claims 1 to 7, wherein the sacrificial material is a polymer material .
9. A method as claimed in any one of claims 1 to 7, wherein the sacrificial material is a metallic material .
10. A method as claimed in any one of claims 1 to 7, wherein the sacrificial material is a semiconductor material .
11. A method as claimed in any one of claims 1 to 7, wherein the sacrificial material is a glass material.
12. A method as claimed in any one of the preceding claims
13. A method as claimed in any one of claims 1 to 5, wherein each mask layer is provided by a layer of photoresist material, the first and second predetermined patterns being formed by a photolithographhic technique.
14. A method as claimed in any one of claims 1 to 6, wherein the etched structure defines at least part of an optical signal processing device.
15. A method as claimed in claim 1, wherein the target material comprises a base material layer, and a metallic layer, the first mask layer being formed on the metallic layer.
16. A method as claimed in claim 8, wherein the etching of the target and sacrificial material comprises : etching the metallic layer to produce a metallic mask layer, and etching the base material layer to form the etched structure therein.
17. A method as claimed in claim 8 or 9, wherein the base material is silicon.
18. A method of manufacturing an etched structure in a target material, substantially as hereinbefore described with reference to the accompanying drawings .
PCT/GB2000/000423 1999-02-11 2000-02-10 Methods of fabricating etched structures WO2000048236A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CA002367064A CA2367064A1 (en) 1999-02-11 2000-02-10 Methods of fabricating etched structures
EP00902762A EP1155440A1 (en) 1999-02-11 2000-02-10 Methods of fabricating etched structures
AU24503/00A AU765894B2 (en) 1999-02-11 2000-02-10 Methods of fabricating etched structures

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Application Number Priority Date Filing Date Title
GB9903110.6 1999-02-11
GBGB9903110.6A GB9903110D0 (en) 1999-02-11 1999-02-11 Method of fabricating etched structures

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
US7166860B2 (en) 2004-12-30 2007-01-23 E. I. Du Pont De Nemours And Company Electronic device and process for forming same
US7276453B2 (en) 2004-08-10 2007-10-02 E.I. Du Pont De Nemours And Company Methods for forming an undercut region and electronic devices incorporating the same

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US4201800A (en) * 1978-04-28 1980-05-06 International Business Machines Corp. Hardened photoresist master image mask process
EP0435187A2 (en) * 1989-12-26 1991-07-03 Fujitsu Limited Method of fabricating a semiconductor device
JPH03263834A (en) * 1990-03-14 1991-11-25 Matsushita Electron Corp Manufacture of semiconductor device
US5091290A (en) * 1990-12-03 1992-02-25 Micron Technology, Inc. Process for promoting adhesion of a layer of photoresist on a substrate having a previous layer of photoresist
US5736457A (en) * 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4201800A (en) * 1978-04-28 1980-05-06 International Business Machines Corp. Hardened photoresist master image mask process
EP0435187A2 (en) * 1989-12-26 1991-07-03 Fujitsu Limited Method of fabricating a semiconductor device
JPH03263834A (en) * 1990-03-14 1991-11-25 Matsushita Electron Corp Manufacture of semiconductor device
US5091290A (en) * 1990-12-03 1992-02-25 Micron Technology, Inc. Process for promoting adhesion of a layer of photoresist on a substrate having a previous layer of photoresist
US5736457A (en) * 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization

Non-Patent Citations (1)

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Title
PATENT ABSTRACTS OF JAPAN vol. 16, no. 73 (E - 1169) 21 February 1992 (1992-02-21) *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7276453B2 (en) 2004-08-10 2007-10-02 E.I. Du Pont De Nemours And Company Methods for forming an undercut region and electronic devices incorporating the same
US7732810B2 (en) 2004-08-10 2010-06-08 E.I. Du Pont De Nemours And Company Methods for forming an undercut region and electronic devices incorporating the same
US7166860B2 (en) 2004-12-30 2007-01-23 E. I. Du Pont De Nemours And Company Electronic device and process for forming same

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CA2367064A1 (en) 2000-08-17
EP1155440A1 (en) 2001-11-21
AU2450300A (en) 2000-08-29
AU765894B2 (en) 2003-10-02
GB9903110D0 (en) 1999-04-07

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