WO2000060567A1 - Method and apparatus for selective enabling of display elements, specially for arrangements with image signal propagation along a display conductor with tap points - Google Patents

Abstract

A method and apparatus for driving a plurality of addressable elements consist of driving and selectively enabling one or more addressable elements arranged as an MxN array using two drivers. The columns may be addressed in parallel. Columns may be coupled to a conductor by a charge transfer/isolation circuit. A voltage waveform or pulse train may be propagated down the display conductor such that a pulse is present on the display conductor for each element of a row of elements to be addressed. When the beginning of the pulse train has propagated to the last column tap-off point so that a different pulse is present at each column tap-off point corresponding to the row of elements to be selected, a corresponding charge is transferred to each column conductor in parallel. Thus, a voltage is supplied to select each element on the selected row as determined by the state of the pulse train at each column tap-off point. During the time the voltages are supplied to the column conductors, the column conductors are isolated from the column tap-off points so that a next pulse train corresponding to the next element row may be propagated down the conductor. The rows may be selected by any row addressing technique, such as individual row drivers, or a beat-frequency technique employing only two row drivers.

Description

METHOD AND APPARATUS FOR SELECΗVE ENABLING OF DISPLAY ELEMENTS, SPECIALLY FOR ARRANGEMENTS WITH IMAGE SIGNAL PROPAGATION ALONG A DISPLAY CONDUCTOR WITH TAP POINTS

Field of the Invention

This invention relates to addressing of pixels arranged in an array format for displaying applications, and more particularly to driving pixel address lines in a video display.

Background of the Invention Addressable components that can be arranged in rows and columns are commonly found in applications ranging, e.g., from memory to panel video display devices. A matrix display apparatus for displaying video signals commonly comprises a display panel having an array of addressable components arranged in row and column lines of pixels. The two-dimensional row and column lines are usually arranged in a rectangular format. The addressable component is called a picture element, display element, or pixel, and consists of a light sensitive element. The display element may emit, reflect, or transmit light in response to signals addressed into the line.

Display elements may be made from different materials and may be constructed in various ways depending on the type and use of the display device. Various types, such as liquid crystal cells, electrochromic cells, plasma cells, fluorescent display tubes, light-emitting diodes (LEDs), and electroluminescence cells have been known. Light modulating materials used to construct display elements have been well known in the industry, and they fundamentally depend on an applied electric field to modulate the amount of light emitted, reflected, or transmitted. Some of the light modulating materials do not exhibit sharp electric field versus light excitation characteristics. Thus, an active device such as a diode or transistor may be used in conjunction with the addressable components to improve the pixel light characteristics. For example, the use of a thin film MOS field effect transistor (TFT) as a switching element is well known to the artisans in the field. The light output of the picture element may be proportional to the applied addressing signal in the matrix display. In order to address a specific picture element, or pixel, in a matrix display, the pixel must be identified and excited. The excited pixel will emit, reflect, or transmit light accordingly. The pixel in the latter case is being enabled. Within an array of a pixel matrix, each pixel may have a unique address that is specified in terms of row and column location, e.g., the element at row x, and column y, or element (x,y). To excite the pixel (x,y), so that to set it to the "on" status, the pixel (x,y) is enabled by addressing the location (x,y) and exciting the pixel. The pixel may be excited by supplying a voltage above a threshold level to the addressed location.

In one addressing technique, the pixel (x,y) is electrically coupled to a row conductor which intersects with a column conductor. The pixel (x, y) is enabled by addressing the specific row conductor line x and the column conductor line y. Each line is addressed by a driving means, which addresses the line according to an applied signal. The driving means consists of a column driver circuit for each column operable according to the line frequency of an applied video signal for supplying data signals derived therefrom to the column in which the pixel is electrically coupled, a row driver circuit for each row for scanning the row in which the pixel is electrically coupled to, and a control circuit which controls the timing of operation of the driver circuits, which is responsive to an applied video signal. All pixels arranged in a row line are electrically coupled to a row line and thus to a row driver. Pixels arranged in a column line are electrically coupled to a column line and thus to a column driver. Therefore, M pixels in one row are commonly coupled to a row driver, and each separately coupled to one of M column drivers. Similarly, N pixels in one column are commonly coupled to a column driver, and each separately coupled to one of N row drivers. A matrix display of MxN pixels usually requires M column drivers and N row drivers, or M+N line drivers. Thus, a display with a resolution of 1280x1024 pixels consists of 1,310,720 pixels, 1280 columns of pixels and 1024 rows of pixels, and 2304 line drivers. Images are formed by enabling, or disabling, selected pixels in the pixel array usually in sequential manner from left to right and top to bottom

Fig. 1 depicts a conventional video matrix display device 100 comprising a plurality of pixels P that are arranged along the y-axis in N rows driven by drivers R_N and along the x-axis in M columns driven by drivers C - Each pixel P has two connecting ports. The first port 122 of the pixel P_u ) is coupled to the row lme 110a and the second port 112 of the pixel is coupled to the column lme 120a. The first port of pixels Pι_ | to P_{lt M} are electrically coupled to row 110a, while the second ports are separately coupled to the corresponding columns driven by C. to C_M. For example, to enable pixel P_3,4 row lme 110c is addressed through driver R₃, and column lme 120d is simultaneously addressed through driver C₄. A specific pattern of pixels may be addressed for enablmg the pixels by activating a plurality of row and column dπvers in a sequential manner. Thus, a large number of drivers are physically needed to construct a matrix display The number of drivers increases with the increase in the display resolution since larger numbers of rows and columns are needed. A need therefore exists to reduce the number of dπvers m a device usmg addressable components. For high-resolution displays, the cost of a large number of drivers may be significant to the overall cost of the display. The complexity of circuitry components associated with the drivers, such as signal generators, control units, and driver memory also increases with resolution, and further provides a disadvantage in addition to the large number of dπvers. Reducmg the number of needed dπvers m matrix display devices, such as flat panel displays, while achievmg or maintaining the same or better image resolution is desirable.

Summary of the Invention

The problems identified above may be in large part solved by a matrix display method and apparatus that eliminates the large number of row and column line drivers needed to address and selectively enable addressable elements or pixels. To achieve the above advantage, an embodiment of the apparatus may provide a total of only two drivers to drive a MxN display device, such as a flat panel display A first and a second driver may be used to drive first and second signals at slightly different frequencies (or phase) on a first and a second display conductor A plurality of pixels may be coupled between the first and second display conductors The pixels may be addressed accordmg to a pixel location in which the first signal may be approximately in phase with the second signal. The pixel location changes from one pixel to the next at a scan rate proportional to the difference between the first and second signal frequencies. The first and second conductors may contain a plurality of delay elements and tap-off points, wherein each pixel may be coupled between tap-off pomts on the first and second conductors. A plurality of pixel row and column conductors may be provided, each connected to a different tap-off pomt of the first and second display conductors.

The row and column conductors may be terminated by their characteristic impedance to prevent any reflection of the traveling signal. Further, the first and the second display conductors may also be terminated by their characteristic impedance to prevent any reflection of the signals traveling on any of the conductors. The peπods of the first and second signals may be greater than or approximately equal to a propagation delay of between first and last tap-off pomts on the first and second conductors, respectively. The pulse width of the first and second signals may be less than or approximately equal to a propagation time of the first and second signal between adjacent tap-off points on the first and second display conductors, respectively The matrix display pixels may be selectively enabled by modulating an amplitude of the first signal and an amplitude of the second signal when the selected pixel locatιon(s) is addressed so that the voltage differential between the first and second signals is sufficient to enable the addressed pixel Broadly speaking, a method and apparatus are contemplated to selectively enable addressable elements m a

MxN array arrangement The apparatus may comprise two separate display conductors driven by two separate drivers where the frequency of their signals is different A plurality of addressable elements may be connected to tap-off points on the two display conductors A plurality of row and column conductors may be connected to the first and second display conductors Each row or column conductor may be connected mto a single point on the display conductor and may be terminated by its charactenstic impedance The signals travelmg on each display conductor may be sequentially delayed by delay elements The pixels may be sequentially addressed at a rate proportional to the difference in frequency between the first and second signals, and may be selectively enabled accordmg to the difference in amplitude between the first and second signals

A pixel display is further contemplated comprising a sequence of pixels, each pixel coupled between a first display conductor and a separate second display conductor wherem a first driver and a second dπvers drive a first signal and a second signal on the first and second display conductors, respectively The pixels may be sequentially addressed at a rate proportional to the difference in frequency between the first and second signals, while they may be selectively activated accordmg to the difference m amplitude between the first and second signals

A method is further contemplated for dπvmg an addressable elements aπay compπsmg dnv ng a first signal on a first addressing conductor at a first frequency, and driving a second signal on a second addressing conductor at a second frequency The second addressing conductor is separate from the first addressing conductor, and the first and second frequencies may be slightly different The addressable elements may be sequentially addressed accordmg to an addressable element location where the first signal is approximately m phase with the second signal The activation of select addressable elements may be achieved by modulating the amplitudes of the first and second signals durmg the time when a pixel selected to be turned on is addressed so that the amplitude differential of the first and second signals may be sufficient to activate the selected addressable element

For another solution, m a display comprising pixels arrayed in M rows and N columns, pixels in every row are coupled together by a row conductive element having first and second ends, and pixels in every column are coupled together by a column conductive element having first and second ends The row-coupled pixels are driven by first and second row drivers (DX_1; DX₂) coupled respectively to the first and second ends of the row conductive element The column-coupled pixels are driven by first and second column dπvers (DY₃, DY ) coupled respectively to the first and second ends of the column conductive element Thus, a total of only four drivers is used to address MxN elements m the array

Each driver outputs a time-varying signal of a different frequency, and the dπver signals propagate through the associated conductive element The amplitude of any one driver is about half the total amplitude needed to activate or rum on a pixel The time-varying voltage seen by a pixel in a row is determined by the amplitude and frequency (U)_h ω₂) of row drivers DX,, DX₂, and by the propagation time needed for the signals to reach the pixel Similarly, column pixels see time-varying voltage signals determined by the amplitude and frequency (ω₃, ω₄) of column drivers DY₃, DY , and by the relevant propagation time One embodiment implements a pixel enablmg signal usmg the beat-frequency difference between two driver source signals that propagate through a pixel string from opposite ends of the string The dnver difference signal dwells sufficiently long on each pixel location to deliver sufficient energy to turn the pixel on or off Vertical scan rate is determined by frequency differential (ω ω₂), and horizontal scan rate frequency differential (u)₃-ω ) The absolute frequencies U)ι,u)₂,ω₃,ω₄ are set proportional to the propagation delay of the medium through which the signals from DXi, DX₂, DY₃, DY₄ travel Preferably the frequencies of the driver signals coupled to the same conductive element are approximately comparable to the inverse of the end-end propagation time associated with the conductive element Video information to be displayed is used to modulate at least one of the row dπvers and one of the column dπvers

In another embodiment, the columns may be addressed in parallel Columns may be coupled to a display conductor by a charge transfer/isolation circuit A voltage waveform or pulse tram may be propagated down the display conductor such that a pulse is present on the display conductor for each pixel of a row of pixels to be addressed When the beginning of the pulse tram has propagated to the last column tap-off pomt so that a different pulse is present at each column tap-off pomt corresponding to the row of pixels to be selected, a corresponding charge is transferred to each column conductor in parallel Thus, a voltage is supplied to turn each pixel on or off on the selected row as determined by the state of the pulse tram at each column tap-off point Duπng the tune the voltages are supplied to the column conductors, the column conductors are isolated from the column tap-off points so that a next pulse tram corresponding to the next pixel row may be propagated down the display conductor The rows may be selected by any row addressing technique, such as individual row dπvers, or a beat-frequency technique employing only two row drivers

In one embodiment, the charge transfer/isolation device for each column conductor comprises a diode with its anode connected to a column tap-off on the display conductor and its cathode connected to the column conductor A capacitor may also be mcluded The anode of each capacitor may be connected to the column conductor and the cathodes connected to a load signal The load signal may be dπven to a low voltage to transfer charge to the capacitors accordmg to the state of the pulse tram at each tap-off pomt The load signal may be dπven to a high voltage to supply the charge to the column conductors When the load signal is high, the diodes may be reversed biased or off to that the column conductors are isolated from the display conductor a the next row pulse tram is propagated on the display conductor

Other features and advantages of the invention will appear from the following descπption m which the preferred embodiments have been set forth in detail, m conjunction with the accompanying drawings

Brief Description of the Drawings

Other features and advantages of the mventton will appear from the folio wmg description in which the preferred embodiments have been set forth details, m conjunction with the accompanying drawings, m which

Fig 1 is a block diagram illustrating a matrix display device comprising MxN pixels, driven by a total of M+N drivers, accordmg to the prior art, Fig 2 is a block diagram illustrating an embodiment of a matπx display device comprising MxN pixels dπven by two dnvers,

Fig 3 depicts the propagation of signals within a matπx display,

Fig 4 illustrates signal waveforms associated with Fig 3, in sequential manner at a pomt of time,

Fig 5 is a simplified diagram to illustrate how individual elements are addressed m a mafπx display device,

Fig 6 illustrates display signal waveforms at various pomts of the display of Fig 5, Fig. 7 illustrates the enabling of an addressable element that requires different enabling needs than those directly provided by the addressing signals,

Fig. 8 depicts a plurality of pixels in a simplified matπx display device to illustrate the scanning of pixels,

Fig 9 illustrates the wave fronts of signals in Fig 7 illustrating the scanning (e g., sequential addressing) of a plurality of pixels,

Fig. 10 illustrates the waveforms of driver signals and a modulatmg signal to enable a particular pixel m Fig. 7,

Fig 11 depicts an embodiment in which the delay elements of Fig. 3 are extensions made on a circuit board, Fig. 12 depicts an embodiment in which the display conductor is a plane,

Fig 13 is a block driver of a display comprising MxN pixels, driven by a total of four dπvers,

Fιgs.l4A and 14B depict the time-dependent dπver signal voltage present at different pixels along a conductive element, Fig 15 depicts an embodiment in which time-dependent drivers are coupled between first and second conductive planes,

Fig 16 depicts the amplitude band type envelope produced when beatmg digital pulse trams whose peπod differential coπesponds to a desired envelope period,

Fig. 17 depicts the optional use of rectifying diodes in a display; Figs. 18A, 18B and 18C depict rectified driver signals present at different pixel node locations for the exemplary configuration of Figure 17,

Fig. 19A is a block dπver of a display comprising MxN pixels, driven by a total of four digital dπvers;

Figs. 19B, 19C, 19D, 19E depict prefeπed time relation-ships between the digital dπve signals for the embodiment of Fig. 19A, Fig. 20 depicts a sample scanning sequence for a display usmg four drivers,

Fig. 21 depicts a sample scanning sequence for a display usmg two drivers,

Fig. 22 illustrates an apparatus to simultaneously address all columns,

Fig. 23 illustrates an apparatus using a parallel column addressing mechanism;

Fig. 24 illustrates another parallel column addressing mechanism for the apparatus m Fig. 23, Fig. 25 illustrates a discharge mechanism for the apparatus of Fig. 24;

Fig. 26 is a waveform diagram for the operation of the apparatus of Fig. 25,

Fig. 27 depicts sub-cell units column and display conductors,

Fig. 28 illustrates the parallel column driving mechanism in Figs 22-27 for a display matπx; and

Fig. 29 illustrates an embodiment m which rows are selected by a beat frequency method and columns are dπven by a parallel column drive method

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the mvention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives fallmg within the spirit and scope of the present mvention as defined by the appended claims Detailed Description of the Invention

Turning now to the drawings, Fig. 2 is a block diagram depicting an embodiment of a matπx display device 200 compnsmg MxN addressable elements, or pixels, 250 driven by two drivers 21 Or, 210c Each dπver 210 generates a signal regulated by the control unit 205. The driver 210 signal is fed into display conductors 240 termmated by characteristic impedance 215 to prevent the signal from bemg reflected. Note that elements associated with column dπver 210c may be designated with a "c" suffix, such as column display conductor 240c, and elements associated with row dπver 21 Or may be designated with an "r" suffix, such as row display conductor 240r However, these elements may be geneπcally referred to without the suffix Display conductor 240 may be any signal conduction medium that permits propagation of the signal from the dπver 210 to the impedance termination unit 215. The signal generated by driver 210 propagates through display conductor 240 at a speed proportional to the speed of light (3 x 10⁸ meter/sec), and mversely proportional to the square root of the dielectπc constant of the conductor mateπal. The signals generated by dπvers 210 are different in frequency or m phase Display conductor 240 may compπse delay elements 230, which delay the signal propagation between two adjacent columns or rows. The plurality of pixels 250 m the matrix display device 200 is shown aπanged in a rectangular format compnsmg N electπcally conductive lines 270 (columns) and M electncally conductive lmes 260 (rows) It will be appreciated by those skilled in the art that aπangements of the plurality of pixels 250 are not restricted to only rectangular format but they can be made mto different shapes and patterns. Columns 270 and rows 260 are electπcally coupled separately to lines 240 so that the signals travelmg m respective display conductors 240c,r may be propagated through the conductive columns and rows. Each of the plurality of columns 270 and each of the plurality of rows 260 may be termmated by an impedance element 220 Impedance element 220 is selected so that no reflection is allowed for the signal travelmg down that lme. Each of the plurality of pixels 250 is coupled to a conductive column 270 and a conductive row 260.

An individual pixel of plurality of pixels 250 is enabled, or disabled, based on the conditions of the signals bemg conducted through at least one column 270 and one row 260. The conditions comprise the frequency difference between the signals of the drivers 210 and amplitude of at least one dπver 210 signal. The frequency difference is determined based on driver 210 signal frequencies, the delay characteristics of the display conductor, and the type of the addressable elements. The amplitude of one or both signal dnvers is determined based on modulatmg video signals. Only two dπvers may be needed to address MxN pixels compared to M+N dnvers needed to address the same number of elements in the prior art Turning now to Figs. 3 and 4, the propagation of signals accordmg to the embodiment of Fig 2 is illustrated. Fig. 3 depicts a portion the matrix display device 200 showing control unit 205, signal dπver 210, display conductor 240, delay elements 230, and impedance units 215 and 220 The direction of signal propagation down the lme 240 is shown by the numeric 295. The directions of the signal propagation down the conductive columns 270 are shown by the numeπc 290. Fig 4 shows the waveform of a dnving signal generated by signal dπver 210 and transmitted through lme 240 The specific wave shape is arbitrary, and the dπver signal is shown as numeric 211. Signal 211 is fed into the delay element 230a before reaching column 270b The signal 211 is the same at the first column 270a movmg in the direction 290 The signal 212 is generated in column 270b due to the delay by 230a. Further, the signal 213 is generated m column 270c due to the delay by delay element 230b Similarly, the signal propagated through line 240 is sequentially delayed m-1 times before reachmg the last conductive column 270m. Turning now to Fig 5, an illustration of the principle of operation accordmg to one embodiment is shown Drivers 210c and 21 Or separately drive two display conductors 240c and 240r, respectively Conductive lmes forming columns 270 and rows 260 are used to drive the coupled pixels A and B Columns are electrically coupled to lme 240c at the locations (A-E), while the rows are electrically coupled to lme 240r at the locations (H-L) For simplicity, only two columns and two rows are shown Pixels A and B are electπcally coupled to columns 270b and 270e, as shown at 219A and 219B, and electrically coupled to rows 260h and 260j, as shown at 218A and 218B VI and V2 represent the signals from drivers 210c and 21 Or, respectively, whose differential amplitude may be sufficient to enable or disable a pixel The pulse width of the signals generated by 210c and 21 Or is selected to be the propagation time between two adjacent nodes (such as A and B) on the conductor lme The peπod of the voltage signals may be comparable to or greater than the propagation time each signal takes to travel down the lmes 240 Therefore, at any pomt in tune each location (A-E) across line 240c will have a different phase of the dnving signal Similarly, each location (H-L) across line 240r will have different phase of the driving signal At some locations the differential voltage amplitude may be higher than a threshold level needed to enable a pixel, and at other locations may be lower than the threshold level Smce the periods of the voltage signals VI and V2 may be set comparable to (or greater than) the signal propagation time the signals take to travel down the lines 240, the frequency of VI and V2 may be proportional to the propagation delay of the lines 240 Smce VI and V2 have different frequencies, the amplitude of the differential voltage signal (the sum of VI and V2) at any particular pixel location is the waveform where the shape of the high frequency carrier signal is the low frequency difference between the two signals The rate of change of the differential voltage signal can be mdependently controlled by selecting the frequency difference between VI and V2 signals Accordmg to one embodiment, this control is provided by the control unιt(s) 205 in Fig 2 of this mvention The provided control functιon(s) is responsive to the video sιgnal(s) 201 shown in Fig 2 Smce the amplitude of the differential voltage signal is the pixel addressing signal, which vanes m both tune and location, enablmg or disabling of a specific pixel or a plurality of pixels may be achieved Further, smce the frequency of the modulated signal is much lower than the absolute frequency of VI and V2 signals, addressing of pixels can be performed at a reasonably slow rate

Considering now pixel A m Fig 5 At a point of time when the signal VI travelmg line 240c at the location B has a specific amplitude that is considered "high", one port (or side) of pixel A will be set "high" through the couplmg at 219A To enable pixel A, the second signal V2 travelmg down lme 240r may be low at the row H at approximately the same point m tune when the VI signal is high at the column B, so that the other side of pixel A is set low through the coupling at 218A If the amplitude of the differential voltage signal across pixel A has been modulated above the threshold level, pixel A will be enabled (turned on) Otherwise, pixel A is disabled (scanned, but turned-off)

Fig 6 illustrates an example of the signals at various pomts of Fig 5 The signal numeric 281 donates the desired voltage signal across the pixel A in order to enable pixel A The desired voltage signal is applied across the nodes 219A and 218A The numerics 282 and 283 refer to the driver signals VI and V2, respectively At the location shown, the signal 282 is the signal at node 219A and 283 is at node 218 A The numeric 284 shows the differential voltage signal (V2-V1) across pixel A The actual signal across the pixel may be more of the shape of the signal 285 due to capacitance of the pixel VI may compnse periodic low-gomg pulses while V2 may compnse periodic high-gomg pulses The pulse width is shown as W_P Duπng the pomt in time m which VI and V2 are approximately m phase at the location of pixel A, the pulses of VI will sum with the pulses of V2 to create the addressing/enabling differential voltage shown at time interval 286 If the amplitude of the signal pulses is modulated sufficiently high (low) during time interval 286, pixel A will be enabled (turned on) When VI and V2 are not in phase at pixel A, as shown at time interval 287, pixel A is not addressed The other pixel locations of the display are sequentially addressed during 287 The pixel-addressing scheme above is given as a matter of example Addressing of a pixel m accordance with this invention is not restπcted to the example above It will appreciated by those skilled m the art that the enabling, or disabling, of pixels can be achieved by various combination of the signal across nodes 218 and 219 that are appropriate to the particular addressable element Possible combmations, in addition to the above example, include different signal shapes, orientation, duration, frequency, levels, and logic As mentioned earlier, the signal generated by the dπver 210 propagates m lme 240 at a speed proportional to the speed of light and mversely proportional to the square root of the medium dielectπc constant The value of the dielectπc constant is typically ranged between 1-10 for the majoπty of mateπals used in the field of electronics Therefore, the dπver signal travels the conductor lme at a speed m the order of a few 10⁸ meters per second For typical dimensions m a matrix display device such as video monitors, the distance between pixels is m the order of one millimeter or less ( 10³ meters), and the length of the display is in the order of tens of centimeters ( 10² meters) The residence time the signal may spend on each coupling nodes on lme 240, such as A-E and H-L of Fig 5, can be assessed by

Tr = (D)^{υ 5} x L / 3x 10⁸xN (seconds)

where D is the conductor medium dielectric constant, L is the length of the conductor in meters, and N is the number of couplmg nodes on the conductor For a conductor lme of 12 mches, and 1280 couplmg nodes, the signal residence time on each node is m the order of few picoseconds Depending on the practical addressable element technology, the residence tune of enablmg signals may be significantly greater than few picoseconds In a typical addressable element, the residence time requirements of the enablmg signal may be m the order of tens of nanoseconds The total energy delivered to the addressable element may not be sufficient to enable the pixel if the applied pulse is very short In such cases, a storage element is required to accumulate enough energy for sustammg the display element Further, dependmg on the particular type of the display element, the signal across the element, or at the contact mode(s) may also need to be rectified or reshaped for the purpose of enabling the element Fig 7 shows an example which implements a storage element to enable a pixel when the addressmg pulse width is much shorter than the element enablmg need The figure shows two diodes 259 coupled to address lmes 270b and 260j, and a resistor and capacitor coupled across pixel A When the signal at node 219 is high and the signal at node 218 is low, diodes 259 are conductmg The voltage at node 257 is the voltage of the lme 240c less the voltage drop on diode 259a The voltage at node 258 is the voltage of the lme 240r plus the voltage drop across diode 259b The voltage difference between nodes 257 and 258 is the addressmg or enablmg voltage pulse across the pixel A This pulse occurs at a frequency proportional to the difference between drivers 210c and 21 Or signal frequencies, and applied across pixel A depending on the alignment of the high and low of the signals VI and V2 at pomts B and G, respectively The capacitor C coupled across the pixel A is selected to hold charge that is sufficient to sustain pixel _ A in the enabling state until the next enabling pulse, but not sufficient to enable pixel A by itself Thus, the capacitor charge is discharged into resistor R if the next enablmg pulse is not applied and consequently pixel A is disabled The above example is intended only for the purpose of explanation and not to limit the invention to the specific application explained It will be appreciated by those skilled in the art that numerous circuit combinations are possible to relate the addressmg signal conditions into the specific enabling/disabling needs of the particular display element

Turning now to Figs 8, 9 and 10, as an illustrative example, the scanning of a plurality of addressable elements (pixels) accordmg to one embodiment of the present mvention is shown One port of each of a plurality of pixels (A, B, and C) are commonly coupled to row lme yl while the other ports are coupled into column lmes xl, x2, and x3, respectively Similarly, pixels (D, E, F) and (G, H, I) are coupled mto the coπespondmg row and address lmes. The signal at yl, y2, and y3 is the time-dependent voltage of lme 240r, generated by dπver 210r, consequently delayed by delay elements 230. Similarly, the signal at xl, x2, and x3 is the time-dependent voltage of lme 240c, generated by dπver 210c, consequently delayed by delay elements 230. Fig. 9 shows an example of the signal waveform on lme yl, y2, y3; and xl, x2, and x3. In this example, for simplicity of illustration, the dπver 21 Or (Fig. 8) signal is selected as 180-degrees in phase compared to the dnver 210c signal. Only nine pixels are shown for simplicity. Further, m this example, the enablmg scheme is selected to occur if the voltage at the row addressmg lme is high and the voltage at the column addressmg lme is low Consequently, if the voltage across the pixel is maximum (the difference between the two addressmg signals), the pixel will be enabled Otherwise the pixel will be disabled. As can be seen m Fig. 8, pixel A achieves simultaneous high and low signals, followed by pixel E, followed by pixel I, and so on Smce the addressmg signals on lmes 240 are delayed by a fixed amount by delay elements 230 between the row lmes and the column lmes; and the enablmg pulse width is set equal to approximately the delay amount between two adjacent rows or columns to prevent more than one pixel bemg enabled at a tune; a diagonal scanning results throughout the pixels. In this example, pixels A-I are diagonally scanned m the following sequence: A, E, I, B, F, G, C, D, H.

To enable (turn-on) a particular pixel or a plurality of pixels, the amplitude of the differential signal across the pixel is modulated by the incoming video signal. Fig 10 shows the signals at row yl, y2, and y3; and column xl, x2, and x3, along with a modulating signal M Note that pulse tram signals are shown wherem multiple pulses will sum across a given pixel to address/enable the pixel, as opposed to the smgle pulse example of Fig. 9 The position of the letters A, E, I, B, F, etc, indicate the time duπng which the pulse tram signals on row yl, y2, y3 and column xl, x2, x3 are in phase at the coπespondmg pixel location. To enable pixel E and H, for example, the amplitude of at least one driver signal is modulated The modulation occurs at the tune when the scanning effect reaches the particular pixels to be enabled, l e , when the signals are approximately m phase at that pixel location Fig. 10 shows the time-dependent modulatmg signal M with two pulses ml and m2, where the time delay between ml and m2 correspond to the scanning delay between pixel E and pixel H The pulse ml occurs at the time when the pixel scanning is addressmg pixel E, thus pixel E is enabled. Similarly, the pulse m2 occurs at the time when the pixel scanning is addressmg pixel H, thus pixel H is enabled. If the dnvers' signal frequencies are much higher than the enabling need of the particular display element, many dnver pulses may comcide across the pixel before the addressing location moves mto the next pixel Thus, allowmg for the simple video modulation descnbed above The time between the two vertical dashed lines is the time required for one complete scan of the nme pixel display In the first scan illustrated in Fig 10, only pixels E and H are enabled (turned on) It is clear how this nme pixel example may be expanded to any desired display size or resolution

The elements of the display device accordmg to the preset invention are not restncted to the specific examples given in the figures For example, the delay elements, display conductors, address lines, as well as the addressable elements may be implemented using different techniques known m the art By a means of example, Fig 11 depicts an embodiment m which the delay elements are made as extensions of the first and second conductors For example, a delay element may comprise a serpentine printed circuit board trace Numeπc 231 represent delay elements as taps made of the conductor lme 240 The addressmg lines 270 are coupled to lme 240 between the delay elements Fig 12 depicts a display 600 compnsmg a first plane 660a and a second plane 660b acting as a first and second displays conductors Plane 660a is coupled mto dnver 610a, which drives the addressmg signal through 660a Plane 660b is coupled mto driver 610b, which drives the addressmg signal through 660b Dπvers 610 are coupled to control units 620 which control the addressmg signals in accordance with the video signals to be displayed Conducting planes 660 are coupled to units 690 to prevent any wave reflection that may occur in the conductmg planes In this embodiment, portions of the plane conductor 610a act as column addressmg bands 661, while portions of the plane conductor 660b act as row addressmg bands 662 An addressable element or pixel 650 is created m the area where enabled bands of the two conductmg planes overlap A particular pixel or a plurality of pixels is addressed when the signals through the addressmg bands 661 and 662 meet designated requirements needed to enable the addressable element

Turning now to a different embodiment, Figure 13 depicts an anay 2100 as compnsmg a plurality of pixels (again shown as squares) that are aπanged along a y-axis in M rows and along an x-axis in N columns Similar to Figure 1, the MxN pixels are identifiable by their co-ordinates, e g , pixel (1,1), pixel (2,1) through pixel (X_M,Y_N) However, m anay 2100, each horizontal pixel is coupled together by a common row conductive element 2200, and each vertical pixel is coupled together by a common column conductive element 2300 By "coupled together" it is meant that electromagnetic energy carried by the conductive element is coupled to the pixels Such couplmg may be ohmic, e g , a direct electrical connection between the conductive element and pixels, or non-ohmic m that it suffices that the energy transfer occurs, perhaps by electrostatic couplmg or otherwise

In Figure 13 row conductive element 2200 is drawn m phantom to make it more readily distinguished from column conductive element 2300 In the embodiment shown, conductive elements 2200 and 2300 are each serpentine-like in shape and will have a known end-to-end length determined by the physical dimensions of array 2100 The physical dimensions of array 2100, m turn, are affected by the mdividual pixel size and the spaced-apart distance between pixels

The row-coupled pixels are driven by first and second rowdnvers (DX|, DX₂) coupled respectively to the first and second ends of the row conductive element 2200 Similarly, column-coupled pixels are dnven by first and second column dπvers (DY₃, DY₄) coupled respectively to the first and second ends of the column conductive element 2300 As explained herein, a total of only four drivers (DXj, DX₂, DY₃, DY₄) is used to address the MxN elements m the array

Each dπver outputs a time- varying signal of a different frequency, and the dπver signals propagate through the associated conductive element Thus, driver DX1 outputs a driver signal fl(ci)it), driver DX2 outputs f2(ω₂t), dπver DY3 outputs 0(ω₃t), and driver DY4 outputs driver signal f4(ω t) The amplitude of any given dπver is about half the magnitude needed to activate a pixel Thus, a pixel is activated by a combmation of signals from two dnvers, one coupled to either end of the conductive element associated with the pixel

The time for electromagnetic waves such as dπver signals, to propagate through a mateπal (e g , the conductive elements and associated materials) at a velocity proportional to the speed of light is given by

_ velocityof light V pn

Vdielectπc constant in which the dielectnc constant (or permittivity) is that of the conductive elements and associated materials (or the equivalent) The velocity of light is 3xl0⁸ m/sec, and the dielectπc constant of commonly used display mateπals will be m the range of about 3 to 10 Thus, the dπver signals will travel along the conductive elements at a rate of perhaps 1 5xl0⁸ m/sec Because the driver signal is propagating so rapidly past each pixel, there would be insufficient dwell time to transfer enough energy to light-up any pixel completely For example, present display technologies scan (and activate or light-up) pixels at a rate of perhaps 30 ns per pixel Even with the serpentine configuration of Figure 13, in a 30 cm x 30 cm panel, an activation pulse would only spend 2 ns on each column or row

Further, simply directly couplmg a single dπve signal to a string of pixels would result m all pixels bemg bπefly partially activated (l e lit up) as the activating pulse passed over them Consequently, it would be impossible to selectively light up only some of the pixels in this string because the same activating signal as it propagates down the string would pass over all pixels equally

These two problems of how to select mdividual pixels and how to use an otherwise too rapidly propagating dπve signal are solved m the present mvention by usmg the beat-frequency difference between two dnver signals as the pixel enablmg signal This difference signal dwells sufficiently long on each pixel location to deliver or transfer sufficient energy to turn the pixel on (activate) or off (de-activate) The time-varying voltage seen by a pixel m a row is determined by the amplitude and frequency the two row dnver signals fι(ωιt) and f2(ω₂t) output by row dnvers DX_b DX₂, and by the propagation time needed for the signals to reach the pixel Similarly, column pixels see time- varying voltage signals determined by the amplitude and frequency of the two column driver signal f3(ϋ)₃t) and f4(U)₄t) output by column drivers DY3, DY4,

Accordmg to the present mvention, the display horizontal scan rate is determined by the frequency differential (ω_rω₂), and the vertical scan rate frequency differential (ω₃-ω ) Further, the absolute frequencies U)ι,ω₂,ω₃,ω₄ are set proportional to the propagation delay of the medium through which the signals from DX^ DX₂, DY₃, DY travel Video information to be displayed on display 2100 is used to modulate at least one of the row drivers and one of the column dnvers Thus m Figure 13, modulator 2400 is coupled to driver DXl and modulator 2500 is coupled to dnver DY4 Of course modulation could instead or in addition be coupled to drivers DX2 and/or DY3

Because the absolute frequencies (Ui ω₂, ω₃, ω are set proportional to the propagation delay of the medium, the resultant composite voltages resultmg from the sum of the two row-dπven voltages and from the sum of the two column-driven voltages will vary with time and with physical location on the conductive element bemg dnven

Consider now the pixel driver waveforms shown m Figures 14A and 14B Assume that nme pixels are connected-together in senes by a conductive element havmg a voltage dπver coupled to each end of the conductive element, whose propagation time end-to-end is about 1 ns Assume that adjacent pixels are spaced apart a distance 18 mm, and that the voltage dnvers output respective signals fl(u)ιf) and f2(ω₂t), wherein each signal is 1 V peak- peak, e g , a voltage peak-peak magnitude that is too low for an mdividual driver signal to activate a pixel

Accordmg to the present mvention, the period of each voltage dπver signal is made approximately comparable to the conductive element propagation time By comparable it is meant that the peπod is within about ±100%, the period being twice the propagation time in the present example Thus, if the conductive element propagation time is 1 ns, let tϋ| = 500 MHz, and ω₂ = 600 MHz This frequency relationship ensures a phase difference between fl(U)₁t) and f2(ω₂t) sufficient to cause each pixel to see a combmed driver signal that differs significantly at each location m the pixel string Since the two driver signals are ongrnating from different locations relative to any given pixel, then signal summation will differ at any particular pixel location at the same mstant of

Figure 14A shows the time-dependent voltage present at the first pixel m the string, e.g , the pixel closest to driver signal fl(Wit), and Figure 14B depicts the voltage present at a pixel mid-way between the first and last pixel in the pixel string. Note that these voltages have the form of an amplitude modulated sinewave m which the high frequency carrier has an amplitude "envelope" representmg the low frequency difference between the two dπver signals. In this example, the envelope frequency is indeed about 100 MHz, e g., (600 MHz - 500 MHz).

Accordmg to the present mvention, the rate of change of the envelope is independently set by selecting the frequency difference between the two dπver signals. However, the absolute frequency of the two dπver signals is set proportional to the propagation delay of the medium through which they travel In this manner, mdividual pixels are addressed at a reasonably slow rate.

It is apparent from examination of Figures 14A and 14B that voltage maxima traverse left and right with a period that is proportional to the difference m periods between the two driver voltage waveforms, e.g., l/ω_1; and l/ω₂ Indeed, this phenomena is present even if the display is implemented not with discrete row and column conductive elements, but with overlymg planes

Figure 15, for example, depicts a display 2500 as compnsmg a first plane 2600 contammg pixels that are addressed by drivers fi and f2 and an overlymg second plane 2700 contammg pixels addressed by dπvers f3 and f4 (For brevity, the Figure 15 notation fl is understood to stand for fl(uJιf), etc.) In this embodiment, first plane 2600 is the row conductive element, whose first and second ends are two opposite diagonal portions of the plane. Similarly, plane 2700 is the column conductive element, whose first and second ends are two opposite diagonal portions of the plane.

In Figure 15, the dπver signals are selected accordmg to the above-descnbed cπteπa. As the fl and f2 signals vary with time, a horizontal band 2800 of pixels is addressed, and as the £3 and f4 signals vary with time, a vertical band 2900 of pixels is addressed The time-motion of these two bands is depicted in Figure 15 by phantom double-arrowed lmes Only pixels lymg at the time-varying mtersection 1000 of movmg bands 2800, 2900 will be active at any given time

Regardless of whether serpentine conductive elements, or conductive planes are utilized m a video display, the preferred enabling waveform is not a smusoid, but rather a digital pulse tram. However, the above-descnbed principals still apply The width of the digital pulses will be proportional to the pixel area that is to be enabled Assume agam that nme pixels (spaced-apart a distance 110 cm) are senes-connected by a conductive element having a digital voltage driver coupled to each end. Let each voltage dnver have an output impedance of R Ω, and let the voltage dπvers output respective digital pulse signals fl(t) and f2(t) that are perhaps 5 V peak-peak Assume that the end-end conductive element propagation time is now 6 ns, and thus the time to propagate from pixel to adjacent pixel is about 0.75 ns. Let fl(t) and f2(t) each output a pulse tram havmg logic "1" level pulses for about 1 ns

In the present digital example, at any pixel location along the pixel string, the voltage will be the continuous sum of the two source voltage waveforms Assume that a pixel is active (e.g., on) when the voltage at the pixel node location exceeds about 3 VDC Let the peπod of fl(t) be 6 ns, and the penod of f2(t) be 5.64 ns, such that the period differential yields a scanning period of 94 ns Thus, l/peπod ,_fr = 1/(5.64 ns) - 1/(6 ns) These waveform charactenstics demonstrate the presence of a beat frequency that is lower than the two source frequencies Figure 16 depicts the composite voltage waveform, at the first node (and also the last node) in the exemplary string of nme pixels Note that two unique locations experience a voltage exceeding about 3 VDC at any given time, these locations bemg symmetrical about the central pixel node Note m Figure 16 that the envelope of the high frequency pulses has a period of about 94 ns, e g., a period coπespondmg to the differential in the frequency of the two input voltage sources fl(t) and £2(f)

For a cathode ray tube ("CRT") type scannmg system, the vertical frame rate is scanned at about 60 Hz, which means the differential in frequency between the fl(t) and f2(f) voltage sources should be 60 Hz In practice, the summed or composite signal at each pixel node may require rectification to produce a continuous pulse that turns on the pixel. If required, a common diode D_N may be implemented per pixel P_N, as shown m Figure 17. The R_NC_N low pass filter associated with each diode rectifier may be implemented usmg stray capacitance and resistance in the anay structure In an existing TFT LCD, each pixel diode may simply be the emitter-base junction of the existmg thin film transistor In any event, it will be appreciated that fabncatmg a diode rectifier per pixel (if needed) is less burdensome than implementing an active TFT dnver per LCD pixel, m terms of cost, yield, and overall reliability. Alternatively, the diode may be implemented per row or per column, replacmg a row or column dπver, instead of replacing a pixel dπver, if a separate propagation path is used.

Figures 18A and 18B depict rectified driver voltages at pixels P2 and P3 in the simplified nme-pixel configuration shown in Figure 17 When the rectified voltage is "high", slightly above 2.5 VDC m this example, the pixel is active or turned on, and when the voltage is "low" or below about 2.5 VDC, the pixel is inactive or turned off The penod of the amplitude peaks is agam about 94 ns, as mtended. A comparison between Figures 18A and 18B shows that pixel P3 turns on at a different time than pixel P2. Figure 18C depicts the sequential activation of pixels P4, P3, P2, PI for the simplified configuration of Figure 17 Note that the pixels are sequentially turned on usmg only two dnvers, but respond as though they were discretely addressed usmg a plurality of drivers, as in the pπor art. Figure 19A depicts a prefeπed embodiment of a display 1100 that is similar to what was depicted m Figure

13, except that row drivers DXl, DX2 and column dπvers DY3, DY4 each output respective digital pulse tram driver signals fl (t), f2 (t), O (t), f4 (t) rather than sinusoidal waveforms Each of the driver signals produce half the voltage magnitude required to enable a pixel As shown, conductive elements 2200 and 2300 preferably are perpendicular serpentine gπds of wire. The periods of signals fl(t) and £2(t), PV1 and PV2 respectively, preferably are separated by Y (Hz), and the amplitude of fl(t) and/or f2(t) may be amplitude modulated by the desired video signal. The penods of signals f3(t) and f4(t), PV3 and PV4 respectively, preferably are separated by X (Hz), and either or both of these signals may also be modulated by the desired video signal. Further, the relative roles of each pair of dπvers outputting the dπver signals may be interchanged, if desired The phase of each dnver signal may be controlled to simplify video memory timing, if desired. Such phase control is known m the art and will now be detailed herem.

In a typical video display, information is read out from a video random access memory ("VRAM") sequentially under the control of a vertical and horizontal synchronization signal. The beam or image refresh sweeps from the top left corner of the screen, moving from left to nght and from top to bottom Each pixel on the screen has a coπespondmg byte of information in the VRAM In the present mvention, the peak of the scannmg enable band occurs when the sum of the two source drivers are both high. In Figure 19A, by setting the phase of DXl to start at the peak voltage at T=0 and by setting DX2 to start at the midpoint between peaks, the amplitude band will be a maximum on row #1 at T=0, given that the propagation time of the serpentine row electrode is 1/2 the penod of DX2. The pulse that starts DXl is the equivalent of the vertical sync signal m a conventional display In common digital logic, the vertical sync signal would reset a counter that generates the DXl signal. In an identical fashion, horizontal sync is used to synchronize the start of the DY3 and DY4 sources.

The frequency separation between fl(t) and f2(t), e.g., the respective repetition rates, is set by the desired vertical refresh rate for display 1100. In present day display systems, the vertical refresh rate typically is m the range of about 60 Hz to about 120 Hz, although other frequencies could of course be implemented by properly selectmg the frequency separation. Figures 19B, 19C, 19D and 19E depict the timing relationships between fl(t), f2(f), β(t) and f4(t) for the embodiment of Figure 19A. The combmed fl(t) and f2(t) signals sequentially enable each row of pixels, and the combmed O(t) and f4(f) signals sequentially enable each column of pixels. The amplitude of any or all of these dnver signals is modulated by the video information to be displayed, to define whether an addressed (e.g., enabled) pixel

The period PV1 of fl(t) preferably is approximately equal to 2*N*T props, where N is the number of rows, and T prop is the propagation delay. The period difference (PV1-PV2) is set by the desired vertical scanning rate for the display. For a vertical scan rate havmg a 60 Hz refresh cycle, (PV1-PV2) = 1/60 (sec.) = 16.7 ms. The penod difference (PV3-PV4) is set by the desired horizontal scannmg rate, which is typically determined by the type of display element used, e.g., LCD, plasma, cold cathode, etc. For a 10 KHz horizontal scannmg rate, (PV3- PV4) = 1/10,000 = 100 μS.

The pulse width W_a associated with fl(t) and f2(t) pulses is the row enable pulse width, and will be comparable to the propagation time of the physical width of the display, 15" (38 cm), for example. For a 38 cm wide display, W_a would be about 2.5 ns. The pulse width W_b associated with f3(t) and f4(t) pulses is the column enable pulse width, and will be comparable to the propagation delay of the physical height of the display, 11.5" (29.2 cm), for example. For a 29.2 cm high display havmg typical dielectric matenals, W_b would be about 2 ns. As the display area is increased, the dπve circuitry implementing DXl, DX2, DX3, DX4 becomes simplified because the pulse widths W_a and W_b become wider, e.g., longer in duration.

Figure 20 depicts a sample scannmg sequence, accordmg to the present invention, and depicts the travel of the combined row and column select amplitude enable bands. The bands are depicted as heavy row and column lmes, and will be found at a location where the amplitude envelope of fl(t) + f(2) is high, and where the amplitude envelope of G(t) + f4(t) is high. In this example, it is assumed that fl(t) is a higher frequency than f2(t), and thus the scannmg direction is away from the higher frequency source toward the lower frequency source. Similarly, it is assumed that f4(t) is a higher frequency than O(t), and thus the scannmg direction is also in a direction away from f4(t) toward the lower frequency O(t). In Figure 20, pixel A is presently lit up, and pixel B will be the next pixel addressed, after which pixel C and then pixel D will be addressed.

Figure 21 depicts another embodiment of the present mvention, wherem only two dπvers DXA outputting fA(t) and DXB outputting fB(t) are used to drive display 1200. The preferably serpentine conductive elements 2200 and 2300 are senes-coupled at their non-dπven ends. In this embodiment, the active pixel is scanned diagonally, e.g., pixel A, then pixel B, then pixel C The startmg phase of fl(t) relative to f4(t) defines which diagonal "line" is scanned. In the various described embodiments of the present invention, it is to be understood that the display in question may be monochrome or color, and may be implemented usmg techniques other than liquid crystal, for example, plasma, cold cathode, among other technologies In a color display, the pixels shown m the vaπous embodiments herem may be considered to be separate aπays of red, or green, or blue pixels Alternatively, the pixels m an anay m an embodiment descnbed herein may be considered to be alternating combmations of red, green, and blue pixels, e g , different colored pixels in the smgle anay shown m the figures In the vaπous LCD embodiments, the present invention provides a response and contrast ratio commensurate with that provided by more expensive active matrix displays, TFT for example However, this performance is attained without the thousands of dπvers needed m prior art implementations, and without the expense and yield difficulties associated with implementing literally millions of per-pixel thin film transistors In a plasma or cold cathode display where each of thousands of dnvers must be relatively high voltage units, the cost savmgs provided by the present mvention is even more dramatic

Parallel Column Addressmg Some display technologies may require that all columns m a selected row be addressed in a very short time period For example, some plasma display technologies may have such a requirement The shorter time penod for column addressing may arise from the nature of the display technology or from a requirement that each row be scanned multiple tunes duπng a refresh penod to create different intensities for such applications as gray scale displays The beat-frequency techniques descnbed above may not be feasible for addressmg the columns when such short time penods are required by the display technology For example, if all columns must be selected for each row in a very short time penod it may be difficult to impart enough energy to each column to properly activate the display elements usmg the beat frequency techniques described above An 853 x 480 pixel display m some technologies may allow only 2 5 microseconds per row to address the 853 columns

A solution to the above noted problem is illustrated m Figure 22 A video driver 710 may dπve a pulse tram on display conductor 740 Each pulse of the pulse tram may coπespond to a pixel on a row to be selected A high voltage pulse may indicate that the pixel is to be "on" and a low voltage pulse may indicate that the pixel is to be "off The display conductor may be termmated by termination device 708, which may match the charactenstic impedance of the display conductor to minimize reflection Tap-off pomt A-N are located along display conductor 740 A propagation delay between each tap-off pomt is represented by delay element 730 Delay element 730 may be circuit board trace, a discrete delay element, or other delay associated with display conductor 740 between tap- off pomts The width of the pulse of the video pulse tram driven on display conductor 740 may be approximately equal to the propagation delay between tap-off points such that when the leadmg pulse reaches that last tap-off pomt N, a different pulse is present at each tap-off pomt coπespondmg to a row of pixels to be selected Control circuitry 705 controls the pulse tram accordmg to a video data signal The voltage differential of the pulse tram dπven on display conductor 740 may coπespond to the voltage differential to be applied to column conductors 770 When the leadmg pulse of a pulse tram for a given row has propagated to the last tap-off pomt, a charge from each tap-off point is transfeπed to the coπespondmg column conductor 770 by a charge transfer/isolation circuit 712 A load signal may be driven to each charge transfer/isolation circuit to enable the charge transfer Note that m one embodiment if the coπespondmg pixel is to be "off, no charge is transfeπed by circuit 712, and if the coπespondmg pixel is to be "on", a charge necessary to place the column conductor at the appropriate voltage to activate the pixel is transfeπed The width of the load signal may be approximately less than or equal to the pulse width of the pulses of the video pulse tram on display conductor 740. This is to ensure that the charge for only one pulse is transfeπed

Once charge transfer is complete, the load signal is deasserted While the load signal is deasserted, the column conductors 770 are isolated from the display conductor 740 Duπng this isolation tune, a new pulse tram coπespondmg to the next pixel row is bemg propagated down the display conductor. Also duπng this isolation time, the transfeπed charge is being applied to the individual column conductors without bemg affected by the new pulse tram. Note that the pixel rows are not illustrated for sake of claπty. The rows may be selected by any row addressmg technique. In a prefeπed embodiment, a beat frequency techniques is used to select the rows

Turning now to Figure 23, a prefeπed implementation of a parallel column addressmg mechanism is shown Note that the terms "column" and "row" are not limiting and the techniques descnbed herem may be applied for addressmg either columns or rows or both. Each row of the display matnx may be selected accordmg to a beat frequency method, such as described above in Figures 2-21. For sake of clarity some details are not shown in Figure 1, such as the individual pixel elements and termination components at the end of each row However, it is understood that such components may be present Each row 760 may be tapped off of a display conductor 840 The display conductor 840 is driven at each end by a display dπver 805 and 810, respectively Between each row tap is a delay element 830. As descnbed above the delay element 830 may mclude cncuit board trace, such as m a serpentine matter, or discrete components, such as an LC component or some other delay device. A pulse tram is dπven at each end of display conductor 840 by the drivers 805 and 810, respectively The period of the pulse tram is approximately equal to or greater than the propagation delay for the length of display conductor 840 from the first to last tap-of pomts. The width of each pulse may be approximately equal to the propagation delay between adjacent row taps Thus, a pulse from driver 805 will sum with a pulse from dnver 810 at only one row tap at a time at a sufficient voltage level to select the given row The frequency between the two pulse trams is different so that the pomt at which the pulses sum to select a row changes at a rate proportional to the frequency difference or beat-frequency. Instead of selectmg both the rows and the columns by a beat frequency technique, such as m figure 13 above, the columns in Figure 23 are addressed accordmg to a parallel technique. The video data to be displayed on a given row of pixels is shifted in to a seπes of shift registers and parallel latches 900. While the data is bemg dπven to a cuπently selected row by drivers 905 the data for the next row of pixels is bemg shifted m to the shift register/latches 900. The shift register/latches 900 function essentially as a serial to parallel converter When a new row is selected the data for that row is simultaneously latched m parallel onto the mputs of each of the column dπvers 905. The column dnver 905 mputs provided from the shift register/latches 900 are typically low voltage digital signals (as is the video data signal shifted mto the shift register / parallel latches 900). Column dπvers 905 amplify the low voltage mput signal to a high voltage to dnve the column so that if the voltage differential between a particular column and row is above the display element threshold the display element is eliminated or activated Thus, each row may be selected by the afore described beat frequency technique However, the columns are simultaneously dnven m parallel for each selected row Driving the columns approximately simultaneously m parallel allows each column to be activated at the appropriate amplitude for a penod of tune approximately equal to the row select time such that the requirements of the display technology may be satisfied However, it is noted that this technique requires a senes of low voltage digital shift registers and latches and a high voltage amplifier dnver for each column. Havmg the shifter register / parallel latch logic and high voltage dπvers for each column conductor increases the cost and complexity of the display driver apparatus as compared to the pure frequency techniques descnbed above

Turning now to Figure 24 a column driving technique is illustrated that reduces the complexity and/or cost of driving the columns simultaneously m parallel as m Figure 23 The technique illustrated in Figure 24 does not require the digital shift registers and latches nor does it require a high voltage amplifier dπver for each column Instead, a display conductor 740 is provided havmg column tap conductors 770 A delay element 730 is present between each column tap 770 The delay element 730 may be similar to the delay elements descnbed above For example, the delay element may include circuit board trace such as in a serpentine manner or discrete LC components or other delay components Dπver 710 outputs a pulse train coπespondmg to the pixel data for a given row onto the display conductor 740 The dπver 710 may be controller by control unit 705 which receives a video data signal Reference number 795 illustrates the direction of propagation of the pulse tram output from dπver 710 The propagation delay for the display conductor 740 for a given pulse of the pulse tram to travel from the first column tap 770a to the last column tap 770n may be approximately equal to the address period for each row Thus, while a cuπent row of pixels is being dπven by column conductors 770, a pulse tram for the next row is bemg driven by dπver 710 down display conductor 740

The voltage differential of the pulse tram signal driven on display conductor 740 is approximately equal to the voltage differential that must be dπven on the column conductors to activate the display pixels When the pulse tram for the next row has reached the last column tap on display conductor 740, a load pulse may be dnven by load dnver 715 m order to transfer the appropriate signal to the column conductor 770 To further illustrate the operation of the parallel column dπver circuitry of Figure 24, an example is given below The voltage levels given m the example may be typical for certain display technologies, however, the parallel column dnver illustrated m Figure 24 is not limited to any particular voltage levels

A diode 702 may be connected between each column conductor 770 and the display conductor 740 A separate capacitor 704 is coupled to each column conductor 770 The cathode of each capacitor is connected together to a common conductor dπven by load driver 715 Load driver 715 dnves the cathode of each capacitor high while the cuπent row charge is being transfeπed from capacitor 704 to each column conductor 770 Duπng this tune the new row charge values for the next row to be selected are bemg driven down display conductor 740 by dnver 710 Diodes 702 are reversed biased or off durmg this time so that the display conductor 740 is isolated from the column conductors 770 When the new pulse train is fully present on display conductor 740 load dπver 715 lowers the voltage on the common cathodes on capacitors 704 The new row charge values are loaded on to capacitors 704 while the load driver is asserting the low voltage on the capacitors 704 cathodes The load dπver 715 lowers the capacitor 704 cathode voltage for an amount of time approximately less than or equal to the propagation delay between the column taps on display conductor 740 This is so that the row charge amount for a particular row does not spill over to the next row while the columns 770 are bemg loaded When load dnver 715 raises the voltage at the common cathodes for capacitor 704, the charge stored on capacitor 704 is supplied to the column conductor 770 to activate the pixels on the selected row accordmg to the amount of charge stored on each capacitor 704 Diodes 702 are off or reversed biased during this time to isolate display conductor 740 from column 770 so that the charge values for the next row may be propagated down display conductor 740 Capacitors 704 may be discrete capacitor components Alternatively, they may compnse the parasitic capacitance of a conductor trace smce the cathodes of the capacitor 704 are all connected to load dnver 715 In other words, a portion of the conductor driven by load driver 715 may overly a portion of each column conductor 770 in order to form the capacitor 704

It may be necessary that enough charge must be pulled off each storage capacitor 704 so that each capacitor is "erased" before the next loadmg cycle If the load of the column (and pixels) itself does not draw enough charge off the capacitor then a separate discharge mechanism, such as a resistor or diode, may be necessary Figure 25 illustrates a discharge mechanism added to the parallel column driver apparatus of Figure 24 In this example diodes 706 are connected to each column conductor with the cathode of each diode connected together and to a dπver 725 for dπvmg a clear voltage pulse Durmg the time m which the charge has been transfeπed from capacitor 704 to column conductor 740 and the next row pulse tram is being propagated down display conductor 740, the clear driver 725 asserts a high voltage to the cathodes of diode 706 so that the diodes are off or reversed biased At the end of a row penod before the next set of row charges are loaded to the column conductors, clear dnver 725 deasserts the anode voltage for each diode 706 to clear any residual charge off the storage capacitor 704 pnor to load dπver 715 lowermg the cathode voltage of capacitor 704 to load the next seπes of row charges Note that the discharge circuitry of Figure 25 may not be necessary or alternatively resistors or some other component may be used mstead of diodes 706

Turing now to Figure 26 a waveform diagram is provided to further illustrate the operation of the display element dnve mechanism illustrated m Figure 25 Waveform 1000 illustrates a pulse tram bemg dnven during time penod W_D on display conductor 740 The way form 1000 shows the pulse train 01100111 bemg dnven duπng the time penod W_D In this example it assumed that there are eight column conductor tap off pomts along display conductor 740 so that at the end of tune penod W_D the pattern of way form 1000 is present on the column conductor tap off pomts For example, a low voltage would be present on the column tap-off pomt closest to the video dnver 710, followed by a high voltage on the next two tap-off pomts, followed by a low voltage on the two tap-off pomts after that, followed by a high voltage on the most distant three tap-off pomts from video dπver 710 Time penod W_D may coπespond approximately to the propagation delay down the length of display conductor 740 from the first tap-off point to the last tap-off pomt Time period W_D may also approximately coπespond to the time required to scan each row of pixels in the display The width W_τ of each mdividual pulse of the pulse tram 1000 may coπespond approximately to the propagation delay time between the individual tap-off pomts on display conductor 740 The tap-off pomts are located along display conductor 740 so that the propagation delay time as represented by delay element 730 is approximately the same between each adjacent tap-off pomt The pulse tram represents the pattem of pixels that are to be activated for the next selected pixel row

Thus, the pulse tram 1000 illustrates that from left to right on the pixel row, the pixels are to be off, on, on, off, off, on, on, on Note that m the example illustrated m Figure 26 the voltage swing of the pulse tram 1000 is from a high of 07 volts to a low of negative 69 3 volts This voltage swmg and the voltage swmg of the other waveforms m Figure 26 is merely an example coπespondmg to a particular display technology However, the present mechanism may be used with any suitable voltage swing as required any particular display technology Durmg the time penod W_D that the pulse tram for the next row of pixels is bemg propagated along display conductor 740, clear dnver 725 and load dπver 715 are at their respective high voltage levels as illustrated by waveforms 1002 and 1004, respectively Thus, diodes 706 are reverse biased and the charge stored on capacitors 704 is bemg transfeπed to the column conductors 770 as illustrated durmg time period W_P at waveform 1006 Note that the charge stored on capacitors 704 durmg this time period W_P coπesponds to the previous pulse train driven on display conductor 740 Thus, durmg the time the next pulse train is bemg propagated down display conductor 740, as illustrated duπng time period W_D, the previous pulse tram is bemg supplied to the column conductors as illustrated duπng time period W_P Note that duπng time period W_P either 70 or zero volts is bemg supplied from capacitor 704 to each column conductor dependmg upon if the particular row pixel for the particular column is intended to be activated or not Before the pulse tram of waveform 1000 is to be transfeπed to the column conductors, clear dπver 725 dnves a low voltage to the cathodes of the diodes 706 as shown at time pomt 1020 This serves to clear any residual charge on capacitor 704 When the pulse tram reaches the end of display conductor 740, load dπver 715 asserts a low voltage on the cathodes of capacitors 704 In the example of Figure 26 -70 volts is applied to the cathodes of capacitors 704 at this pomt Also at this point, the voltage at the first column tap-off pomt is at -693 volts, the voltage at the next two tap-off pomts is at 0 7 volts, followed by -69 3 volts at the next two tap-off pomts, followed by 0 7 volts at the last three tap-off pomts When load driver 715 applies -70 volts to the cathodes of capacitors 704, the anode of each capacitor 704 is also pulled down by 70 volts smce the voltage on a capacitor cannot change mstantaneously Thus, the diode 702 connected to the first tap-off pomt from display conductor 740 and the first column conductor 770 will have -70 volts at its cathode and -69 3 volts at its anode The diode at the second tap-off pomt on the display conductor will have -70 volts on its cathode and 07 volts on its anode at this instant Therefor, when load dπver 715 applies -70 volts to the cathodes of capacitors 704, the diodes connected to the first, fourth, and fifth tap-off points will be off smce the voltage difference across these diodes is only 07 volts (less than the rum on voltage of the diodes) and the second, third, sixth, seventh, and eighth diodes will be on smce the voltage difference across these diodes is 70 7 volts This in turn will cause a charge transfer from the display conductor tap-off pomts to the capacitors 704 through the on diodes The second, third, sixth, seventh, and eighth capacitors will thus charge up to zero volts and the first, fourth, and fifth capacitors will remain at -70 volts while the load dπver 715 asserts -70 volts at the capacitor cathodes Thus, while the load dπver 715 asserts a low voltage on the cathodes of capacitors 704, the capacitors are charged to the voltage coπespondmg to the respective voltage of the pulse tram illustrated by waveform 1000 When load dπver 715 transitions the cathodes of the capacitors 704 from -70 volts to zero volts as shown at time pomt 1024, the anodes of the capacitors 704 will also be shifted upward by 70 volts as illustrated by waveform 1006 Thus, the first, fourth, and fifth capacitors will be charged at zero volts and the second, third, sixth, seventh, and eighth capacitors will be charged at 70 volts to coπespond to the pulse tram that was shifted on the display conductor 740 durmg tune period W_D These voltage levels are now applied to the column conductors and thus selected row pixels while the next pulse tram is bemg shifted down display conductor 740

Note that load driver 715 asserts a low voltage (in this example -70 volts) for a penod of time W_c which is set to be approximately less than or equal to the propagation tune between adjacent taps on display conductor 740 This is so that a charge pulse propagating down display conductor 740 which also has a width approximately equal to the propagation delay between taps does not spill over to the next tap while the load dπver 715 is dnving the load voltage of -70 volts Durmg the time that the load dnver 715 and clear driver 725 are assertmg their respective high voltages, the diodes 702 are off or reversed biased to isolate the column conductor 770 from the display conductor 740 This allows the charge from capacitors 704 to be applied to the column conductors 770 while the next pulse tram is bemg shifted on display conductor 740 As mentioned above, before the next pulse tram is loaded onto the capacitors 704 any residual capacitor charge is cleared by clear dnver 725 assertmg a low voltage on the cathodes of the diodes 706 as illustrated by waveform 1002 The width W_E of this clear pulse is illustrated to be approximately equal to the load pulse width W_c However, there is not necessaπly a direct coπespondence between these pulse widths For example, smce some charge is dissipated from the capacitors by the pixel loads, the clear pulse width W_E may be shorter than the load pulse width W_c

It may be desirable to maximize the clear and load pulse widths to reduce the peak sinking cuπent capability required of clear driver 725 and load driver 715 within the constraints of the display timing For example, an 853 x 480 display may allow only 2 5 microseconds per row If all 853 columns were simultaneously addressed every 2 5 microseconds, the video waveform pulse width W_τ and the load pulse width W_c would be approximately 2.5 μs / 853 = 2.9 ns In this example, if a zero to 70 volt column pulse for 2.5 microseconds is desired mto a load drawing 100 rmcroamps and the dπve pulse cannot droop more than 10 volts to properly activate a pixel, a 25 pf capacitor for capacitor 704 would be required as calculated from I = C*dV/dT, where I=100uA, dV=10V, dT=2.5μs. Note that these values are merely an example for one particular display Using the 2.9 nanosecond pulse width and the 25 picofarad capacitance values calculated above, the load driver 715, for example, may have to sink 515 amps when assertmg the load signal to capacitor 704 worse case.

It may not be feasible for the dπvers to sink such a large cuπent as calculated above A solution to this problem is to break the column conductor 770 and display conductor 740 mto a number of sub-cell units as illustrated m Figure 27 For example, the 853 columns may be divided mto 54 sub-cells with approximately 16 taps and column conductors per sub-cell Thus, m such a system there would be 54 display conductors 740 each havmg 16 tap-off pomts and column conductors. Separate dnvers may be provided for each sub-cell This sub-cell architecture may reduce the cuπent which the load dnver 715, for example, must sulk to 180 milliamps peak for the worst case where all columns are at the high voltage. In this example, the video pulse tram pulse width and the load pulse width may be 156 ns and each driver must sink cuπent for only 16 loads. The sub-cell architecture allows the cuπent sink capacity of the dπvers to be traded off agamst the number of sub-cells and the number of dπvers. The greater the sub-cell division the less cuπent sink capacity required by each dnver Note also that a one-to-one coπelation of dπvers to sub-cells is not necessanly required. For example, each sub-cell may have its own load dnver, but several sub-cells may share a clear dnver. In the above example the actual power dissipated by the load driver, for example, may be low because of the low duty cycle of the load cycle (156 nanoseconds divided by 2.5 microseconds = 6%) The sub-cell architecture allows the column groupmgs and number of dnvers to be adjusted to meet the desired tradeoff between number of dnvers and dπver capacity

Tummg now to Figure 28, the parallel column driving mechanism descnbed above m Figures 22-27 is illustrated for a display matrix 1050 m which rows are selected by row dπver(s) 1060 Note that row dπver 1060 may be any suitable row selection/dnvmg mechanism, such as the beat frequency techniques descnbed above or mdividual row driver techniques, etc. Row dnver 1060 selects one row at a time from top to bottom. As each row 1070 is selected, all of the columns 1080 are dnven approximately simultaneously in parallel with voltage levels coπespondmg to video data for the selected row. Durmg this time a new video pulse train is propagated down display conductor 740, and when the next row is selected, this new pulse tram is dnven m parallel on columns 1080. Tummg now to Figure 29, an implementation is illustrated in which the rows are selected by the beat frequency method descnbed above and the columns are driven by the parallel column dnve method descnbed above. The rows are addressed one at a tune accordmg to where on second display conductor 840 the row address signals driven by dnvers 805 and 810 combine their respective amplitude to the appropnate voltage to select a row As described above, the pulse width of the row address signals is approximately equal to the propagation delay between adjacent row taps, and the period of the row signals is approximately equal to the propagation delay on second display condcutor 740 from the first row tap-off point through the last row tap-off pomt The rate at which the addressed row changes from one row to another is proportional to the frequency difference between the row address signal dπven by dπver 805 and the row address signal driven by driver 810 Diodes and/or capacitors 832 may be included on the row conductors if necessary, for rectifymg for example Also, note that row and/or column terminators, mdividual pixel elements, etc , are not illustrated for claπty As a row 1070 is selected, voltages are provided on columns 1080 by column conductors 770, as descnbed above The load driver 715 dnve a high load voltage to the capacitor 704 cathodes and diodes 702 are reversed biased (or off) so that the charge stored on capacitors 704 supplies a voltage to columns 1080 Dependmg upon the supplied voltage level, pixels along the selected row are turned on or off Note that the columns are all supplied with the voltages (addressed) approximately simultaneously in parallel for the selected pixel row Shortly before the next row is selected residual charge may be cleared from the columns and capacitors 704 (usmg, e g , a clear dπver and diodes as described in Fig 25) and load dπver 715 then may drive a low voltage on the load signal to capacitors 704 cathodes to load the next series of row pixel voltages, as descnbed above

The prefeπed embodiments have been descnbed with respect to addressmg any of MxN pixel elements aπayed in M rows and N columns m a display In addition to the display types refeπed to earlier herein, the invention also has applicability with various emissive and reflective displays mcludmg electroluminescent units, light emitting diode units, micro-minor units, among others The present mvention may be used with other devices that rely on addressed aπays, include imaging devices such as CCD video cameras, printers, touch screens, etc Further, the present mvention may be used to address any MxN addressable elements that require or implement selectabihty functions for the purpose of pomtmg, savmg, loadmg, storing, retπevrng, aπanging, and displaying Further, the present mvention may also be used to address any of MxN storage cells m an anay of RAM memory elements, or mdeed to address other selectable elements similarly aπayed It will be appreciated by those skilled in the art havmg the benefit of this disclosure that the forms and elements of the mvention shown and descnbed are to be taken as exemplary, presently prefeπed embodiments Vanous modifications and changes may be made without departing from the spirit and scope of the mvention as set forth m the claims It is mtended that the following claims be interpreted to embrace all such modifications and changes

Claims

What claimed is:

1 A display driving apparatus, compnsmg a video driver for dnving a video signal on a first display conductor, a plurality of first diodes, wherem the anode of each first diode is connected to a separate one of a plurality of tap-off pomts on said first display conductor, a plurality of capacitors, wherem the anode of each capacitor is connected to a separate one of a plurality of column conductors, wherem each one of said column conductors is connected to the cathode of a separate one of said first diodes, and a load driver for dnving a load signal to the cathodes of said capacitors, wherem a charge coπespondmg to said video signal at each said tap-off pomt is transfeπed to each respective capacitor when said load signal is m a first state, and wherem said charge is supplied from each said capacitor to each respective column conductor when said load signal is m a second state

2 The apparatus as recited m claim 1, wherem said video signal comprises a series of voltage pulses, wherem each one of said voltage pulse represents whether a display element on a selected row of display elements should be on or off

3 The apparatus as recited in claim 2, wherem the propagation delay on said first display conductor between adjacent tap-off pomts is approximately the same for each parr of adjacent tap-off pomts, and wherem the pulse width of each of said voltage pulses is approximately equal to the propagation delay between adjacent tap-off pomts

4 The apparatus as recited m claim 3, wherem m said first state said load signal is driven at a low voltage for approximately equal to or less than said propagation delay between adjacent tap-off pomts

5 The apparatus as recited m claim 4, wherein m said second state said load signal is dnven at a high voltage relative to said low voltage

6 The apparatus as recited m claim 2, wherem a different series of voltage pulses is driven on said first display conductor at a period approximately equal to the propagation delay of said first display conductor from a first tap-off pomt through a last tap-off pomt on said first display conductor, wherein each said senes of voltage pulses coπesponds to a different row of display elements

7 The apparatus as recited m claim 1 , wherem durmg said second state said column conductors are isolated from said first display conductor by said first diodes

8 The apparatus as recited in claim 7, wherein said video signal comprises a senes of voltage pulses, and wherem duπng said second state a new series of voltage pulses is driven on said first display conductor while charge from a previous series of voltage pulses is transfeπed to said capacitors 9 The apparatus as recited m claim 1, wherem said video signal compnses a voltage waveform m which a low video signal voltage coπesponds to an "off pixel state and a high video signal voltage coπesponds to an "on" pixel state

10 The apparatus as recited in claim 9, wherem the voltage differential from said low video signal voltage to said high video signal voltage is approximately equal to the voltage differential between a low column voltage and a high column voltage on said column conductors

11 The apparatus as recited m claim 10, wherem said load signal transitions between said first state and said second state, wherem said low column voltage or said high column voltage is supplied to said columns conductors by said capacitors durmg said second state, wherem a low column voltage is supplied if a low video signal voltage was present on the coπespondmg said tap-off pomt durmg a just pnor first state and a high column voltage is supplied if a high video signal voltage was present on the coπespondmg said tap-off pomt duπng the just pnor first state

12 The apparatus a recited in claim 11, wherem said high column voltage is sufficient to activate pixels on a selected row of pixels, and wherem said low column voltage is not sufficient to activate pixels on the selected row of pixels

13 The apparatus as recited m claim 9, wherem said load driver drives said load signal to a low load voltage during said first state and to a high load voltage duπng said second state, wherem said low video signal voltage and said high video signal voltage are higher than said low load voltage and said high load voltage respectively by a turn-on voltage of said first diodes

14 The apparatus as recited m claim 1, wherem said capacitors are formed by portions of a conductor trace for said load signal patterned over said column conductors

15 The apparatus as recited claim 1, further compnsmg a clear dnver for dnving a clear signal to discharge said capacitors

16 The apparatus as recited m claim 15, further compnsmg a plurality of second diodes, wherem the anode of each said second diode is connected to a separate one of said column conductors, and wherem the cathode of each said second diode is connected to said clear signal

17 The apparatus as recited in claim 15, wherem said video signal compnses a senes of voltage pulses, wherem each one of said voltage pulse represents whether a display element on a selected row of display elements should be on or off, and wherem said load signal transitions between said first state and said second state each tune a new series of voltage pulses is propagated on said first display conductor

18 The apparatus as recited in claim 17, wherem said clear signal is driven to a low voltage to discharge said capacitors before each transition of said load signal from said second state to said first state 19 The apparatus as recited in claim 1, further compnsmg a second display conductor, a senes of row conductors coupled to said second display conductor, a first row driver for outputtmg a first row addressing signal at a first frequency at a first end of said second display conductor, and a second row driver for outputtmg a second row addressmg signal at a second frequency at a second end of said second display conductor, wherem said first and second row addressmg signal combine to address one row at a time, wherem display elements coupled between an addressed one of row conductors and said column conductors are activated accordmg to said charged supplied to said column conductors

20 The apparatus as recited m claim 19, wherem said row conductors are addressed one after another at an address rate proportional to the difference between said first and second frequencies

21 The apparatus as recited in claim 1, wherem said video driver, first diodes, and capacitors are repeated for a plurality of column sub-cells, wherem a different said video driver dnves a different video signal for each sub- cell, and wherem the charge coπespondmg to each video signal is transfeπed to each respective column in parallel for all said sub-cells

22 The apparatus as recited m claim 21, wherem said load dπver is repeated for each sub-cell so that each sub-cell has a different load dπver

23 The apparatus as recited m claim 22, wherem the cuπent capacity required for each load dnver is proportional to the number of sub-cells

24 The apparatus as recited m claim 21, wherem the cuπent capacity required for each video dnver is proportional to the number of sub-cells