WO2000067518A1

WO2000067518A1 - Method and apparatus for reducing buffer delay

Info

Publication number: WO2000067518A1
Application number: PCT/SE2000/000848
Authority: WO
Inventors: Joachim Roos
Original assignee: Net Insight Ab
Priority date: 1999-05-04
Filing date: 2000-05-03
Publication date: 2000-11-09
Also published as: SE516746C2; SE9901606D0; AU4447300A; SE9901606L

Abstract

The present invention relates to methods and an apparatus for switching data. According to the invention, storage means providing three or more frame buffers are used for temporarily storing frames of slots received via an input port of said apparatus. Read and write pointers are provided to designate which of said frame buffers that are used to be read/write accessed at each point in time. Control means are provided for controlling the operation of said pointer means, said control means being arranged to position said pointers so that the frame buffer currently designated by said write pointer is not the same as the one currently designated by said read pointer. Configuring means are provided for enabling, for slots that are to be transmitted from said output port and that are not to be time switched by said switch, reading of data for said slot from the frame buffer that is located one frame buffer ahead, in said round-robin fashion, of the frame buffer designated by said read pointer.

Description

METHOD AND APPARATUS FOR REDUCING BUFFER DELAY

Technical Field of Invention

The present invention refers to switching of data between at least one input port and at least one output port of a switch, wherein a frame buffer is used to temporarily store frames of data during said switching.

Background of the Invention

In almost any system that switch data between at least one input port and at least one output port, means for temporarily storing said data while in the transfer from said input port to said output ports.

In synchronous systems wherein data on the input and output ports are transferred in essentially fixed length frames, each typically being divided into time slots, use of frame buffers are often preferred for such storing of data .

The function of a frame buffer is to store an entire frame of data during a short period of time and to allow for re-ordering of the slots contained therein. A frame buffer may for example be used to store input frames in such a way that an entire frame of slots is written into the frame buffer with the sequence of slots of the input frame unaffected. When outputted, the slots of the frame are collected from the frame buffer in a random, selec- tive order, thereby providing a desired switching. Alternatively, input slots are written into the frame buffer selectively, thereby providing the desired switching, and the so-created frame of slots is then read out as a whole from the frame buffer. Irrespective of the way in which a frame buffer is used, it is necessary to make sure that new data written into the buffer does not overwrite old data that have not yet been properly read out therefrom, i.e. to ensure so- called buffer consistency. One way to solve this is to synchronize the writing of frames into a frame buffer and the reading of slots from the buffer according to a common frame synchronization signal. However, if there for example is a phase difference between the input frame start signal for the components reading data from the buffer and output frame start signal for the components writing data into the buffer, the task of synchronizing the write and read operations in relation to the buffer becomes more complicated. Another problem with frame buffering is that the larger margin added between the writing of data into a frame buffer and the reading of data from said frame buffer to ensure buffer consistency, the larger will the delay through the switch be. Buffering at higher buffer consistency margins will thus typically imply a negative effect in the form of increased delay.

An object of the invention is therefore to provide an easy and efficient way of synchronizing operation in relation to a frame buffer when switching data between an input and an output port, and especially when switching data between one or more input ports and one or more output ports when both time and space switching are required, while keeping the delay low.

Summary of the Invention The above mentioned and other objects are achieved by the invention as defined in the accompanying claims.

The invention uses a multiple buffer scheme, in which three or more frame buffers, three being the preferred alternative, are provided for each input port. The invention thus uses so-called input port buffering, i.e. frames received via the input port are written sequentially, from frame start to frame end, into said three or more frame buffers. Write and read pointers are provided to designate which particular frame buffer that is currently used for writing of data and which particular frame buffer that is currently used for reading of data, respectively. The pointers are positioned, based upon the phase relationship between said input and output frame synchronization signal, so that they will not point to the same frame buffers simultaneously. The pointers are advanced individually at respective start of frame occurrences in a round robin, modulo-3 (in case of using three frame buffers) fashion.

For the system to be able to perform full time switching of data, i.e. to transmit the last incoming slot of one input frame as the first outgoing slot of an output frame, and vice versa, one frame buffer is needed. In addition, to avoid that this frame buffer is not updated before data has been read therefrom, a second frame buffer is required. In addition, to accommodate for the fact that in networks such as DTM (Dynamic synchronous Transfer Mode) , the input frame and the output frame may be arbitrarily located in phase with respect to each other as long as there is no accumulated phase drift between the two, a third buffer is needed. To be noted, event though use of more than three frame buffers would add even more margins between the read and write operations in relation to the frame buffers, this would also increase the delay through the switch. Use of three frame buffers for each input port is hence considered the most preferred embodiment. According to the invention, for slots to be transmitted from the output port, it is determined if they are configured to receive data from the same respective slot positions via said input port, i.e. if they are not to be time switched by the switch. Based thereupon, reading of data from a respective entry of the frame buffer that is located one frame buffer ahead, in said round-robin fashion, of the frame buffer currently designated by said read pointer is enabled, thereby advantageously reducing buffer delay with respect to such slots. The requirements placed upon the each combination of read and write pointer is that they do not effectively designate the same frame buffer simultaneously. Their momentary positions will typically be such that there is either one frame buffer between the two or no frame buffer between the two. In the former case, reading data on frame ahead of the buffer designated by the read pointer may always be performed. However, in the latter case, the writing of slots into the frame buffer designated by the write pointer will be ahead in time of an output slot clock that causes read-out of slots from the frame buffer designated by the read pointer. If data for an output slot position is to be read from the same slot position of an input frame, the write mechanism will always have had time to pass said slot position of the input frame, and reading of data one frame buffer ahead of the buffer designated by the read pointer may thus be allowed for such slots.

Consequently, for any slot that is switched from the input port associated with the write pointer to the output port associated with the read pointer, and that occupies the same slot positions within each frame recei- ved at the input port as within each frame to be transmitted from the output port, the basic condition for reading one frame ahead of the read pointer will be fulfilled.

Additional requirements may is some cases also be considered before a final decision on permitting reading one frame ahead can be made. For example, if the switch operates in a system wherein a communication channel may be established to include two or more time slots within a frame, and wherein re-ordering is not allowed for data transferred within said channel, the sequential order of the slots of such a channel has to be maintained in order to preserve channel consistency. In such a case, it shall preferably be ensured that reading ahead one buffer according to the invention may and will be performed for slots defining the channel, i.e. requiring that non of the slots defining the channel are time switched, when enabling reading one frame ahead for any one of the slots defining the channel.

In systems wherein an input port and an output port are associated in such a way that all slot positions that are not to be switched from said input port to other output ports, and that are not to be switched from other input ports to said output port, are simply to be forwarded on the same slot position from the input port to the output port, the invention step of reading one frame buffer ahead can be used for all slots that are not time switched as long as they are received from the input port, thus irrespective of whether or not the system has to ensure channel consistency.

An advantage of the invention is thus that it synchronizes write and read operations in relation to the buffer without necessarily hard-locking the input frame synchronization signal to the output frame synchronization signal, the invention however not being limited thereto, while decreasing the delay for such slots that are not to be time switched by the switch.

Another advantage of the invention is that it defines a simple rule for actually permitting use of a frame buffer for read and write simultaneously.

Another advantage of the invention is that this mechanism may be used individually for each input/output port combination. The behavior of a the read accessing of frame buffers used when reading data from an input port to a first output port need then not affect the behavior when read accessing said buffers for reading data from said input port to a second output port.

To be noted, reading ahead one frame could be used also for slots that are time switched, given that the shift in time represented by the subject time switching is smaller that the phase difference between the input and output start of frames. However, embodiments of the invention wherein only non time-switched slots are considered for reading one frame ahead, and wherein the possibility of further evaluating the phase relationship for limiting delay (reading ahead) with respect to time- switched slots as well are ignored, are much simpler to implement and therefore preferred from that point of view.

Furthermore, event though means are provided to make sure that the read pointer and the write pointer do not designate the same frame buffer simultaneously, this does not mean that they may never be allowed to do so. For example, means for providing an additional margin for allowing the pointers to designate the same buffer for a short period of time under strict requirements may be added to the system.

For further exemplifying description of such rules and mechanisms, as well as for further discussion with respect to the operation of a triple buffering scheme of the kind in which the invention is advantageously implemented, reference is made to the Swedish Patent Application SE 9704067-9. As the invention provides for a relaxation of the relationship between the reading and writing of data in relation to a frame memory, and consequently of the relationship between frame synchronization signals of the ports that access said frame memory, the invention is especially advantageous in the context of networks wherein the synchronization requirements are such that each frame synchronization signal may show a limited jitter and may be arbitrarily located in phase in relation to other frame synchronization signals, but may not show any persistent frame drift in relation to other frame synchronization signals. An example of a network of this kind is the DTM (Dynamic synchronous Transfer Mode) network. For further information on such a network, reference is made to "The DTM Gigabit Network", Christer Bohm, Per Lindgren, Lars Ramfelt, and Peter Sjόdin, Journal of High Speed Networks, 3 (2 ): 109-126, 1994. Brief Description of the Drawings

The above mentioned features, embodiments and aspects of the invention will now be further exemplified with reference to the accompanying drawing, wherein: Figs. 1-3 show read/write pointer positions in relation to a set of three frame buffers;

Fig. 4 shows a switch apparatus according to an embodiment of the invention;

Fig. 5 shows configurations of a slot mapping table according to an embodiment of the invention;

Fig. 6 shows a switch apparatus switching between two input and two output ports according to an embodiment of the invention; and

Fig. 7 shows configurations of a slot mapping table according to another embodiment of the invention.

Detailed Description of Preferred Embodiments

To simplify the following description, it will be assumed in the following that data are transferred in essentially fixed length frames, for example having a nominal duration of 125 μs, and that the start of each frame is defined by a frame synchronization signal, also referred to as frame start signal. Furthermore, it is assumed that each frame is divided into a plurality of fixed size, e.g. 64-bit, slots forming a payload that follows the frame start signal within each frame.

Fig. 1 illustrates a frame memory 10 comprising three frame buffers 1-3 for temporarily storing frames of slots that has been received from one input port of a switch. In addition to being used by said input port, the frame memory 10 is typically arranged to be accessed by one or more output ports that use the frame memory for data retrieval when transmitting frames of slots from the respective output port. Each one of the three frame buffers has capacity to store one entire frame of slots. As indicated in Fig. 1, while one frame buffer is being updated, the remaining two buffers may be used for data retrieval. The basis for the frame buffer selection for read and write is the use of a modulo-3 counter, which is incremented on each occurrence of a respective frame start signal. For the input port writing data into the frame memory 10, there is provided a write pointer W designating which one of the three buffers that is currently to be used for storing a frame that is currently to be written into the memory as received via the input port. At start of a new frame to be written into the memory 10, the write pointer W is advanced into designating a next one of the three frame buffers in a round robin, modulo-3 fashion. Similarly, for each output port arranged to read data from the frame memory 10, there is provided a number of read pointers R (one read pointer for each output port) designating which one of the three frame buffers that is currently to be used for reading slots to be transmitted from the respective output port. At each occurrence of the output port frame start signal, indicating that a new frame is to be put together for transmission, the respective read pointer R is advanced into designating a next one of the three frame buffers in a round robin, modulo-3 fashion.

Consequently, a unique read pointer in the range of 0, 1, 2 is provided for each input/output port combina- tion, which makes it possible to offer completely independent retrieval of data in the stored frames at any speed combination as long as the nominal frame frequency is the same (typically 125 μs ) . To be noted, in addition to this read pointer, a unique frame buffer entry address coming from a slot mapping table (to be described more in detail below with reference to Figs 4, 5 and 7) will be provided, at each retrieval, to identify, for each outgoing slot, the specific entry within the frame buffer from which data is to be read. If, for example, it is assumed that the pointer W is currently pointing at frame buffer 3 in Fig. 1, the read pointer R for an output port may point at frame buffer 1, as indicated by the solid line arrow, or at frame buffer 2, as indicated the dotted line arrow. It is now assumed that the relationship between the input and output frame start signals has been determined to be such that the read pointer R will be advanced before the write pointer W is advanced, as a result of the fact that the next occurrence of the output frame start signal is expected to take place before the next occurrence of the input frame start signal. To ensure buffer consistency, the read pointer shall then preferably not be allowed to advanced into designating the same frame buffer as the one currently designated by the read pointer W, i.e. frame buffer 3, since data in frame buffer 3 may then potentially be read before it has been written. Therefore, in the assumed situation, the currently proper position for the read pointer would be to designate frame buffer 1, i.e. the frame buffer that is indicated by the solid line arrow to the left in Fig. 1.

This situation is now described more in detail with reference to Fig. 2, the positioning of the read pointer and the write pointer thus being assumed to be such that the write pointer is pointing two frame buffers ahead of the write pointer. Irrespective of which slot position of the frame buffer 1 that a data reading unit (such as the slot mapping table to be described below) designates, i.e. which entry of the frame buffer that data is to be retrieved from, it would not cause any buffer inconsistency if said retrieval were to be performed one frame ahead, i.e. if data instead were collected from the corresponding entry or slot position of frame buffer 2, as long as such read-ahead were performed for all slot positions defining the same channel and for all frames to be transmitted from the output port that the read pointer refers to. It is then assumed that a next output frame start signal is received, causing the read pointer to advance one step into designating frame buffer 2. This situation is now described more in detail with reference to Fig. 3. As the write pointer now points only one frame buffer ahead of the read pointer, reading of data one frame buffer ahead of the frame buffer currently designated by the read pointer may now only be performed if data is to be retrieved from an entry or slot that has a lower slot position or number than the entry or slot position that is currently being written into, as schematically indicated in Fig. 3. For example, when the output port components are ready to retrieve data for the first slot of the output frame, the write components writing data into frame buffer 3 will already be at the, lets say, entry twenty- one of frame buffer 3. If the mapping instructions for the first slot of the output frame states that data is to be retrieved from the first slot of the input frame, reading one frame ahead of the frame buffer 2 designated by the read pointer will for this slot consequently not necessarily cause buffer inconsistency. Similarly, when the output port components are ready to retrieve data for slot thirty-one of the output frame, the write components writing data into frame buffer 3 will similarly already be at the entry fifty-one of frame buffer 3. If the mapping instructions for slot thirty-one of the output frame states that data is to be retrieved from slot thirty-one of the input frame, reading one frame ahead of the frame buffer 2 designated by the read pointer will still not necessarily cause buffer inconsistency. Consequently, for any data that is switched from the input port associated with the write pointer to the output port associated with the read pointer, and that occupies the same slot positions within each frame received at the input port as within each frame to be transmitted from the output port, i.e. that is not time switched, the basic requirement for reading one frame ahead of the read pointer is fulfilled. Note however that additional requirements may is some cases also have to be considered, for example to ensure channel consistency as will be described further with reference to Fig. 7.

A switch apparatus comprising components and mechanisms used to write and read data from a triple buffer of the kind shown in Figs. 1-3 will now be described with reference to Fig. 4.

Fig. 4 schematically shows a portion 200 of a switch comprising a triple buffer 220, comprising frame buffers 220a-220c, with respect to one input/output port combination. In addition to the triple buffer 220, the apparatus comprises a write buffer select counter 250, an input demultiplexer 210, an input slot counter 240, an output slot counter 260, a read buffer select counter 270, an output multiplexor 230, a buffer sequencing state machine 290, a slot mapping table 280, and a slot mapping configuration controller 285.

According to a preferred embodiment of a switch apparatus having M input ports and N output ports, each input port will be provided with a respective triple buffer 220, write buffer select counter 250, input demultiplexer 210, and input slot counter 240. Also, for each input/output port combination there will be provided a respective read buffer select counter 270, output multiplexor 230, and buffer sequencing state machine 290, and for each output port there will provided a respective output slot counter 260 and slot mapping table 280. Furthermore, each of the N output ports will be provided with a respective additional output multiplexor (not shown) multipexing together data received form the M output multiplexors 230 that operates in relation to input/output port combinations including the subject output port. The description below will be with respect to an input/output port combination in the MxN switch, the overall operation of the MxN switch being readily derived therefrom.

During operation, in Fig. 4, an input frame start signal 208 indicates occurrences of the frame start signal of the frames that are received at the input port and is provided to, the input slor counter 240, the state machine 290, and to the write buffer select counter 250. The write buffer select counter 250 uses the input frame start signal 208 to trigger advancement of a modulo-3 pointer that forms output to the demultiplexer 210. The demultiplexer 210 writes frames 209 received at the input port to a frame buffer as identified by the modulo-3 pointer from the counter 250. The output pointer from the write buffer select counter 250 is also provided to the read buffer select counter 270.

At the same time, the input slot counter 240 controls which entry of the buffer that each sequential slot of the input frame is written into. The input slot counter 240 is reset on each reception of the frame start signal 208 and counts, at the rate of a slot frequency, from a first entry to a last entry of the buffer in sequential order, the slots of each frame thereby being written into the frame buffer to be located therein with maintained sequential slot order.

An output frame start signal 232 indicates occurrences of the frame start signal of frames that are to be transmitted from the output port. It is provided to the output slot counter 260, the state machine 290 and the read buffer select counter 270. The latter uses the frame start signal 232 to trigger advancement of a modulo-3 pointer that forms output to the multiplexor 230. The multiplexor 230 forwards data, collected from the frame buffer identified by the modulo-3 pointer from the counter 270, to the output port.

Based upon the above-mentioned inputs, the state machine 290 is arranged to provide a control signal to the read buffer select counter 270, said control signal being determined by the phase relationship between the input and output frame start signals, as discussed above with reference to Figs. 1-3. Based upon the control signal received from the state machine 290, the read buffer select counter 270 will position its outputted read pointer one or two frame buffers behind the frame buffer identified by the signal from the write buffer select counter 250 and continue using the frame start signal 232 to trigger advancement of the modulo-3 pointer. In addition, if so indicated by an offset signal received from the slot mapping table 280, the read buffer select counter 270 will, for individual, specific slots of an output frame, temporarily increment the pointer provided to the multiplexor 230, thereby causing readout of data one frame buffer ahead for such slots according to the invention.

Moreover, the output slot counter 260 is reset on each reception of the output frame start signal 232 and counts, at the rate of an output slot frequency, to address a first entry to a last entry of a slot mapping table 280 in sequential order, thus stepping through the slot mapping table once for each output frame. For each specific output slot, the output slot counter 260 will thus point at a respective entry of the slot mapping table 280.

The slot mapping table 280 (an example on a design thereof being illustrated more in detail in Figs. 5 and 7) in turn provides, at each entry thereof, a) a respective address to the triple buffer 220, designating from which entry thereof that slot data is to be retrieved, b) a respective identification of which input port, i.e. which triple buffer, that said data is to be retrieved from (i.e. in the multi input port scenario), and c) an offset enabling flag defining said offset signal to the read buffer select counter 270. Note that port identification signal b) is not indicated in Fig. 4. The entries of the slot mapping table 280 thus define the desired slot scheduling of the output frame.

Furthermore, the slot mapping configuration controller 285 is connected to define the content of the slot mapping table 280, thereby defining the switching patterns set-up over the switch apparatus. Furthermore, in an embodiment of the invention, it is the slot mapping configuration controller 285 that defines, by setting the offset enabling flag in the slot mapping table 280, whether or not reading ahead one frame shall be enabled for different slots.

To be noted, when operating in relation to a plurality of input ports, the address provided from the slot mapping table 280 as an entry to the triple buffer 220 may be multicasted to all triple buffers, i.e. to the triple buffer of each input port, and said offset may be multicasted to all read buffer select counters that operates in relation to a combination of the output port associated with said slot mapping table and a respective input port. Furthermore, said identification designating which input port that data is to be retrieved from, will be provided to an additional multiplexor (not shown) collecting data from said read buffer select counters for selection of which one of said data to forward for the specific output slot.

The slot mapping table 280 and its operation will now be described more in detail also with reference to Fig. 5, there being denoted SMT . The table is addressed by the output SC from the output slot counter 260 in Fig. 4. At each respective entry (i.e. corresponding to a respective slot count), a first column "INPUT SLOT" defines the respective entry address to be provided to the triple buffer, designating from which entry of the triple buffer that slot data is to be retrieved for the slot identified by the slot count SC, a second column "INPUT PORT" provides the respective identification of which input port, i.e. which triple buffer, that data is to be retrieved from for the slot identified by the slot count SC, and a third column "OFFSET" providing a respective offset enabling flag defining the offset signal that is provided to the read buffer select counter 270 in Fig. 4.

To be noted in Fig. 5, an in accordance with an embodiment of the invention, the slot mapping configu- ration controller 285 have set content of the slot mapping table SMT so that, if a slot is not to be time switched, i.e. if the identified entry of a triple buffer found in column "INPUT SLOT" is the same as the entry (slot count) of the slot mapping table SMT as such, thus indicating that the slot position from which data is to be collected from the incoming frame is the same as the position of the slot in the outgoing frame in which said data is to be transmitted, the offset enabling flag is set to one (1), thus indicating that reading one frame buffer ahead of the one currently identified by the read buffer select counter 270 is allowed. For example, in Fig. 5, this is the case for entries 0, 1, 2, 6, 7, ..., and 999. Thus the offset is set to one (1) at these entries in the SMT. However, this is not true from entries 3, 4, and 5, the offset thus in this case being set to zero (0) .

In Fig. 6, a switch S has two interfaces to two respective unidirectional communication busses A and B on which frames of slots are transmitted in a multi-access fashion. As illustrated, the switch receives an input frame from bus A comprising slots A1-A4 and an input frame from bus B comprising slots B1-B4. In the frame outputted on bus A, the three first slots A1-A3 has exactly the same positions as in the frame received. Reading of data for these three slot one frame buffer ahead according to the invention, and as described above, is therefore used for these three output slots. However, data for the fourth time slot to be outputted on bitstream A is to be collected from the second slot B2 of the frame received on bus B. Therefore, for this slot, the option of reading one frame buffer ahead will typically not be a valid operation. Consequently, for any channel defined by slots of a frame that is propagated on a multi-access bus, and that is merely to be forwarded by the switch downstream in the same slots and on the same bus that it was received, the conditions will be fulfilled for reading one frame ahead of the read pointer in relation to a triple (or more) buffer of the kind addressed by the invention.

Fig. 7 shows an embodiment of the content of the slot mapping table SMT of Fig. 5 when used in a context wherein communication channels may be established to each include two or more time slots within a frame and wherein re-ordering is not allowed for data transferred within a channel. As the sequential order of the slots of such a channel has to be maintained in order to preserve channel consistency, the flag OFFSET defining reading ahead one buffer according to the invention is only set by the slot mapping configuration controller 285 for a slot if non of the slots defining the channel that the slot is part of are to be time switched and thus if reading ahead one frame can be enabled for all of the slots that define the channel .

As illustrated in Fig. 7, it is assumed that a first channel CHI has been established to be defined by time slot positions 0, 1 and 2 at both the input port 1 and the subject output port served by the subject slot mapping table. As non of the time slots defining this channel CHI are time switched, reading ahead one frame is enabled for all of these time slots, as is indicated by the set OFFSET flag for entries 0, 1, and 2 of the slot mapping table SMT.

At the same time, it is assumed that a second channel CH2 has been established to be defined by time slot positions 6 and 10 at both the input port 4 and positions 6 and 7 and the subject output port served by the subject slot mapping table. Even though one of the two slots defining the channel is not time switched (slot position 6) , the channel does contain one time slot that is time switched (from slot 7 to slot 10) . As this channel CH2 includes slots that are time switched, and as re-ordering is not allowed in this assumed context, reading ahead one frame is not enabled for any one of the time slots defining the channel, as is indicated by the not-set OFFSET flag for entries 6 and 7 of the slot mapping table SMT.

Even though exemplifying embodiment of the invention has been described in detail above, modifications, combinations and alterations thereof may be made, as will be clear to those skilled in the art, within the scope of the invention, which is defined by the accompanying claims .

Claims

1. A method for switching data in a communication network, said method comprising the steps of: temporarily and sequentially storing frames of slots of data received via an input port of a switch in three or more frame buffers; providing a write pointer designating which one of said three or more frame buffers that is to be used for storing a frame of slots received via said input port; providing a read pointer designating which one of said three or more frame buffers that is to be used for reading data to be transmitted in a frame from an output port of said switch; advancing said write pointer into designating a next one of said frame buffers in a round-robin fashion at the start of a next frame of slots to be stored in said three of more frame buffers; advancing said read pointer into designating a next one of said frame buffers in a round-robin fashion at the start of a next frame of slots to be read for transmission from said output port; positioning said pointers so that no one of said pointers will be advanced to effectively designate the same frame buffer as the other one of said pointers; and determining if a slot to be transmitted from said output port is not to be time switched by said switch and based thereupon enabling reading of data for said slot from the frame buffer that is located one frame buffer ahead, in said round-robin fashion, of the frame buffer designated by said read pointer.

2. A method as claimed in claim 1, said determining step comprising determining, for a channel defined by one or more slots in a frame to be transmitted from said output port, if non of said one or more slots is to be time switched by said switch and, based thereupon, enabling reading of data for all of said one or more slots from the frame buffer that is located one frame buffer ahead, in said round-robin fashion, of the frame buffer designated by said read pointer.

3. A method as claimed in claim 1, said determining step comprising enabling, for all slots that is to be transmitted from said output port and is not to be time switched by said switch, reading of data from the frame buffer that is located one frame buffer ahead, in said round-robin fashion, of the frame buffer designated by said read pointer.

4. A method as claimed in claim 1, said determining step comprising enabling, for all slots that is to be transmitted from said output port, having been received from said input port, said input port forming an input/output interface together with said output port, while not being time switched by said switch, reading of data from the frame buffer that is located one frame buffer ahead, in said round-robin fashion, of the frame buffer designated by said read pointer.

5. A method as claimed in any one of the preceding claims, wherein said storing step comprises storing the n:th slot of a frame received via said input port in a n:th entry of the frame buffer designated by said write pointer at a respective point in time.

6. A method as claimed in any one of the preceding claims, further comprising the step of defining, for each slot of frames to be transmitted from said output port, if data for the slot shall be retrieved from said three of more buffers receiving frames from said input port and, if so, from which entry thereof that said data shall be retrieved.

7. A method as claimed in any one of the preceding claims, wherein said positioning step comprises detecting which one of said first signal and said second signal that is received first in time and adjusting one or both of said pointers so that, if said first signal is received first, the frame buffer designated by said write pointer is at least two frame buffers ahead, in said round-robin fashion, of the frame buffer designated by said read pointer, or, if said second signal is received first, the frame buffer designated by said read pointer is at least two frame buffers ahead, in said round-robin fashion, of the frame buffer designated by said write pointer.

8. A method for switching data in a communication network, said method comprising the steps of: temporarily and sequentially storing frames of slots of data received via one or more input ports of a switch in one or more respective sets of three or more frame buffers; providing, for each of said input ports, a write pointer designating which one of the respective set of three or more frame buffers that is to be used for storing a frame of slots received via the input port; providing, for each combination of input and output port, a read pointer designating which one of the set of three or more frame buffers storing data from the input port that is currently to be used for reading data to be transmitted in a frame from the output port; advancing each write pointer into designating a next one of the respective set of three or more frame buffers in a round-robin fashion at the start of a next frame of slots to be stored in the respective set of three or more frame buffers; advancing each read pointer into designating a next one of the respective set of three or more frame buffers in a round-robin fashion at the start of a next frame of slots to be read for transmission from the output port associated with the read pointer; positioning said pointers so that no read pointer will ever advance into effectively designating the same frame buffer as a write pointer and vice versa; and determining if a slot that is to be transmitted from an output port is not to be time switched by said switch and, based thereupon, enabling reading of data for said slot from frame buffers that are located one frame buffer ahead, in said round-robin fashion, of the frame buffers designated by the read pointers associated with said output port.

9. A method as claimed in claim 8, said determining step comprising determining, for a channel defined by one or more slots in a frame to be transmitted from an output port of the switch, if non of said one or more slots is to be time switched by said switch and, based thereupon, enabling reading of data for all of said one or more slots from the frame buffers that are located one frame buffer ahead, in said round-robin fashion, of the frame buffers designated by the read pointers associated with said output port.

10. A method as claimed in claim 8, said determining step comprising enabling, for all slot that are to be transmitted from an output port of said switch and that is not to be time switched by said switch, reading of data from frame buffers that are located one frame buffer ahead, in said round-robin fashion, of the frame buffers designated by the read pointers associated with said output port .

11. A method as claimed in claim 8, 9, or 10, where- in said storing step comprises storing the n:th slot of a frame received via an input port in a n:th entry of the frame buffer designated by the write pointer associated with the input port.

12. A method as claimed in claim 8, 9, 10, or 11, further comprising defining, for each slot of frames to be transmitted from an output port of the switch, which set of three of more frame buffers, and from which entry thereof, that said data shall be retrieved from.

13. A method as claimed in any one of the preceding claims, wherein an n:th slot of frames that is to be transmitted from an output port of said switch is defined as not being time switched by said switch if configured to receive data from the n:th slot of frames received via an input port of said switch.

14. An apparatus for switching data in a communication network, said apparatus comprising: one or more sets of three or more frame buffers, each set being arranged for temporarily and sequentially storing frames of slots of data received via a respective input port; write pointer means (250), one in relation to each input port for designating which one of the set of three or more frame buffers that is used for storing data from the input port that is currently to be used for storing a frame of slots received via the input port, said write pointer means being arranged to advance to designate a next one of said three or more frame buffers in a round- robin fashion at the start of a next frame of slots to be stored in said three of more frame buffers as received from the input port; read pointer means (270), one in relation to each combination of input and output port for designating, which one of the three or more frame buffers associated with the respective input port that is currently to be used for reading data to be transmitted in a frame from the respective output port and being arranged to advance to designate next one of the input port's three or more frame buffers in a round-robin fashion at the start of a next frame of slots to be read for transmission from the output port; control means (290) for controlling the operation of said pointer means to position said pointers so that no one of said read pointers will be advanced to effectively designate the same frame buffer as a write pointer and vice versa; and configuring means (280, 285) for determining if a slot a slot to be transmitted from an output port of said apparatus is not to be time-switched by said apparatus and enabling reading of data for said slot from frame buffers located one frame buffer ahead, in said round- robin fashion, of the frame buffers designated by read pointer means associated with said output port based thereupon.

15. An apparatus as claimed in claim 14, said configuring means (280, 285) being arranged to determine if a slot to be transmitted from an output port forms part of a channel, being defined by one or more time slots within a frame, for which non of the time slots defining said channel is to be time-switched by said apparatus and only if so enable reading of data for said slot from frame buffers located one frame buffer ahead, in said round-robin fashion, of the frame buffers designated by the read pointer means associated with said output port.

16. An apparatus as claimed in claim 14, 15, or 16, said configuring means comprising means (280) for defining, for each slot of frames to be transmitted from said output port, from which set of three of more frame buffers, and from which entry thereof, that data for said slot shall be read from.