WO2001004746A1 - Process of formation, memorization and reuse, in execution time, of sequences of dynamic instructions in computers - Google Patents

Process of formation, memorization and reuse, in execution time, of sequences of dynamic instructions in computers Download PDF

Info

Publication number
WO2001004746A1
WO2001004746A1 PCT/BR2000/000074 BR0000074W WO0104746A1 WO 2001004746 A1 WO2001004746 A1 WO 2001004746A1 BR 0000074 W BR0000074 W BR 0000074W WO 0104746 A1 WO0104746 A1 WO 0104746A1
Authority
WO
WIPO (PCT)
Prior art keywords
instructions
memo
reuse
memorization
sequence
Prior art date
Application number
PCT/BR2000/000074
Other languages
French (fr)
Inventor
Felipe Maia GALVÃO FRANÇA
Teodoro Amarildo
Original Assignee
Coppe/Ufrj - Coordenação Dos Programas De Pós Graduação De Engenharia Da Universidade Federal Do Rio De Janeiro
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Coppe/Ufrj - Coordenação Dos Programas De Pós Graduação De Engenharia Da Universidade Federal Do Rio De Janeiro filed Critical Coppe/Ufrj - Coordenação Dos Programas De Pós Graduação De Engenharia Da Universidade Federal Do Rio De Janeiro
Priority to AU57990/00A priority Critical patent/AU5799000A/en
Publication of WO2001004746A1 publication Critical patent/WO2001004746A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3808Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824Operand accessing
    • G06F9/383Operand prefetching

Definitions

  • the present invention refers to a process of definition of a digital computational system capable of forming (selecting) , memorizing and reusing, in execution time (dynamically) , dynamic sequences of instructions, hence eliminating the necessity of re- executing such sequences when presenting input entries that have been priviously observed and, consequently, producing the same output; note that: dynamic instructions are characterized as instances of static instructions in execution time; a sequence of dynamic instructions is defined as a succession of dynamic instructions, such succession is ordered by the flux of execution; input of a sequence of dynamic instructions is defined as the set of values attributed to the source operands of each dynamic instruction in the sequence; and, output of a sequence dynamic of instructions is defined as the set of values attributed to each result operand of each dynamic instruction in the sequence.
  • the invention aims to a process of definition of a digital computational system capable of forming (selecting) , memorizing and reusing, in execution time (dynamically) , dynamic sequences of instructions, hence eliminating the necessity of re- executing
  • the reduction of program execution time, using memorization of results in computers, is basically effected through the Memorization and the consequent Reuse of Subrotines, functions and dynamic instructions, aiming at the reduction of the total amount of necessary instructions to the execution of programs, mantaining, however, the correction of the results.
  • Some procedures for Memorizing and Reusing Subrotines, Functions and Dynamic Instructions already exists, however, no process has been explored for the Formation, Memorization and Reuse of sequences of dynamic instructions where the goal is Forming (through selection) , Memorizing and Reusing at execution time, of sequences of dynamic instructions built from the re-execution of dynamic instructions with input values that ⁇ rave been already observed.
  • the procedures for Reuse of Subrotines and Functions usually present as main obstaxile the procesLs of Selecting of such Subrotines and Functions.
  • the Selection of Subrotines and Functions to be memorized is effected in a static manner, by manually observing the encoding and the semanthics of the program, or with the aid of execution statistics or assited by the compiler or done in an incremental manner.
  • the application of these procedures is not generic and is normally customized and dependent on the exeistence of such elements in a given program.
  • the Procedures for Selection, Memorization and Reuse of dynamic instructions applies Memorization and Reuse from particular schemes based on Memorization tables with a determined number of entries, that memorizes the dynamic instructions, where in the best case in particular conditions for all the schemes, at most four (4) dynamic instructions are reused at once.
  • This invention presents a simple and efficient process for Selecting, Memorizing, and Reusing, at execution time, sequences of dynamic instructions of any size (where the size of a sequence of dynamic instructions refers to the amount of dynamic instructions included in the sequence) , and in comparison to previous work, we obtain a higher reuse percentual from the application of this process.
  • the existing Processes for the Formation, Memorization and Reuse applied to programs are: 1.
  • Hardware Instruction Memorization Where in programs in general: the Selection, Memorization and Reuse are effected on dynamic instructions via hardware at execution time.
  • the existing schemes to effect the reuse of instructions differ form each other basically by: the information that is stored in the Memorization tables, the access method to the tables and invalidations performed.
  • the Sv scheme reuses instructions that present values for the input operands (registers) previously observed;
  • the Sn scheme reuses instructions based on the name of the operands (registers), i.e., an instruction reuses a value that has instantiated an operand if that operand value has not been altered; 3.3.
  • the Sn+d scheme reuses instructions like Sn, however, it also manipulates chains of dependant instructions, more specifically, chains of instructions that have true data dependancy among themselves; 3.4.
  • the Me oing scheme applies reuse in a restricted form which is exclusive to instructions with high execution latency (multiplication, division, etc) , being only valid fro instructions where the cost of reuse is smaller than the cost of execution (considering that cost is measured by time) .
  • the process that is the object of this invention allows for the employment of hardware, typically an electronic circuit, at execution time for the Formation, Memorization and Reuse of sequences of dynamic instructions.
  • a sequence of dynamic instructions is characterized as being typically constituted by two (2) or three (3) instructions (sequences containing only one (1) or more than three (3) instructions can also be treated by the process) .
  • the goal of the process is to directly reuse the results from the re- execution of dynamic instructions which present previously memorized entries, instead of re-executing all the instructions of the sequence, this way the total number of executed instructions in a given program is reduced, thence a reduction of total execution time is obtained.
  • the goal of the present invention is to provide a process for Formation, Memorization and Reuse of sequences of dynamic instructions, which is basically composed by four (4) distinct stages:
  • Buffer_T be a table that will temporarily store elements of Memo_table_I in such a way that these instructions are stored consecutively in its entries, i.e., will store the sequence of the dynamic instructions being formed.
  • R_Reg - register that stores the result of the operation.
  • SI _Reg - register that stores the first operand of the instruction.
  • S2 _Reg - register that stores the second operand of the instruction.
  • I - If 0 indicates that the instruction has an operand in a register and the second operand is immediate.
  • NPC_L memory address of the next instruction to be executed after the last instruction of the sequence.
  • OS Tags - register used by the exit scope IS_Val - values of the registers indicated by IS_Tags.
  • PROCEDURES FOR INDEXATION AND UPDATING OF THE MEMORIZATION TABLES The Memorization tables will be indexed by keys according to the fields of the table in question. One entry of Memo_table_I will be indexed by the association of the data fields PC + Sl_Val + S2_Val . The current instruction instantiated for execution will be found in Memo_table_I if its memory address (PC) and associated values to its input operands correspond to the fields PC, Sl_val and S2_Val of Memo_table__I, respectively.
  • Memo_table_T One entry of Memo_table_T will be indexed by the association of the fields PC_F + IS_Tags + IS_Val.
  • the current dynamic instruction instantiated for execution will be found in Memo_table_T if its memory address (PC) matches the field PC_F of an entry of Memo_table_T and, in such an entry, the values of the registers of the registers file of the target computer indicated by the fields IS_Tags (of the same entry selected by PC) coincide with the fields IS_Val (of the same entry) that correspond to the input scope of the stored sequence.
  • PC memory address
  • Buffer_T will only play the roll of temporarily storing the identified sequence, this temporary storage will have the goal of extracting from the complete sequence solely the information that will be relevant to the Reuse of the sequence and to the storage of this information in Memo_table_T .
  • the descritpion of the updating operations on the tables is based on a First-In-First-Out - FIFO - strategy (other updating strategies can be used) , that is, if there are free entries in the tables they could house new dynamic instructions or information about the sequences of dynamic instructions to be inserted, otherwise the oldest entry (that is, the one first inserted) will be expunged to give space to the new required insertion, and this lastest insertion will be considered the most recent one.
  • the algorithm of Formation, Memorization and Reuse of sequences of dynamic instructions is based on two (2) search procedures performed on the tables Memo_table_I and Memo table T.
  • the issuing of these search procedures can occur concurrently and, moreover, asynchronously and/or subdivided in various stages of a pipeline that has a parallel to the stages of the target computer architecture.
  • Figure 5 shows a sequence of redundant instructions, being this sequence stored in Buffer_T and delimited by the address interval [104,116].
  • Figure 6 shows a new entry included in Memo table T from the sequence stored in Buffer_T ( Figure 5) ; this new entry will store information about the sequence built and this procedure corresponds to the phase of memorization of the sequence of dynamic instructions.
  • sequence reuse in this example will occur whenever a re-execution of instruction 104 occurs and, in this re-execution, the input scope operand values of the sequence coincide with the values of the respective operands in the registers file of the target computer, that is, if there is an entry in Memo_table_T containing the value 104 in the field PC_F and the registers file of the target computer has in its registers identified by the field IS_Tags of the same entry, the same values stored in the field IS_Val from the same entry as shown in Figure 7.
  • the reuse action will proceed by writing the value stored in the field NPC_L onto the PC of the target computer, altering, in this way, the execution flux and re-writing the registers (of the registers file of the target computer) indicated by the field OS_Tags with the values stored in field OS_Val, restoring, in this way, the machine context for the execution of the instruction to the reused sequence. From the exposed above, the instructions of a redundant sequence will be not executed since they were reused all at once, as illustrated by Figure 8.
  • the size of input and output scopes are, each, smaller or equal to four

Abstract

This is about a process for the formation, memorization and reuse, at execution time, of sequences of dynamic instructions aiming at reducing the number of dynamic instructions executed by a program, in order to eliminate the need for re-executing redundant instructions (instructions that execute, more than once, upon the same values at its input operands) included in the sequence whenever this sequence present, as input scope, values that were already seen and stored at memorization tables. This process does not need to effect invalidations upon memorization table entries and its use is not limited to chains of dependant instructions. This process reduces the number of dynamic instructions needed to be executed by a target program, reducing, in this way, the total execution time of such program and keeping the correctness of the results. The invention also refers to an electronic device for the implementation of the process.

Description

Description of the Invention "PROCESS OF FORMATION, MEMORIZATION AND REUSE, IN EXECUTION TIME, OF SEQUENCES OF DYNAMIC INSTRUCTIONS IN COMPUTERS" TECNICAL FIELD The present invention refers to a process of definition of a digital computational system capable of forming (selecting) , memorizing and reusing, in execution time (dynamically) , dynamic sequences of instructions, hence eliminating the necessity of re- executing such sequences when presenting input entries that have been priviously observed and, consequently, producing the same output; note that: dynamic instructions are caracterized as instances of static instructions in execution time; a sequence of dynamic instructions is defined as a succession of dynamic instructions, such succession is ordered by the flux of execution; input of a sequence of dynamic instructions is defined as the set of values attributed to the source operands of each dynamic instruction in the sequence; and, output of a sequence dynamic of instructions is defined as the set of values attributed to each result operand of each dynamic instruction in the sequence. The invention aims at the conception of a digital eletronic circuit wich performs the task refered to above. PREVIOUS TECHNIQUES
The reduction of program execution time, using memorization of results in computers, is basically effected through the Memorization and the consequent Reuse of Subrotines, functions and dynamic instructions, aiming at the reduction of the total amount of necessary instructions to the execution of programs, mantaining, however, the correction of the results. Some procedures for Memorizing and Reusing Subrotines, Functions and Dynamic Instructions already exists, however, no process has been explored for the Formation, Memorization and Reuse of sequences of dynamic instructions where the goal is Forming (through selection) , Memorizing and Reusing at execution time, of sequences of dynamic instructions built from the re-execution of dynamic instructions with input values that ±rave been already observed. The procedures for Reuse of Subrotines and Functions usually present as main obstaxile the procesLs of Selecting of such Subrotines and Functions. The Selection of Subrotines and Functions to be memorized is effected in a static manner, by manually observing the encoding and the semanthics of the program, or with the aid of execution statistics or assited by the compiler or done in an incremental manner. The application of these procedures is not generic and is normally customized and dependent on the exeistence of such elements in a given program. The Procedures for Selection, Memorization and Reuse of dynamic instructions, applies Memorization and Reuse from particular schemes based on Memorization tables with a determined number of entries, that memorizes the dynamic instructions, where in the best case in particular conditions for all the schemes, at most four (4) dynamic instructions are reused at once. This invention presents a simple and efficient process for Selecting, Memorizing, and Reusing, at execution time, sequences of dynamic instructions of any size (where the size of a sequence of dynamic instructions refers to the amount of dynamic instructions included in the sequence) , and in comparison to previous work, we obtain a higher reuse percentual from the application of this process. The existing Processes for the Formation, Memorization and Reuse applied to programs are: 1. Software Function Memoization - Where in a given program, the Subrotines or Functions that are canditates to be reused are previously selected in a statical form, and the functions of Memorization and Reuse are effected by pieces of code that are inserted in the target program.
2. Hardware Function Memoization - Where in a given program the Subrotines or Functions that are candidates to be reused are previously selected in statical form, and the functions of Memorization and Reuse are effected by a piece of hardware that is activated by instructions that are inserted in the code of the target program.
3. Hardware Instruction Memorization - Where in programs in general: the Selection, Memorization and Reuse are effected on dynamic instructions via hardware at execution time. The existing schemes to effect the reuse of instructions differ form each other basically by: the information that is stored in the Memorization tables, the access method to the tables and invalidations performed.
3.1. The Sv scheme reuses instructions that present values for the input operands (registers) previously observed;
3.2. The Sn scheme reuses instructions based on the name of the operands (registers), i.e., an instruction reuses a value that has instantiated an operand if that operand value has not been altered; 3.3. The Sn+d scheme reuses instructions like Sn, however, it also manipulates chains of dependant instructions, more specifically, chains of instructions that have true data dependancy among themselves; 3.4. The Me oing scheme applies reuse in a restricted form which is exclusive to instructions with high execution latency (multiplication, division, etc) , being only valid fro instructions where the cost of reuse is smaller than the cost of execution (considering that cost is mesured by time) .
4. Hardware Basic Block Reuse - Where for programs in general: the Selection, Memorization and Reuse are effected on basic blocks, that is, sequences of instructions delimited by one only entry point and one only exit jpoint. The basic blocks are partially selected and previously marked in static form by the compiler and/or dynamically by hardware. During the execution of a program the basic blocks will be memorized with their respective entry and exit scopes, including memory reading/writing instructions that have to be executed in orde to validade the reuse. This method restricts memorization to pieces of code with well defined execution flow. All the schemes present above have their utilization restricted either to isolated instructions or to basic blocks. DESCRIPTION OF THE INVENTION
The process that is the object of this invention allows for the employment of hardware, typically an electronic circuit, at execution time for the Formation, Memorization and Reuse of sequences of dynamic instructions. In this process, a sequence of dynamic instructions is characterized as being typically constituted by two (2) or three (3) instructions (sequences containing only one (1) or more than three (3) instructions can also be treated by the process) . The goal of the process is to directly reuse the results from the re- execution of dynamic instructions which present previously memorized entries, instead of re-executing all the instructions of the sequence, this way the total number of executed instructions in a given program is reduced, thence a reduction of total execution time is obtained. This way, the goal of the present invention is to provide a process for Formation, Memorization and Reuse of sequences of dynamic instructions, which is basically composed by four (4) distinct stages:
(i) SELECTION OF THE INSTRUCTION SET FOR THE APPLICATION OF THE PROCESS The application of the process will be restricted to a subset of the overall instruction set of the target computer, which could be enlarged or reduced, depending on the architectural characteristics of the target computer. The basic instructions that are manipulated by the process are classified in groups according to their functionality, this groups are defined as the group of arithmetical instructions, the group of logical instructions, the group of instructions for execution flow control, and the group of instructions for local and main memory manipulation. The sequences of dynamic instructions will be composed by instructions belonging to these groups and to the union of such groups will be demoninated as the Selection Set. (ii) DEFINITION AND REPRESENTATION OF THE MEMORIZATION TABLES The memorization tables will be defined and represented according to the architectural characteristics of the target computer, such definition will consider the model of a LOAD/STORE architecture (where the instruction operands will allways be in registers internal to the target computer) , nevertheless, the definition could be applied to other architectural models. Let Memo_table_I be a table that will store the already executed dynamic instructions, where each stored instruction will be instantiated with respective values for the input operands and output results from its previous execution. Let Memo_table_T a table that will store information about sequences of dynamic instructions where all of the instructions of each sequence have already been executed and are or had been stored in Memo_table_I, with the goal of the application of Reuse.
Let Buffer_T be a table that will temporarily store elements of Memo_table_I in such a way that these instructions are stored consecutively in its entries, i.e., will store the sequence of the dynamic instructions being formed.
Description of the fields of one entry of Memo_table_I from
Figure (1) :
PC - memory address of the instruction. N_PC - memory address of the next instruction to be executed.
R_Reg - register that stores the result of the operation.
SI _Reg - register that stores the first operand of the instruction. S2 _Reg - register that stores the second operand of the instruction.
R_Val - value of the result produced by the execution of the instruction.
Sl_Val - value of the first operand of the instruction. S2__Val - value of the second operand of the instruction.
I - If = 0 indicates that the instruction has an operand in a register and the second operand is immediate.
If = 1 indicates that the instruction has the two operands in registers. Description of the fields of an entry of Memo_table__T from
Figure (2) :
PC_F - memory address of the first instruction of the sequence.
NPC_L - memory address of the next instruction to be executed after the last instruction of the sequence.
IS_Tags - registers used by the entry scope.
OS Tags - register used by the exit scope. IS_Val - values of the registers indicated by IS_Tags. OS_Val - values of the registers indicated by 0S_Tags. (iii) PROCEDURES FOR INDEXATION AND UPDATING OF THE MEMORIZATION TABLES The Memorization tables will be indexed by keys according to the fields of the table in question. One entry of Memo_table_I will be indexed by the association of the data fields PC + Sl_Val + S2_Val . The current instruction instantiated for execution will be found in Memo_table_I if its memory address (PC) and associated values to its input operands correspond to the fields PC, Sl_val and S2_Val of Memo_table__I, respectively. One entry of Memo_table_T will be indexed by the association of the fields PC_F + IS_Tags + IS_Val. The current dynamic instruction instantiated for execution will be found in Memo_table_T if its memory address (PC) matches the field PC_F of an entry of Memo_table_T and, in such an entry, the values of the registers of the registers file of the target computer indicated by the fields IS_Tags (of the same entry selected by PC) coincide with the fields IS_Val (of the same entry) that correspond to the input scope of the stored sequence. Buffer_T will only play the roll of temporarily storing the identified sequence, this temporary storage will have the goal of extracting from the complete sequence solely the information that will be relevant to the Reuse of the sequence and to the storage of this information in Memo_table_T . The descritpion of the updating operations on the tables (Memo_table_I and Memo_table_T) is based on a First-In-First-Out - FIFO - strategy (other updating strategies can be used) , that is, if there are free entries in the tables they could house new dynamic instructions or information about the sequences of dynamic instructions to be inserted, otherwise the oldest entry (that is, the one first inserted) will be expunged to give space to the new required insertion, and this lastest insertion will be considered the most recent one.
(iv) ALGORITHM OF FORMATION, MEMORIZATION AND REUSE OF SEQUENCES OF DYNAMIC INSTRUCTIONS
The algorithm of Formation, Memorization and Reuse of sequences of dynamic instructions is based on two (2) search procedures performed on the tables Memo_table_I and Memo table T. The issuing of these search procedures can occur concurrently and, moreover, asynchronously and/or subdivided in various stages of a pipeline that has a parallel to the stages of the target computer architecture. Consider the tables Memo_table_I, Memo_table_T and Buffer_T. For each instruction to be executed do: Search in Memo_table_I :
(1) Check if the current instruction belongs to the Selection set;
(2) If (1) is false then any sequence that is being formed in Buffer_T is ended, and the information extracted about such a sequence is stored in Memo_table_T, and Buffer_T is free for the storage of a new sequence; end of the algorithm; Else continue;
(3) Check if the current instantiated instruction and its operands is stored in Memo__table_I ;
(4) If (3) is false then include the current instantiated instruction in Memo_table_I and end any sequence being formed in Buffer_T and the information extracted about such a sequence is stored in Memo_table_T, and Buffer_T is free for the storage of a new sequence; end of the algorithm; Else the instruction in question is redundant and it will initiate or be added to the formation of the current sequence, being included in Buffer T. Search in Memo_table_T :
(1) Check if the current instruction belongs to the Selection set;
(2) If (1) is false then do not search in Memo_table_T; end of the algorithm; Else continue;
(3) Check if PC (Program Counter) of the current instruction occurs at any of the Memo_table_T entries;
(4) If (3) is true then select the first entry which input scope, indicated by IS_Tags and IS_Vals, corresponds to the state of the registers file of the target computer;
(5) If (4) is true (that is, there exists at least one valid entry) then, considering the entry in question, load the PC of the target computer with the value of NPC_L field and update the registers file of the target computer with the output scope given by 0S_Tags and OS_Vals fields. EXAMPLE
For the Formation of the sequences of the dynamic instructions to be memorized, will be considered the piece of code presented in Figure 3, where for each instantiated instruction (with the values given to its operands) by the execution of this piece of code, such instructions will be stored at Memo_table_I entries (if the instruction belongs to the Selection set) as shown by Figure 4. An instruction will be considered redundant if at a re-execution of such instruction, an instance of this instruction is already stored in Memo_table_I, in this case the instruction is candidate to initiate or to add to the formation of a sequence of dynamic instructions, being this instruction sequentially stored in Buffer_T (which stores a sequence of redundant instructions) . Figure 5 shows a sequence of redundant instructions, being this sequence stored in Buffer_T and delimited by the address interval [104,116]. Figure 6 shows a new entry included in Memo table T from the sequence stored in Buffer_T (Figure 5) ; this new entry will store information about the sequence built and this procedure corresponds to the phase of memorization of the sequence of dynamic instructions. The sequence reuse in this example will occur whenever a re-execution of instruction 104 occurs and, in this re-execution, the input scope operand values of the sequence coincide with the values of the respective operands in the registers file of the target computer, that is, if there is an entry in Memo_table_T containing the value 104 in the field PC_F and the registers file of the target computer has in its registers identified by the field IS_Tags of the same entry, the same values stored in the field IS_Val from the same entry as shown in Figure 7. In this case, considering the already identified Memo_table_T entry, the reuse action will proceed by writing the value stored in the field NPC_L onto the PC of the target computer, altering, in this way, the execution flux and re-writing the registers (of the registers file of the target computer) indicated by the field OS_Tags with the values stored in field OS_Val, restoring, in this way, the machine context for the execution of the instruction to the reused sequence. From the exposed above, the instructions of a redundant sequence will be not executed since they were reused all at once, as illustrated by Figure 8.
ADVANTAGES OF THE REINVINDICATED PROCESS
The process of Formation, Memorization and Reuse of sequences of dynamic instructions described here is efficient on exployting the repetitive behavior of pieces of program code that arefrequently re-executed from the same entries, on the following aspects: (i) There is no need for identifying, building or selecting, in a statical manner, sequences of instructions likely to repeat themselves;
(ii) The reuse of a sequence of dynamic instructions is equivalent to the reuse of all instructions of such sequence all at once, so that the cost of re-executing all these instructions is reduced to the cost of execution of a single instruction, considering the cases in which the cost of reuse of one (1) instruction is equal to the cost of execution of the same instruction (cost in time) .
(iii) There is no need for instantiating all the instructions of a sequence of dynamic instructions that will be executed since the reuse of sequences is based on input scopes and, as such scopes determine the flux and results of all the instructions to be executed, the execution of any instruction belonging to the sequence is not necessary to validate its reuse.
(iv) The reuse of sequences of dynamic instructions is not restricted to the amount of simultaneous accesses that can be done to a memorization table, to the dynamic instructions individually.
(v) The reuse process i rirrorlucad i_s bl e to xeduce the amount of hardware and execution bottlenecks on effecting: (a) Register Renaming, since the instructions of a reused sequence that were not executed, did not need to rename their output registers^ aliviating this way the renaming unit; (b) Branch Prediction, since branches included in such - used -sequen es a re .sol ved eEorehand, reducing, in this way, the latency related to brach resolution; (c) Use of -fiinctienal Units., since -by -avoi ding the _re--execution of instructions of a redundant sequence, the allocation of Functional Units to the instructions ot such -sequence is avoided; (d) Resolution of True Data Dependencies, since the dependent instructions included in a redundant sequence will be executed all at once, that is, in the same cycle.
(vi) Other types of instructions can be included in the reuse process, so that incremental enhancement is allowed. Implementation to any target computer is feasable since in
99.6% of the sequences of dynamic instructions captured and reused by the process (measured in tests) , the size of input and output scopes are, each, smaller or equal to four
(4) registers.. (vii) Potential gains in terms of power consumption are expected since functional units and/or pipeline stages that are spared from re-executing redundant sequences of dynamic instructions could be switched-off if appropriate power- saving mechanisms would be employed in conjunction to the new reuse process.

Claims

1. PROCESS OF FORMATION, MEMORIZATION AND REUSE, IN EXECUTION TIME, OF SEQUENCES OF DYNAMIC INSTRUCTIONS IN COMPUTERS, characterized by reuse, during execution time, of sequences of dynamic instructions containing, not in a exclusive manner, one or more instructions of the control of execution flow type, i.e., instructions that have as main characteristic the ability of modifying the program counter (PC) of the target computer.
2. PROCESS OF FORMATION, MEMORIZATION AND REUSE, IN EXECUTION TIME, OF SEQUENCES OF DYNAMIC INSTRUCTIONS IN COMPUTERS, characterized by selecting a reduced subset, when compared to related methodologies, of instruction types candidates to the reuse by the target computer, excluding instructions types such as (i) main memory access; (ii) floating-point operations; and (iii) priviledged (typically for the support of the Operating System) ; with the possibility of enlarging or reducing this selection, depending on the architectural characteristics of the target computer, without compromising the correctness of the process, which in this case may not necessarily display the same efficiency, of formation, memorization and reuse at execution time, of sequences of dynamic instructions composed by instructions pertaining to the remaining types, that is, typically types of (iv) arithmetical instructions, (v) logical and shifts instructions, and (vi) instructions of execution flow control, calls to and returns from subrotines.
3. PROCESS OF FORMATION, MEMORIZATION
AND REUSE, IN EXECUTION TIME, OF SEQUENCES OF DYNAMIC INSTRUCTIONS IN COMPUTERS, according to Claim 1, characterized by defining the concurrent use of three different types of memorization tables, that are: (i) Memo_table_I a type of table that will store already executed dynamic instructions, where each instruction that is stored will be instantiated with its respective values for the input operands and output results resulting from its execution; (ii) Memo_table_T a type of table that will store information about sequences of dynamic instructions where all instructions of the sequence have already been executed and are or have been stored in Memo_table_I aiming at the application of Reuse, and; (iii) Buffer_T a type of table that will temporarily store elements of Memo_table_I consecutively in its entries, that is, it will store a sequence of dynamic instructions in the process of formation.
4. PROCESS OF FORMATION, MEMORIZATION
AND REUSE, IN EXECUTION TIME, OF SEQUENCES OF DYNAMIC INSTRUCTIONS IN COMPUTERS, according to Claim 3, characterized by effecting the indexation and updating of the memorization tables, in such a way that the memorization tables will be indexed by keys according to the fields of the table in question; one entry of Memo_table_I will be indexed by the association of the fields data fields PC + Sl_Val + S2_Val and a current dynamic instruction for execution will be found in Memo_table_I if its memory address (PC) and associated values to its input operands correspond to the fields PC, Sl_val and S2_Val of Memo_table_I, respectively, one entry of Memo_table_T will be indexed by the association of the fields PC_F + IS_Tags + IS_Val and the current dynamic instruction instantiated for execution will be found in Memo_table_T if its memory address (PC) matches the field PC_F of an entry of Memo table T and, in such an entry, the values of the registers of the registers file of the target computer indicated by the fields IS_Tags (of the same entry selected by PC) coincide with the fields IS_Val (of the same entry) that correspond to the input scope of the stored sequence; Buffer_T will only play the roll of temporarily storing the identified sequence, and this temporary storage will have the goal of extracting from the complete sequence solely the information that will be relevant to the Reuse of the sequence and to the storage of this information in Memo_table_T, given the previous considerations.
5. PROCESS OF FORMATION, MEMORIZATION AND REUSE, IN EXECUTION TIME, OF SEQUENCES OF DYNAMIC INSTRUCTIONS IN COMPUTERS, according to Claim 4, characterized by doing without the use of any invalidation mechanism over the entries of the three types of tables used.
6. PROCESS OF FORMATION, MEMORIZATION AND REUSE, IN EXECUTION TIME, OF SEQUENCES OF DYNAMIC INSTRUCTIONS IN COMPUTERS, according to Claim 4, characterized by executing a algorithmic sequence of formation, memorization and reuse of sequences of dynamic instructions based in two (2) search procedures performed on the tables Memo_table_I and Memo_table_T, where the issuing of these search procedures can occur concurrently and, moreover, asynchronously and/or subdivided in various stages of a pipeline that has a parallel to the stages of the target computer architecture, considering the tables Memo_table_I, Memo_table_T and Buffer_T, where for each instruction to be executed it will be held a Search in Memo_table_I in the following way: (1) Check if the current instruction belongs to the Selection set; (2) If (1) is false then any sequence that is being formed in Buffer T is ended, and the information extracted about such a sequence is stored in Memo_table_T, and Buffer T is free for the storage of a new sequence; end of the algorithm; Else continue; (3) Check if the current instantiated instruction and its operands is stored in Memo_table_I; (4) If (3) is false then include the current instantiated instruction in Memo_table_I and end any sequence being formed in Buffer_T and the information extracted about such a sequence is stored in Memo_table__T, and Buffer_T is free for the storage of a new sequence; end of the algorithm; Else the instruction in question is redundant and it will initiate or be added to the formation of the current sequence, being included in Buffer_T; and a Search in Memo_table_T will be held in t;he following way: (1) Check if the current instruction belongs to the Selection set; (2) If (1) is false then do not search in Memo_table_T; end of the algorithm; Else continue; (3) Check if PC (Program Counter) of the current instruction occurs at any of the Memo_table__T entries; (4) If (3) is true then select the first entry which input scope, indicated by IS_Tags and IS_Vals, corresponds to the state of the registers file of the target computer;
(5) If (4) is true (that is, there exists at least one valid entry) then, considering the entry in question, load the PC of the target computer with the value of NPC_L field and update the registers file of the target computer with the output scope given by 0S_Tags and OS_Vals fields.
7. PROCESS OF FORMATION, MEMORIZATION AND REUSE, IN EXECUTION TIME, OF SEQUENCES OF DYNAMIC INSTRUCTIONS IN COMPUTERS, according to Claim 6 characterized by forming sequences of dynamic instructions from the nth repetition, n belonging to N* , where N* represents the set of natural numbers excluding the zero, of any instruction belonging to the Sselection Set.
PCT/BR2000/000074 1999-07-13 2000-07-12 Process of formation, memorization and reuse, in execution time, of sequences of dynamic instructions in computers WO2001004746A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU57990/00A AU5799000A (en) 1999-07-13 2000-07-12 Process of formation, memorization and reuse, in execution time, of sequences of dynamic instructions in computers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
BR9902725A BR9902725A (en) 1999-07-13 1999-07-13 Process of formation, memorization and reuse, in execution time, of dynamic instruction sequences in computers
BRPI9902725-9 1999-07-13

Publications (1)

Publication Number Publication Date
WO2001004746A1 true WO2001004746A1 (en) 2001-01-18

Family

ID=4072777

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/BR2000/000074 WO2001004746A1 (en) 1999-07-13 2000-07-12 Process of formation, memorization and reuse, in execution time, of sequences of dynamic instructions in computers

Country Status (3)

Country Link
AU (1) AU5799000A (en)
BR (1) BR9902725A (en)
WO (1) WO2001004746A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2516732A (en) * 2013-07-12 2015-02-04 Advanced Risc Mach Ltd Result data stream coding for repeating workloads
US9286043B2 (en) 2013-03-15 2016-03-15 Microsoft Technology Licensing, Llc Software build optimization
US20180074827A1 (en) * 2016-09-14 2018-03-15 Intel Corporation Instruction and Logic for Dynamic Store Elimination

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0463973A2 (en) * 1990-06-29 1992-01-02 Digital Equipment Corporation Branch prediction in high performance processor
US5546559A (en) * 1993-06-07 1996-08-13 Hitachi, Ltd. Cache reuse control system having reuse information field in each cache entry to indicate whether data in the particular entry has higher or lower probability of reuse
EP0743598A2 (en) * 1995-05-18 1996-11-20 Hewlett-Packard Company Compiler for increased data cache efficiency
US5619662A (en) * 1992-11-12 1997-04-08 Digital Equipment Corporation Memory reference tagging
US5649178A (en) * 1995-06-07 1997-07-15 International Business Machines, Corporation Apparatus and method for storing and initializing branch prediction with selective information transfer
US5845103A (en) * 1997-06-13 1998-12-01 Wisconsin Alumni Research Foundation Computer with dynamic instruction reuse

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0463973A2 (en) * 1990-06-29 1992-01-02 Digital Equipment Corporation Branch prediction in high performance processor
US5619662A (en) * 1992-11-12 1997-04-08 Digital Equipment Corporation Memory reference tagging
US5546559A (en) * 1993-06-07 1996-08-13 Hitachi, Ltd. Cache reuse control system having reuse information field in each cache entry to indicate whether data in the particular entry has higher or lower probability of reuse
EP0743598A2 (en) * 1995-05-18 1996-11-20 Hewlett-Packard Company Compiler for increased data cache efficiency
US5649178A (en) * 1995-06-07 1997-07-15 International Business Machines, Corporation Apparatus and method for storing and initializing branch prediction with selective information transfer
US5845103A (en) * 1997-06-13 1998-12-01 Wisconsin Alumni Research Foundation Computer with dynamic instruction reuse

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9286043B2 (en) 2013-03-15 2016-03-15 Microsoft Technology Licensing, Llc Software build optimization
GB2516732A (en) * 2013-07-12 2015-02-04 Advanced Risc Mach Ltd Result data stream coding for repeating workloads
US9679342B2 (en) 2013-07-12 2017-06-13 Arm Limited Result data stream coding for repeating workloads
GB2516732B (en) * 2013-07-12 2020-11-25 Advanced Risc Mach Ltd Result data stream coding for repeating workloads
US20180074827A1 (en) * 2016-09-14 2018-03-15 Intel Corporation Instruction and Logic for Dynamic Store Elimination
US10540178B2 (en) * 2016-09-14 2020-01-21 Intel Corporation Eliminating redundant stores using a protection designator and a clear designator

Also Published As

Publication number Publication date
AU5799000A (en) 2001-01-30
BR9902725A (en) 2001-03-06

Similar Documents

Publication Publication Date Title
US5918005A (en) Apparatus region-based detection of interference among reordered memory operations in a processor
US11340908B2 (en) Reducing data hazards in pipelined processors to provide high processor utilization
JP3488162B2 (en) Method and apparatus for reordering loading operations in a computer processing system
US8650555B1 (en) Method for increasing the speed of speculative execution
US6694427B1 (en) Method system and apparatus for instruction tracing with out of order processors
US5710902A (en) Instruction dependency chain indentifier
US6334176B1 (en) Method and apparatus for generating an alignment control vector
US5694564A (en) Data processing system a method for performing register renaming having back-up capability
US5949995A (en) Programmable branch prediction system and method for inserting prediction operation which is independent of execution of program code
Huang et al. Speculative disambiguation: A compilation technique for dynamic memory disambiguation
US6081887A (en) System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction
EP0851343A2 (en) System for processing floating point operations
US20020069346A1 (en) Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list
EP1733311A2 (en) Method and structure for explicit software control of data speculation
CA2105806C (en) Apparatus for implementing interrupts in pipelined processors
US6681321B1 (en) Method system and apparatus for instruction execution tracing with out of order processors
US11269634B2 (en) Data structure relinquishing
WO2001004746A1 (en) Process of formation, memorization and reuse, in execution time, of sequences of dynamic instructions in computers
JP3138259B2 (en) System and method for fast register renaming by counting
US5745780A (en) Method and apparatus for source lookup within a central processing unit
CN116339830A (en) Register management method and device, electronic equipment and readable storage medium
US5729723A (en) Data processing unit
KR100305487B1 (en) Method and system in a data processing system of permitting concurrent processing of instructions of a particular type
EP0736830B1 (en) Method and apparatus for reconstructing the address of the next instruction to be completed in a pipelined processor
JPS60126736A (en) Data processor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM HR HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP