Description of the Invention "PROCESS OF FORMATION, MEMORIZATION AND REUSE, IN EXECUTION TIME, OF SEQUENCES OF DYNAMIC INSTRUCTIONS IN COMPUTERS" TECNICAL FIELD The present invention refers to a process of definition of a digital computational system capable of forming (selecting) , memorizing and reusing, in execution time (dynamically) , dynamic sequences of instructions, hence eliminating the necessity of re- executing such sequences when presenting input entries that have been priviously observed and, consequently, producing the same output; note that: dynamic instructions are caracterized as instances of static instructions in execution time; a sequence of dynamic instructions is defined as a succession of dynamic instructions, such succession is ordered by the flux of execution; input of a sequence of dynamic instructions is defined as the set of values attributed to the source operands of each dynamic instruction in the sequence; and, output of a sequence dynamic of instructions is defined as the set of values attributed to each result operand of each dynamic instruction in the sequence. The invention aims at the conception of a digital eletronic circuit wich performs the task refered to above. PREVIOUS TECHNIQUES
The reduction of program execution time, using memorization of results in computers, is basically effected through the Memorization and the consequent Reuse of Subrotines, functions and dynamic instructions, aiming at the reduction of the total amount of necessary instructions to the execution of programs, mantaining, however, the correction of the results. Some procedures for Memorizing and Reusing Subrotines, Functions
and Dynamic Instructions already exists, however, no process has been explored for the Formation, Memorization and Reuse of sequences of dynamic instructions where the goal is Forming (through selection) , Memorizing and Reusing at execution time, of sequences of dynamic instructions built from the re-execution of dynamic instructions with input values that ±rave been already observed. The procedures for Reuse of Subrotines and Functions usually present as main obstaxile the procesLs of Selecting of such Subrotines and Functions. The Selection of Subrotines and Functions to be memorized is effected in a static manner, by manually observing the encoding and the semanthics of the program, or with the aid of execution statistics or assited by the compiler or done in an incremental manner. The application of these procedures is not generic and is normally customized and dependent on the exeistence of such elements in a given program. The Procedures for Selection, Memorization and Reuse of dynamic instructions, applies Memorization and Reuse from particular schemes based on Memorization tables with a determined number of entries, that memorizes the dynamic instructions, where in the best case in particular conditions for all the schemes, at most four (4) dynamic instructions are reused at once. This invention presents a simple and efficient process for Selecting, Memorizing, and Reusing, at execution time, sequences of dynamic instructions of any size (where the size of a sequence of dynamic instructions refers to the amount of dynamic instructions included in the sequence) , and in comparison to previous work, we obtain a higher reuse percentual from the application of this process. The existing Processes for the Formation, Memorization and Reuse applied to programs are:
1. Software Function Memoization - Where in a given program, the Subrotines or Functions that are canditates to be reused are previously selected in a statical form, and the functions of Memorization and Reuse are effected by pieces of code that are inserted in the target program.
2. Hardware Function Memoization - Where in a given program the Subrotines or Functions that are candidates to be reused are previously selected in statical form, and the functions of Memorization and Reuse are effected by a piece of hardware that is activated by instructions that are inserted in the code of the target program.
3. Hardware Instruction Memorization - Where in programs in general: the Selection, Memorization and Reuse are effected on dynamic instructions via hardware at execution time. The existing schemes to effect the reuse of instructions differ form each other basically by: the information that is stored in the Memorization tables, the access method to the tables and invalidations performed.
3.1. The Sv scheme reuses instructions that present values for the input operands (registers) previously observed;
3.2. The Sn scheme reuses instructions based on the name of the operands (registers), i.e., an instruction reuses a value that has instantiated an operand if that operand value has not been altered; 3.3. The Sn+d scheme reuses instructions like Sn, however, it also manipulates chains of dependant instructions, more specifically, chains of instructions that have true data dependancy among themselves; 3.4. The Me oing scheme applies reuse in a restricted form which is exclusive to instructions with high execution latency (multiplication, division, etc) , being only valid fro instructions where the cost of reuse is smaller than the cost of execution (considering that cost is mesured by
time) .
4. Hardware Basic Block Reuse - Where for programs in general: the Selection, Memorization and Reuse are effected on basic blocks, that is, sequences of instructions delimited by one only entry point and one only exit jpoint. The basic blocks are partially selected and previously marked in static form by the compiler and/or dynamically by hardware. During the execution of a program the basic blocks will be memorized with their respective entry and exit scopes, including memory reading/writing instructions that have to be executed in orde to validade the reuse. This method restricts memorization to pieces of code with well defined execution flow. All the schemes present above have their utilization restricted either to isolated instructions or to basic blocks. DESCRIPTION OF THE INVENTION
The process that is the object of this invention allows for the employment of hardware, typically an electronic circuit, at execution time for the Formation, Memorization and Reuse of sequences of dynamic instructions. In this process, a sequence of dynamic instructions is characterized as being typically constituted by two (2) or three (3) instructions (sequences containing only one (1) or more than three (3) instructions can also be treated by the process) . The goal of the process is to directly reuse the results from the re- execution of dynamic instructions which present previously memorized entries, instead of re-executing all the instructions of the sequence, this way the total number of executed instructions in a given program is reduced, thence a reduction of total execution time is obtained. This way, the goal of the present invention is to provide a process for Formation, Memorization and Reuse of sequences of
dynamic instructions, which is basically composed by four (4) distinct stages:
(i) SELECTION OF THE INSTRUCTION SET FOR THE APPLICATION OF THE PROCESS The application of the process will be restricted to a subset of the overall instruction set of the target computer, which could be enlarged or reduced, depending on the architectural characteristics of the target computer. The basic instructions that are manipulated by the process are classified in groups according to their functionality, this groups are defined as the group of arithmetical instructions, the group of logical instructions, the group of instructions for execution flow control, and the group of instructions for local and main memory manipulation. The sequences of dynamic instructions will be composed by instructions belonging to these groups and to the union of such groups will be demoninated as the Selection Set. (ii) DEFINITION AND REPRESENTATION OF THE MEMORIZATION TABLES The memorization tables will be defined and represented according to the architectural characteristics of the target computer, such definition will consider the model of a LOAD/STORE architecture (where the instruction operands will allways be in registers internal to the target computer) , nevertheless, the definition could be applied to other architectural models. Let Memo_table_I be a table that will store the already executed dynamic instructions, where each stored instruction will be instantiated with respective values for the input operands and output results from its previous execution. Let Memo_table_T a table that will store information about sequences of dynamic instructions where all of the instructions of each sequence have already been executed and are or had been stored in
Memo_table_I, with the goal of the application of Reuse.
Let Buffer_T be a table that will temporarily store elements of Memo_table_I in such a way that these instructions are stored consecutively in its entries, i.e., will store the sequence of the dynamic instructions being formed.
Description of the fields of one entry of Memo_table_I from
Figure (1) :
PC - memory address of the instruction. N_PC - memory address of the next instruction to be executed.
R_Reg - register that stores the result of the operation.
SI _Reg - register that stores the first operand of the instruction. S2 _Reg - register that stores the second operand of the instruction.
R_Val - value of the result produced by the execution of the instruction.
Sl_Val - value of the first operand of the instruction. S2__Val - value of the second operand of the instruction.
I - If = 0 indicates that the instruction has an operand in a register and the second operand is immediate.
If = 1 indicates that the instruction has the two operands in registers. Description of the fields of an entry of Memo_table__T from
Figure (2) :
PC_F - memory address of the first instruction of the sequence.
NPC_L - memory address of the next instruction to be executed after the last instruction of the sequence.
IS_Tags - registers used by the entry scope.
OS Tags - register used by the exit scope.
IS_Val - values of the registers indicated by IS_Tags. OS_Val - values of the registers indicated by 0S_Tags. (iii) PROCEDURES FOR INDEXATION AND UPDATING OF THE MEMORIZATION TABLES The Memorization tables will be indexed by keys according to the fields of the table in question. One entry of Memo_table_I will be indexed by the association of the data fields PC + Sl_Val + S2_Val . The current instruction instantiated for execution will be found in Memo_table_I if its memory address (PC) and associated values to its input operands correspond to the fields PC, Sl_val and S2_Val of Memo_table__I, respectively. One entry of Memo_table_T will be indexed by the association of the fields PC_F + IS_Tags + IS_Val. The current dynamic instruction instantiated for execution will be found in Memo_table_T if its memory address (PC) matches the field PC_F of an entry of Memo_table_T and, in such an entry, the values of the registers of the registers file of the target computer indicated by the fields IS_Tags (of the same entry selected by PC) coincide with the fields IS_Val (of the same entry) that correspond to the input scope of the stored sequence. Buffer_T will only play the roll of temporarily storing the identified sequence, this temporary storage will have the goal of extracting from the complete sequence solely the information that will be relevant to the Reuse of the sequence and to the storage of this information in Memo_table_T . The descritpion of the updating operations on the tables (Memo_table_I and Memo_table_T) is based on a First-In-First-Out - FIFO - strategy (other updating strategies can be used) , that is, if there are free entries in the tables they could house new dynamic instructions or information about the sequences of dynamic instructions to be inserted, otherwise the oldest entry (that is, the one
first inserted) will be expunged to give space to the new required insertion, and this lastest insertion will be considered the most recent one.
(iv) ALGORITHM OF FORMATION, MEMORIZATION AND REUSE OF SEQUENCES OF DYNAMIC INSTRUCTIONS
The algorithm of Formation, Memorization and Reuse of sequences of dynamic instructions is based on two (2) search procedures performed on the tables Memo_table_I and Memo table T. The issuing of these search procedures can occur concurrently and, moreover, asynchronously and/or subdivided in various stages of a pipeline that has a parallel to the stages of the target computer architecture. Consider the tables Memo_table_I, Memo_table_T and Buffer_T. For each instruction to be executed do: Search in Memo_table_I :
(1) Check if the current instruction belongs to the Selection set;
(2) If (1) is false then any sequence that is being formed in Buffer_T is ended, and the information extracted about such a sequence is stored in Memo_table_T, and Buffer_T is free for the storage of a new sequence; end of the algorithm; Else continue;
(3) Check if the current instantiated instruction and its operands is stored in Memo__table_I ;
(4) If (3) is false then include the current instantiated instruction in Memo_table_I and end any sequence being formed in Buffer_T and the information extracted about such a sequence is stored in Memo_table_T, and Buffer_T is free for the storage of a new sequence; end of the algorithm; Else the instruction in question is redundant and it will initiate or be added to the formation of the current sequence, being included in Buffer T.
Search in Memo_table_T :
(1) Check if the current instruction belongs to the Selection set;
(2) If (1) is false then do not search in Memo_table_T; end of the algorithm; Else continue;
(3) Check if PC (Program Counter) of the current instruction occurs at any of the Memo_table_T entries;
(4) If (3) is true then select the first entry which input scope, indicated by IS_Tags and IS_Vals, corresponds to the state of the registers file of the target computer;
(5) If (4) is true (that is, there exists at least one valid entry) then, considering the entry in question, load the PC of the target computer with the value of NPC_L field and update the registers file of the target computer with the output scope given by 0S_Tags and OS_Vals fields. EXAMPLE
For the Formation of the sequences of the dynamic instructions to be memorized, will be considered the piece of code presented in Figure 3, where for each instantiated instruction (with the values given to its operands) by the execution of this piece of code, such instructions will be stored at Memo_table_I entries (if the instruction belongs to the Selection set) as shown by Figure 4. An instruction will be considered redundant if at a re-execution of such instruction, an instance of this instruction is already stored in Memo_table_I, in this case the instruction is candidate to initiate or to add to the formation of a sequence of dynamic instructions, being this instruction sequentially stored in Buffer_T (which stores a sequence of redundant instructions) . Figure 5 shows a sequence of redundant instructions, being this sequence stored in Buffer_T and delimited by the address interval [104,116]. Figure 6 shows a new entry included in Memo table T from
the sequence stored in Buffer_T (Figure 5) ; this new entry will store information about the sequence built and this procedure corresponds to the phase of memorization of the sequence of dynamic instructions. The sequence reuse in this example will occur whenever a re-execution of instruction 104 occurs and, in this re-execution, the input scope operand values of the sequence coincide with the values of the respective operands in the registers file of the target computer, that is, if there is an entry in Memo_table_T containing the value 104 in the field PC_F and the registers file of the target computer has in its registers identified by the field IS_Tags of the same entry, the same values stored in the field IS_Val from the same entry as shown in Figure 7. In this case, considering the already identified Memo_table_T entry, the reuse action will proceed by writing the value stored in the field NPC_L onto the PC of the target computer, altering, in this way, the execution flux and re-writing the registers (of the registers file of the target computer) indicated by the field OS_Tags with the values stored in field OS_Val, restoring, in this way, the machine context for the execution of the instruction to the reused sequence. From the exposed above, the instructions of a redundant sequence will be not executed since they were reused all at once, as illustrated by Figure 8.
ADVANTAGES OF THE REINVINDICATED PROCESS
The process of Formation, Memorization and Reuse of sequences of dynamic instructions described here is efficient on exployting the repetitive behavior of pieces of program code that arefrequently re-executed from the same entries, on the following aspects:
(i) There is no need for identifying, building or selecting, in a statical manner, sequences of instructions likely to repeat themselves;
(ii) The reuse of a sequence of dynamic instructions is equivalent to the reuse of all instructions of such sequence all at once, so that the cost of re-executing all these instructions is reduced to the cost of execution of a single instruction, considering the cases in which the cost of reuse of one (1) instruction is equal to the cost of execution of the same instruction (cost in time) .
(iii) There is no need for instantiating all the instructions of a sequence of dynamic instructions that will be executed since the reuse of sequences is based on input scopes and, as such scopes determine the flux and results of all the instructions to be executed, the execution of any instruction belonging to the sequence is not necessary to validate its reuse.
(iv) The reuse of sequences of dynamic instructions is not restricted to the amount of simultaneous accesses that can be done to a memorization table, to the dynamic instructions individually.
(v) The reuse process i rirrorlucad i_s bl e to xeduce the amount of hardware and execution bottlenecks on effecting: (a) Register Renaming, since the instructions of a reused sequence that were not executed, did not need to rename their output registers^ aliviating this way the renaming unit; (b) Branch Prediction, since branches included in such - used -sequen es a re .sol ved eEorehand, reducing, in this way, the latency related to brach resolution; (c) Use of -fiinctienal Units., since -by -avoi ding the _re--execution of instructions of a redundant sequence, the allocation of Functional Units to the instructions ot such -sequence is avoided; (d) Resolution of True Data Dependencies, since
the dependent instructions included in a redundant sequence will be executed all at once, that is, in the same cycle.
(vi) Other types of instructions can be included in the reuse process, so that incremental enhancement is allowed. Implementation to any target computer is feasable since in
99.6% of the sequences of dynamic instructions captured and reused by the process (measured in tests) , the size of input and output scopes are, each, smaller or equal to four
(4) registers.. (vii) Potential gains in terms of power consumption are expected since functional units and/or pipeline stages that are spared from re-executing redundant sequences of dynamic instructions could be switched-off if appropriate power- saving mechanisms would be employed in conjunction to the new reuse process.