WO2001017014A1

WO2001017014A1 - Storage cell array and a method for the manufacture thereof

Info

Publication number: WO2001017014A1
Application number: PCT/DE2000/002218
Authority: WO
Inventors: Bernhard Sell; Josef Willer; Dirk Schumann
Original assignee: Infineon Technologies Ag
Priority date: 1999-08-30
Filing date: 2000-07-07
Publication date: 2001-03-08
Also published as: TW463369B

Abstract

The invention relates to a storage cell array with storage capacitors, each of which has a lower capacitor electrode (53), a capacitor dielectric (54) and an upper capacitor electrode which are at least partially located in a trench. At least one of the capacitor electrodes (53, 61) is a metallic electrode, in particular made of tungsten-silicide. The storage cell array can be manufactured with a required space of 8F2 per storage cell.

Description

description

Memory cell arrangement and method for its production

So-called single-transistor memory cells are used almost exclusively in memory cell arrangements with dynamic, random access. A one-transistor memory cell comprises a read-out transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electrical charge, which represents a logical variable, 0 or 1. By controlling the read transistor via a word line, this information can be read out via a bit line. The storage capacitor must have a minimum capacitance for safe storage of the charge and simultaneous differentiability of the information read out. The lower limit for the capacitance of the storage capacitor is currently seen at 25 fF.

Since the memory density increases from memory generation to memory generation, the required area of the single-transistor memory cell must be reduced from generation to generation. At the same time, the minimum capacitance of the storage capacitor must be maintained.

Up to one MBit generation, both the read-out transistor and the storage capacitor were implemented as planar components. From the 4 MBit memory generation onwards, a further reduction in the area of the memory cell was achieved by a three-dimensional arrangement of the read transistor and memory capacitor. One possibility is to implement the storage capacitor in a trench (see, for example, BK Ya ada etal, Proc. Intern. Electronic Devices and Materials IEDM 85, p. 702 ff). In this case, the electrodes of the storage capacitor act as a diffusion region adjoining the wall of the trench and a doped polysilicon filling which is located in the trench. The electrodes of the storage capacitor are thus along the surface of the Trench arranged. As a result, the effective area of the storage capacitor, on which the capacitance depends, is increased compared to the space requirement for the storage capacitor on the surface of the substrate, which corresponds to the cross section of the trench. By reducing the cross section of the

Trench can further increase the packing density. The enlargement of the depth of the trench is, however, limited for technological reasons.

The invention is based on the problem of specifying a memory cell arrangement with memory cells, each of which has a storage capacitor and a selection transistor, in which the storage capacitor is arranged on a trench and, with a constant cross-sectional area and depth of the trench, has an increased capacitance in comparison with the prior art , Furthermore, a method for producing such a memory cell arrangement is to be specified.

This object is achieved by a memory cell arrangement according to claim 1 and a method for its production according to claim 7. Further developments of the invention emerge from the remaining claims.

In the memory cell arrangement according to the invention, the memory cells each have a storage capacitor and a selection transistor. The storage capacitor comprises a lower capacitor electrode, a capacitor dielectric and an upper capacitor electrode, which are at least partially arranged in a trench. The lower capacitor electrode is adjacent to a wall of the trench. At least one of the capacitor electrodes is designed as a metallic electrode. This prevents the formation of a depletion zone in the capacitor electrode designed as a metallic electrode, which leads to an increase in the specific capacitance. This measure also has the advantage that the electrode resistance of the capacitor electrode designed as a metallic electrode is reduced. The metallic electrode is preferably formed from tungsten silicide, tungsten, tungsten nitride, ruthenium or ruthenium oxide, since these metals can be introduced into the trench by CVD deposition. Furthermore, the metallic electrode can also be formed from iridium or iridu oxide.

Both the lower capacitor electrode and the upper capacitor electrode or both capacitor electrodes can be designed as a metallic electrode.

If only the lower capacitor electrode is designed as a metallic electrode, it is within the scope of the invention that the upper capacitor electrode contains doped polysilicon.

If only the upper capacitor electrode is designed as a metallic electrode, it is within the scope of the invention that the lower capacitor electrode is designed as a diffusion region adjacent to the trench.

A further increase in area can be achieved in that the trench extends from a main area of a semiconductor substrate into the semiconductor substrate and the trench has a smaller cross section in the area of the main area parallel to the main area than in an area of the trench facing away from the main area. In this embodiment, cavities are also avoided when filling the trench.

The memory cell arrangement has the advantage that it requires only minor modifications to a conventional process circuit for its manufacture. The invention is explained in more detail below on the basis of exemplary embodiments which are illustrated in the figures.

Figure 1 to Figure 7 shows steps for producing a

Memory cell arrangement in which an upper capacitor electrode is designed as a metal electrode.

FIG. 8 and FIG. 9 show manufacturing steps for a variant of the memory cell arrangement in which the upper capacitor electrode is designed as a metallic electrode.

FIGS. 10 to 13 show manufacturing steps for forming a selection transistor.

FIG. 14 shows a layout in an 8F ² cell architecture.

FIG. 15 to FIG. 21 show steps for producing a storage capacitor in which the lower capacitor electrode is designed as a metallic electrode.

FIGS. 22 and 23 show steps for producing a storage capacitor in which the lower and the upper capacitor electrodes are designed as metal electrodes.

FIGS. 24 to 27 show manufacturing steps for a selection transistor.

An 8 n thick SiO 2 (oxide) layer 3 and a 220 nm thick Si ₃ N ₄ layer 4 are applied to a main surface 1 of a semiconductor substrate 2. A 620 nm thick BPSG layer (not shown) is applied thereon.

Using a photolithographically produced mask (not shown), the BPSG layer, the Si ₃ N ₄ - Layer 4 and the Si0 ₂ layer 3 structured in a plasma etching process with CF4 / CHF3, so that a hard mask is formed. Using this hard mask as an etching mask, trenches 5 are etched into the main surface 1 in a further plasma etching process using HBr / NF ₃ . The BPSG layer is subsequently removed by wet etching with H2SO4 / HF.

The trenches 5 have a depth of 7 μm, a width of 100 × 250 nm and a mutual spacing of 100 nm.

A 10 nm thick SiO ₂ layer 6 is subsequently produced by thermal oxidation and covers at least the walls of the trenches 5. By depositing a 70 nm thick polysilicon layer, chemical-mechanical polishing to the surface of the Si ₃ N ₄ layer 4 and etching back the polysilicon layer with ΞF ₆ , a polysilicon filling ₇ is produced in the trenches 5, the surface of which is 1100 nm below the main surface 1 is arranged. The chemical mechanical polishing can be omitted if necessary. A 10 nm thick SiO ₂ layer 8 is formed on the surface of the polysilicon filling 7 by thermal oxidation.

Subsequently, a 10 nm thick Si ₃ N ₄ layer is deposited in a CVD process and selectively etched to SiO ₂ with CHF ₃ in an anisotropic plasma etching process. This creates 5 Si ₃ N ₄ spacers 9 above the polysilicon filling 7 on the flanks of the trenches.

The Si0 ₂ layer 8 is removed in a wet chemical etching step using NH ₄ F / HF, which attacks SiO ₂ selectively to form Si ₃ N ₄ and silicon. The etching time is such that approximately 25 nm of SiO _{2 are} removed. As a result, undercuts occur in the surface of the polysilicon filling 7, in which the side walls of the trenches 5 adjacent to the semiconductor substrate 2 are exposed (see FIG. 2). By CVD separation of

Si ₃ N ₄ in a layer thickness of 5 nm and subsequent anisotropic etching with CHF ₃ , these undercuts are Si ₃ N Fillings 10 filled. The etching time for this anisotopic etching step is dimensioned such that 5 nm Si ₃ N _{4 are} etched away.

SF ₆ is then used to selectively etch polysilicon to Si ₃ N ₄ and Si0 ₂ . The polysilicon filling 7 is removed from the trench 5 in each case. The exposed part of the Si0 ₂ layer 6 is removed by etching with NH ₄ F / HF. The etching time is dimensioned so that 10 nm Si0 _{2 are} etched. An isotropic etching step with ammonia is then carried out, in which silicon is selectively etched to nitride. The etching time is dimensioned so that 20 nm silicon are etched. The cross section of the trenches 5 in the lower region of the trenches 5, ie in the region facing away from the main surface 1, is widened by 40 nm (see FIG. 3).

By depositing an arsenic-doped silicate glass layer in a layer thickness of 50 nm and a TEOS-Si0 ₂ layer in a thickness of 20 nm and a subsequent tempering step at 1000 degrees Celsius, 120 seconds is achieved by diffusion out of the arsenic-doped silicate glass layer in the semiconductor substrate 2, an n ⁺ -doped region 11, which acts as the lower capacitor electrode of a single capacitor in the finished memory cell arrangement, is formed. The lower capacitor electrodes of adjacent capacitors are connected to one another via the n ⁺ -doped region 11. Alternatively, gas phase doping can also be carried out, for example with the following parameters: 900 ° C., 3 Torr tributylarsine (TBA) [33 percent], 12 min.

When diffusing out of the arsenic-doped silicate glass layer, the Si ₃ N ₄ filling 10 and the Si ₃ N ₄ spacer 9 act as a diffusion barrier, so that the n ⁺ -doped region 11 is delimited approximately 1000 nm below the main surface 1.

In an etching step selective to Si ₃ N ₄ and silicon

NH ₄ F / HF, the arsenic-doped silicate glass layer and the TEOS-Si0 ₂ layer are removed. In an etching step with HF / ethylene glycol, the Si ₃ N _{4 is attacked} selectively to Si ₂ silicon and the etching time is such that 15 nm Si ₃ N _{4 are} etched, the Si ₃ N ₄ filling 10 and the Si ₃ N ₄ spacer 9 removed (see Figure 4). A 5 nm thick dielectric layer 12 is subsequently deposited, which contains Si ₂ and Si ₃ N ₄ . Alternatively, the dielectric layer 12 contains Al2O3 (aluminum oxide), T1O2

(Titanium oxide), Ta2θ5 (tantalum oxide). A 30 nm thick tungsten silicide layer 13 is deposited by CVD deposition

(see Figure 4).

The remaining space in the trench 5 is filled with photoresist 14 and zuruckgeatzt with N _2/0. ₂ By anisotropic etching with HCI / CI2 / NF3 in a plasma-assisted etching process, tungsten silicide is then selectively etched to Si ₃ N ₄ and the dielectric layer 12. This creates an upper capacitor electrode 15 made of tungsten silicide (see FIG. 5).

After removing the photoresist fill 14 in an etching process with 0 ₂ / N ₂ , the remaining free space m is provided in the trench 5 by depositing a 70 nm thick polysilicon layer and chemical-mechanical polishing down to the surface of the S ₃ N ₄ layer 4 with a polysilicon filling 16 (see Figure 6).

In an etching step with SF ₆ , the polysilicon filling 16 is etched back under the main surface 1 by 100 nm. A S ₃ N ₄ attacking etching step with HF / ethylene glycol follows, in which nitride is etched. With the help of NH ₄ F / HF, exposed parts of the dielectric layer 12 and the SiO 2 layer 6 are removed (see FIG. 7). After a thermal oxidation (Sacπficial oxidation) is followed by an implantation with phosphorus with a dose of 2 x 10 ¹³ cm ^~ 2 and an energy of 10 keV to form a ^ -doped region 17 which in the upper region of the trench 5 to the main surface 1 borders. The depth of the n ⁺ -doped region 17 is such that between the basic doping of the semiconductor substrate 2 adjoins the surface of the trench 5 in the n ⁺ -doped region 17 and the n ⁺ -doped region 11 (see FIG. 7). The Si0 ₂ generated before the implantation is subsequently removed again. The trench 5 is essentially filled with a polysilicon filling 18 by deposition of polysilicon and anisotropic etching with SF ₆ .

The polysilicon fillings 16, 18 are in situ doped with arsenic during the deposition. As a result, the polysilicon fillings 16, 18 act as a connection structure between the upper capacitor electrode 15 and the n ^τ -doped region 17. The n "-doped region 17 is connected to a source / drain region of a selection transistor in the further production process.

As an alternative to the process sequence described with reference to FIG. 7, a 20 nm thick tungsten silicide layer 15 'and then a 50 nm thick polysilicon layer 16' can first be applied to the structure, as shown in FIG FIG. 6 is shown, can be deposited (see FIG. 8).

By chemical-mechanical polishing of polysilicon and tungsten silicide down to the surface of the Si ₃ N ₄ layer 4 and subsequent etching with HC1 / C1 ₂ / NF ₃ , in which the etching rate of Si0 and polysilicon is higher than that of tungsten silicide is, the tungsten silicide layer 15 ', the polysilicon layer 16', the Si0 ₂ layer 6 and the dielectric layer 12 are etched back 100 nm below the main surface 1. This creates an upper capacitor electrode 15 '', the doped over the height of the n ⁺ region 11 protrudes, and a polysilicon fill 16 ^'', the remaining free space of the trench 5 within the upper capacitor electrode 15 'fills (see Figure 9)'. Analogously as described with reference to FIG. 7, Si ₃ N ₄ etching around 10 nm with HF / ethylene glycol, isotropic etching of dielectric material around 5 nm, sacrificial oxidation and angled implantation with phosphorus follow around the n ⁺ -doped region 17 to form. After removal of the oxide layer formed before the implantation with DHF (dilute hydrofluoric acid), the polysilicon filling 18 is formed by depositing 80 nm polysilicon and chemical-mechanical polishing down to the surface of the Si ₃ N layer 4.

With the help of a photolithographically generated mask (not shown) and implantation with phosphorus with 1.3 MeV and 10 ^ ³ _C m ^~ 2, an n-doped well 19 is formed (see Figure 9).

The polysilicon filling 18 is etched up to the main surface 1 by etching with SF ₆ .

To define active areas, isolation structures 20 are subsequently created which laterally delimit active areas (see FIG. 10). For this purpose, a photolithographically generated mask (not shown) is formed which covers the active areas. A non-selective etching step with CHF ₃ / N / NF ₃ follows, in which silicon, tungsten silicide, Si0 ₂ and polysilicon is etched. The etching time is set so that 200 nm polysilicon are etched. After removal of the photoresist mask with 0 ₂ / N ₂ and wet chemical etching of the dielectric layer 12 at a depth of 3 nm, an oxidation is carried out and 5 nm SiN _{4 is} deposited. This is followed by a TEOS deposition of Si0 ₂ in a thickness of 250 nm. By chemical mechanical polishing to the surface of the Si ₃ N ₄ layer 4, an etching step in hot H ₃ P0 ₄ which attacks Si ₃ N ₄ , and an etching step with DHF which attacks Si0 ₂ , the insulation structure 20 is completed and the SiN ₄ layer 4 and the Si0 ₂ layer 3 are removed (see FIG. 10). CO LO) P>

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ke (not shown) and implantation steps, source / drain regions 28 are generated for selection transistors. The implantation is carried out with phosphorus with an energy of 25 keV and a dose of 3 x 10 ¹³ cm ^-2 .

By depositing an Si ₃ N ₄ layer with a layer thickness of 35 nm and anisotopic etching with CHF ₃ , Si ₃ N ₄ spacers 29 are produced on the flanks of the gate electrodes 26 and the Si ₃ N ₄ layer 25.

An oxynitride layer 30 is subsequently deposited over the entire surface in a layer thickness of 23 nm. This is followed by the deposition of a BPSG layer 31 with a thickness of 550 nm. In a tempering step at 850 ° C., the BPSG layer 31 is blown over. A planar surface is produced by chemical mechanical polishing, in which the oxynitride layer 30 acts as an etching stop (see FIG. 12).

An SiO ₂ layer 32 with a layer thickness of 450 nm is formed over the whole area by TEOS deposition (see FIG. 13). In the Si0 ₂ layer 32 and the BPSG layer 31, contact holes 33 to source / drain regions 28 are opened. The contact holes 33 are each opened to the source / drain region of a selection transistor which is not in contact with the n ⁺ -doped region 17. A photolithographically produced mask (not shown) is used to open the contact holes 33. The etching is carried out with 0 ₂ / C ₄ F ₈ / CO. The oxynitride layer 30 acts as an etch stop. To complete the contact holes 33, the oxynitride layer 30 is removed with 0 ₂ / CHF ₃ .

The contact holes 33 are provided with polysilicon fillings 34 by in situ-doped deposition of polysilicon and etching back of the polysilicon with CF ₄ / SF ₆ (see FIG. 13). With the help of a photolithographically generated mask (not shown) which covers the cell field of the memory cell arrangement, the SiO ₂ layer 32 is formed in the region of the periphery removed by etching with CF ₄ / CHF ₃ and an HDD implantation is carried out for transistors in the periphery.

After the formation of a photolithographically generated mask, the course of strip-shaped bit lines BL, which run parallel to one another and which run perpendicular to the word lines WL, etching takes place in the SiO ₂ layer 32 with CF ₄ / CHF ₃ . After removing the mask with 0 ₂ / N ₂ , the bit lines are generated by depositing titanium and tungsten and then chemical-mechanical polishing.

In order to complete the memory cell arrangement, wiring levels are formed in a known manner.

The memory cell arrangement has a memory capacitor arranged in one of the trenches 5 and a planar selection transistor for each memory cell. A space requirement of 8F ^{2 is} required per memory cell, where F is the smallest structure size that can be produced in the respective technology. The layout of the memory cell arrangement is shown in FIG. The bit lines BL run in the form of strips and parallel to one another, the width of the bit lines BL in each case F and their mutual spacing likewise being F. The word lines WL, which likewise have a width of F and a mutual spacing of F, run perpendicular to this. Active areas A are arranged below the bit lines BL, two word lines WL crossing above each active area. The active areas A are arranged offset from each other below adjacent bit lines BL. A bit line contact BLK is arranged in the middle of the active areas A, which enables an electrical connection between the respective bit line BL and the active area A. The trenches 5 are arranged below the word lines WL. The widening of the trenches 5 in the lower area is entered as a dotted contour and provided with the reference symbol 5 '. At the crossing point between one of the Bit lines BL and one of the word lines WL each have the gate electrode 26 of the associated selection transistor arranged (see FIG. 14).

The active regions A each extend between two trenches 5. They comprise two selection transistors which are connected to the associated bit line BL via a common bit line contact BLK. Depending on which of the word lines WL is driven, the information is read out of the storage capacitor which is arranged in one of the trenches 5 or the other of the trenches 5.

According to a further embodiment of the invention, an SiO ₂ layer 43 with a thickness of 8 nm and an SiN ₄ layer 44 with a thickness of 220 nm are applied to a main surface 41 of a semiconductor substrate 42 made of monocrystalline silicon. A BPSG layer with a thickness of 620 nm is deposited thereon (not shown). With the help of a photolithographically structured mask (not shown) which defines the arrangement of storage capacitors, the BPSG layer, the Si ₃ N ₄ layer 44 and the SiO ₂ layer 43 are structured by plasma etching with CF ₄ / CHF ₃ . After removing the mask with 0 ₂ / N; a trench 45 is formed using the BPSG layer as a hard mask by plasma etching with HBr / NF per memory cell. The trench 45 has a depth of 7 μm and a width of 100 nm × 250 nm (see FIG. 15).

The BPSG layer is removed by wet chemical etching with H ₂ S0 ₄ / HF. A SiO ₂ layer 46 with a layer thickness of 10 nm is formed by thermal oxidation and covers at least the walls of the trenches 45.

This is followed by the deposition of a 70 nm thick polysilicon layer, from which a polysilicon filling 47 is formed by chemical mechanical polishing down to the surface of the Si ₃ N ₄ layer 44 and etching with SF ₆ , which is arranged 1100 nm below the main surface 41 is. On the surface of the polysi- silicon layer 47, a 10 nm thick SiO ₂ layer 48 is formed by oxidation.

By CVD deposition of a 10 nm thick Si ₃ N ₄ layer and anisotropic plasma etching with CHF ₃ , Si ₃ N _{4 being} selectively etched to Si0 ₂ , 47 Si ₃ N ₄ spacers 49 are produced above the polysilicon filling (see FIG. 15 ).

The Si0 ₂ layer 48 and thereby exposed parts of the SiO ₂ layer 46 are removed by wet chemical etching of SiO ₂ selectively to Si ₃ N ₄ and silicon with NH ₄ F / HF. The etching time is set so that 25 nm Si0 _{2 are} etched. By CVD deposition of a 5 nm Si ₃ N layer and anisotropic etching with CHF ₃ , the etching time being set in such a way that 5 nm Si ₃ N _{4 are} etched, undercuts resulting from the wet chemical oxide etching with an Si ₃ N ₄ - Filling 50 filled (see Figure 16).

With the help of SF ₆ , the polysilicon filling 47 is subsequently removed selectively to Si ₃ N ₄ and Si0 ₂ . The exposed part of the SiO ₂ layer 46 is removed by wet chemical etching with NH ₄ F / HF. The cross section of the trenches 45 below the Si ₃ N ₄ spacer 49 and the Si ₃ N ₄ filling 50 is widened by isotropic etching with ammonia, silicon being attacked selectively to Si ₃ N ₄ . The etching time is set so that 20 nm

Silicon are etched. This means that the cross section of the respective trench 45 is widened by 40 nm (see FIG. 17).

By wet chemical etching with HF / ethylene glycol, the

Si ₃ N ₄ spacer 49 and the Si ₃ N ₄ filling 50 selectively removed to Si0 ₂ and silicon. The etching time is set so that 15 nm Si ₃ N _{4 are} etched. A 30 nm thick, arsenic-doped tungsten silicide layer 51 is produced by in situ-doped deposition of tungsten silicide (see FIG. 18). By depositing a photoresist, the trenches 45 are provided with a lacquer filling 52 in the lower region, in that the cross section of the trenches 45 has been widened by the isotropic silicon etching. The height of the resist filling 52 is adjusted by etching with N _2/0. ₂ Through anisotropic etching with HC1 / C1 ₂ / NF ₃ , in which tungsten silicide is etched selectively to Si ₃ N ₄ and Si0 ₂ , lower capacitor electrodes 53 are formed in the trenches 45 by structuring the tungsten silicide layer 51. The lower capacitor electrodes 53 are each arranged along the surface of the respective trench 45 in the region of the widening. Parts of the arsenic-doped tungsten silicide layer 51 which are arranged above the widened cross section of the respective trench 55 or which are arranged on the surface of the silicon nitride layer 44 are removed in the process (see FIG. 19). Subsequently, the paint filling 52 is removed with 0 ₂ / N ₂ .

This is followed by the deposition of a dielectric layer 54 in a layer thickness of 5 nm. The dielectric layer 54 contains SiO ₂ and Si ₃ N ₄ or the alternative dielectrics listed in connection with the first exemplary embodiment and serves as a capacitor dielectric in the finished memory cell arrangement. By depositing a 70 nm thick, in situ-doped polysilicon layer, a tempering step at 1100 degrees Celsius, 60 seconds and chemical-mechanical polishing of the polysilicon layer down to the surface of the Si ₃ N ₄ layer 44, an n ⁺ is formed by diffusion out of the lower capacitor electrode 53 doped region 55, which connects the adjacent lower capacitor electrodes 53 to one another, and a polysilicon filling 56 is formed by structuring the polysilicon layer (see FIG. 20).

The polysilicon filling 56 is etched back by 100 nm below the main surface 41 by etching with SF ₆ . There follows an Si ₃ N ₄ etching with HF / ethylene glycol, in which 10 nm Si ₃ N _{4 are} etched and an etching with NH ₄ F / HF, with which Si0 ₂ and dielectric material are etched. After a sacrificial oxidative On to form a scatter oxide (not shown), an implantation is carried out in which a

Area 57 is formed in the side wall of each trench 45 in the area of the main surface 41 (see Figure 21). Free space remaining in the respective trench 45 above the polysilicon filling 56 is filled with a polysilicon filling 58 by depositing msitu-doped polysilicon and scratching the polysilicon with SF _b . The polysilicon filling 56 acts as an upper capacitor electrode in the finished storage capacitor. The polysilicon filling 58 acts as a connection structure between the n ⁺ -doped region 57 and the polysilicon filling 56, which acts as an upper capacitor electrode.

To produce an upper capacitor electrode made of tungsten silicide, alternatively, after the dielectric layer 54 has been deposited, a 20 nm thick tungsten silicide layer 59 and then a 30 nm thick, msitu-doped polysilicon layer 60 can be deposited (see FIG. 22). In a tempering step at 1100 degrees Celsius, 60 seconds, the polysilicon layer 60 is healed and the N ⁺ -doped region 55 is formed by diffusion out of the arsenic-doped tungsten-silicon layer 51, which interconnects the lower capacitor electrodes 53 connects (see Figure 22).

The tungsten silicide layer 59 and the polysilicon layer 60 are structured by chemical-mechanical polishing down to the surface of the Si ₃ N ₄ layer 44. Subsequently, HCI / CI2 / NF3 polysilicon, tungsten silicide and Si0 _{2 are} selectively etched to Si ₃ N ₄ . The etching rates of S1O ₂ and polysilicon are somewhat higher than that of tungsten silicide. With

HF / ethylene glycol are 10 nm Si ₃ N ₄ etched. As a result, the surface of the semiconductor substrate 42 is exposed in the upper region of the trench 45. There follows an isotropic etching of the dielectric layer 54 with DHF. The etching time is set so that 5 nm are etched. After formation of a scattering oxide, the n ⁺ -doped region 57 is formed by angled phosphor implantation with an energy of 10 keV and a dose of 2 × 10 ¹³ cm ^-2 (see FIG. 23).

After removing the scatter oxide with DHF, an 80 nm thick in-situ doped polysilicon layer is deposited and structured by CMP. In this way, a polysilicon filling 63 is produced which essentially fills the respective trench 45 (see FIG. 23).

A masked implantation follows to form an n-doped well (not shown). The polysilicon filling 63 is etched up to the main surface 41 by etching with SF ₆ .

Isolation structures 64 are subsequently produced which surround and thus define active areas. For this purpose, a mask is created that defines the active areas (not shown). By non-selective plasma etching of silicon, tungsten silicide, Si0 ₂ and polysilicon with the help of CHF ₃ / N ₂ / NF ₃ , the etching time being set so that polysilicon is etched by 200 nm by removing one used in the process Lacquer mask with 0 ₂ / N ₂ , by wet chemical etching of 3 nm dielectric layer, by oxidation and deposition of a 5 nm thick Si ₃ N ₄ layer and by deposition in a TEOS process of a 250 nm thick Si0 ₂ layer and subsequent chemical - Mechanical polishing, the insulation structures 64 are completed. The Si ₃ N ₄ layer 44 is subsequently removed by etching in hot H ₃ PO ₄ and the Si0 ₂ layer 43 is removed by etching in DHF (dilute hydrofluoric acid) (see FIG. 24).

A scattering oxide is subsequently formed by a sacrificial oxidation. Masks and implantations generated by photolithography are used to form n-doped wells, p-doped wells and to carry out Threshold voltage implantations in the area of the periphery and the selection transistors of the cell array (not shown in detail). In particular, a p-doped well 65 with a dopant concentration of 5 × 10 ^^ cm ^{-3 is produced} in the region of the active areas, which is intended for receiving the selection transistors (see FIG. 25).

After removal of the scatter oxide with DHF, a gate oxide 66 is formed in a layer thickness of 6 nm by thermal oxidation. Subsequently, a polysilicon layer 67 and a tungsten silicide layer 68 are formed by integrated deposition. The polysilicon layer 67 is doped in situ and has a thickness of 80 nm. The tungsten silicide layer 68 has a thickness of 60 nm (see FIG. 25).

An Si ₃ N ₄ layer 69 is then deposited in a layer thickness of 200 nm.

(Not shown) using a mask photolithographically generated, the arrangement of gate electrodes comprising word lines which are streifenför ig and parallel to each other, defining the SiN ₄ layers 69 with CHF _3/0 ₂ / CF _4, the tungsten Silicide layer 68 etched with HC1 / C1 ₂ / NF ₃ and the polysilicon layer with HC1 / C1 ₂ . Gate electrodes 70 are each formed from the tungsten silicide layer 68 and the polysilicon layer 67 (see FIG. 26).

The side walls of the gate electrodes 70 are provided with an SiO ₂ layer 71 by oxidation. A masked implantation follows to form source / drain regions 72.

After removal of the eotolacquer masks used last, deposition of a 35 nm thick Si ₃ N ₄ layer and anisotropic etching with CHF ₃ on the flanks of the gate electrodes 70 and the Si ₃ N ₄ layer 69 form Si ₃ N ₄ spacers 73 , A 23 nm thick oxynitride layer 74 is subsequently deposited. A planar surface is achieved by depositing a BPSG layer 75 in a layer thickness of 550 nm, flowing the BPSG layer 75 and chemical-mechanical polishing, the oxynitride layer 74 acting as an etching stop (see FIG. 26).

An SiO ₂ layer 76 with a layer thickness of 450 nm is applied to this planar surface in a TEOS process. With the aid of a photolithographically produced mask (not shown), contact holes 77 are produced in the SiO ₂ layer 76, which extend to the source / drain region 72 of the selection transistors and the transistors in the periphery that do not contain the n ⁺ -doped Area 57 is connected (see Figure 27). When anisotropic etching is used to open the contact hole 76 with 0 ₂ / C ₄ F ₈ / CO, the oxynitride layer 74 acts as an etching stop. In the area of the contact holes 77, the oxynitride layer 74 is removed with 0 ₂ / CHF ₃ .

With the help of a photolithographically generated mask that covers the cell field of the memory cell arrangement, a

HDD implantation performed for transistors in the periphery (not shown).

A polysilicon filling 78 is formed in the contact holes 77 by depositing an in-situ doped polysilicon layer and anisotropic etching with CF / SF ₆ (see FIG. 27).

With the help of another photolithographically generated mask (not shown), which defines the arrangement of strip-shaped, parallel bit lines that run perpendicular to the word lines, CF ₄ / CHF _{3 is} etched into the SiO ₂ layer 76. Doing so. etched to a depth of 270 nm.

After removing the photolithographically produced mask with 0 ₂ / N ₂ , titanium and tungsten are deposited and structured mechanical-mechanical polishing. Bit lines 79 are thereby generated.

The memory cell arrangement is completed in a known manner by the formation of further wiring levels.

Claims

claims

1. Memory cell arrangement

with memory cells, each having a storage capacitor and a selection transistor,

the storage capacitor has a lower capacitor electrode, a capacitor dielectric and an upper capacitor electrode, which are arranged at least partially in a trench, the lower capacitor electrode being adjacent to a wall of the trench,

- In which at least one of the capacitor electrodes is designed as a metallic electrode.

2. Memory cell arrangement according to claim 1, wherein the metallic electrode contains tungsten silicide, tungsten, tungsten nitride, ruthenium, ruthenium oxide or iridium or iridium oxide.

3. Memory cell arrangement according to claim 1 or 2, in which the lower capacitor electrode and the upper capacitor electrode are designed as metallic electrodes.

4. Memory cell arrangement according to claim 1 or 2, in which the lower capacitor electrode is designed as a metallic electrode and the upper capacitor electrode contains doped polysilicon.

5. Memory cell arrangement according to claim 1 or 2, in which the lower capacitor electrode is designed as a diffusion region adjoining the trench and the upper capacitor electrode is designed as a metallic electrode.

6. Memory cell arrangement according to one of claims 1 to 5, in which the trench extends from a main surface of a semiconductor substrate into the semiconductor substrate and the trench in the region of the main surface parallel to the main surface. before it has a smaller cross section than in a region of the trench facing away from the main surface.

7. Method for producing a memory cell arrangement with a storage capacitor and a selection transistor,

a trench is etched into a main surface of a semiconductor substrate,

in which a lower capacitor electrode, which is adjacent to a wall of the trench, a storage dielectric and an upper capacitor electrode, which is at least partially arranged in the trench, are formed,

- In which at least one of the capacitor electrodes is formed by CVD deposition of a metal.

8. The method according to claim 7, wherein at least one of the capacitor electrodes is formed by CVD deposition of tungsten silicide, tungsten, tungsten nitride, ruthenium, ruthenium oxide or iridium or iridium oxide.

9. The method according to claim 7 or 8,

in which anisotropic etching is first carried out in the semiconductor substrate to form the trench,

in which a part of the trench wall adjacent to the main surface is provided with a protective spacer,

- in which the trench is widened selectively to the protective spacer in the region facing away from the main surface by means of an isotropic etching.

10. The method according to any one of claims 7 to 9,

- in which the lower capacitor electrode is formed by diffusion out of a diffusion source introduced into the trench as a diffusion region adjacent to the wall of the trench, - in which the upper capacitor electrode is formed by CVD deposition of a metal.

11. The method according to any one of claims 7 to 9,

in which the lower capacitor electrode is formed by CVD deposition of a metal,

- In which the upper capacitor electrode is formed from doped polysilicon.

12. The method according to any one of claims 7 to 9, wherein the lower capacitor electrode and the upper capacitor electrode are formed by CVD deposition of a metal.