WO2001024029A3 - Network topology for a scalable multiprocessor system - Google Patents

Network topology for a scalable multiprocessor system Download PDF

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Publication number
WO2001024029A3
WO2001024029A3 PCT/US2000/027024 US0027024W WO0124029A3 WO 2001024029 A3 WO2001024029 A3 WO 2001024029A3 US 0027024 W US0027024 W US 0027024W WO 0124029 A3 WO0124029 A3 WO 0124029A3
Authority
WO
WIPO (PCT)
Prior art keywords
scalable
processing element
multiprocessor system
network topology
routers
Prior art date
Application number
PCT/US2000/027024
Other languages
French (fr)
Other versions
WO2001024029A2 (en
Inventor
Martin M Deneroff
Gregory M Thorson
Randal S Passint
Original Assignee
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics Inc filed Critical Silicon Graphics Inc
Priority to DE60034470T priority Critical patent/DE60034470T2/en
Priority to JP2001526728A priority patent/JP4480315B2/en
Priority to EP00967199A priority patent/EP1222557B1/en
Publication of WO2001024029A2 publication Critical patent/WO2001024029A2/en
Publication of WO2001024029A3 publication Critical patent/WO2001024029A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17312—Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/14—Routing performance; Theoretical aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H04L67/1001—Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers

Abstract

A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.
PCT/US2000/027024 1999-09-29 2000-09-29 Network topology for a scalable multiprocessor system WO2001024029A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE60034470T DE60034470T2 (en) 1999-09-29 2000-09-29 Massively parallel data processing system and scalable interconnection network for such a system
JP2001526728A JP4480315B2 (en) 1999-09-29 2000-09-29 Scalable multiprocessor network
EP00967199A EP1222557B1 (en) 1999-09-29 2000-09-29 Network topology for a scalable multiprocessor system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/408,972 1999-09-29
US09/408,972 US6973559B1 (en) 1999-09-29 1999-09-29 Scalable hypercube multiprocessor network for massive parallel processing

Publications (2)

Publication Number Publication Date
WO2001024029A2 WO2001024029A2 (en) 2001-04-05
WO2001024029A3 true WO2001024029A3 (en) 2001-08-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/027024 WO2001024029A2 (en) 1999-09-29 2000-09-29 Network topology for a scalable multiprocessor system

Country Status (5)

Country Link
US (5) US6973559B1 (en)
EP (1) EP1222557B1 (en)
JP (1) JP4480315B2 (en)
DE (1) DE60034470T2 (en)
WO (1) WO2001024029A2 (en)

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US6973559B1 (en) 1999-09-29 2005-12-06 Silicon Graphics, Inc. Scalable hypercube multiprocessor network for massive parallel processing
US7436775B2 (en) * 2003-07-24 2008-10-14 Alcatel Lucent Software configurable cluster-based router using stock personal computers as cluster nodes
US20050138324A1 (en) * 2003-12-19 2005-06-23 International Business Machines Corporation Processing unit having a dual channel bus architecture
US7486619B2 (en) * 2004-03-04 2009-02-03 International Business Machines Corporation Multidimensional switch network
US9990607B1 (en) 2006-01-13 2018-06-05 Wensheng Hua Balanced network and method
US7826455B2 (en) * 2007-11-02 2010-11-02 Cisco Technology, Inc. Providing single point-of-presence across multiple processors
US7872990B2 (en) * 2008-04-30 2011-01-18 Microsoft Corporation Multi-level interconnection network
US8001310B2 (en) 2009-03-04 2011-08-16 Hewlett-Packard Development Company, L.P. Scalable computer node having an expansion module that is socket-compatible with a central processing unit
US9479358B2 (en) * 2009-05-13 2016-10-25 International Business Machines Corporation Managing graphics load balancing strategies
US8307116B2 (en) * 2009-06-19 2012-11-06 Board Of Regents Of The University Of Texas System Scalable bus-based on-chip interconnection networks
TWI410087B (en) * 2010-12-20 2013-09-21 Ind Tech Res Inst Manycore networks-on-chip architecture
EP2759100B1 (en) 2011-10-26 2015-03-04 International Business Machines Corporation Optimising data transmission in a hypercube network
US9294419B2 (en) * 2013-06-26 2016-03-22 Intel Corporation Scalable multi-layer 2D-mesh routers
JP6337606B2 (en) 2014-05-15 2018-06-06 富士通株式会社 Information processing apparatus, route determination method, and program
RU2635896C1 (en) * 2016-07-07 2017-11-16 Акционерное общество "Научно-исследовательский институт вычислительных комплексов им. М.А. Карцева" (АО "НИИВК им. М.А. Карцева") High-performance computer platform based on processors with heterogeneous architecture
US10057334B2 (en) 2016-11-14 2018-08-21 Futurewei Technologies, Inc. Quad full mesh and dimension driven network architecture
RU2708794C2 (en) * 2018-05-21 2019-12-11 Общество с ограниченной ответственностью "Центр инженерной физики при МГУ имени М.В. Ломоносова" Computational module for multi-stream processing of digital data and processing method using said module
US11750531B2 (en) 2019-01-17 2023-09-05 Ciena Corporation FPGA-based virtual fabric for data center computing

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WO1999026429A2 (en) * 1997-11-17 1999-05-27 Cray Research, Inc. Hybrid hypercube/torus architecture

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Also Published As

Publication number Publication date
US6973559B1 (en) 2005-12-06
JP2003510720A (en) 2003-03-18
US20130246653A1 (en) 2013-09-19
JP4480315B2 (en) 2010-06-16
EP1222557B1 (en) 2007-04-18
EP1222557A2 (en) 2002-07-17
US20060282648A1 (en) 2006-12-14
DE60034470D1 (en) 2007-05-31
US20090113172A1 (en) 2009-04-30
US20160337229A1 (en) 2016-11-17
US8433816B2 (en) 2013-04-30
DE60034470T2 (en) 2008-01-03
US9514092B2 (en) 2016-12-06
WO2001024029A2 (en) 2001-04-05

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