WO2001024268A1

WO2001024268A1 - A nonvolatile memory device with a high work function floating-gate and method of fabrication

Info

Publication number: WO2001024268A1
Application number: PCT/US2000/022784
Authority: WO
Inventors: Neal R. Mielke; Manzur Gill
Original assignee: Intel Corporation
Priority date: 1999-09-24
Filing date: 2000-08-17
Publication date: 2001-04-05
Also published as: TW474013B; AU6918300A

Abstract

A nonvolatile memory device and its method of fabrication is described. The electrically erasable nonvolatile memory device of the present invention includes a tunnel dielectric formed on a p-type substrate region. A floating-gate having a work function of greater than 4.1 eV is formed on the tunnel dielectric layer. A dielectric is then formed on the floating-gate. a control gate is then formed on the dielectric over the floating-gate.

Description

A NONVOLATILE MEMORY DEVICE WITH A HIGH WORK FUNCTION FLOATING-GATE AND METHOD OF FABRICATION

BACKGROUND OF THE INVENTION

1. FIELD OF THE INVENTION

The present invention relates to the field of semiconductor manufacturing and more specifically to an electrically erasable nonvolatile memory device and its method of fabrication.

2. DISCUSSION OF RELATED ART

A conventional electrically erasable nonvolatile memory device 100 is shown in Figure 1. Memory device 100 includes an n+ polysilicon floating gate 102 formed on the tunnel oxide 104 which is formed on the p-type silicon region 106. An interpoly dielectric 108 is formed on the n+ polysilicon floating gate and a control gate 110 formed on the interpoly dielectric layer 108 and a pair of n+ source/drain regions 109 are formed along laterally opposite sidewalls of floating gate electrode 102. To store information in memory device 100 charge is stored on floating gate 102. To erase memory device 100 charge is removed from floating gate 10.

A problem with floating gate memory storage devices, such as device 100 shown in Figure 1, is charge leakage whereby electrons leak off the floating gate. The more a device is cycled (programmed/erased)^' the more likely the charge will leak from the floating gate. If too much charge leaks off the device one will not be able to determine whether or not the device is programmed. As device dimensions and dielectric thicknesses are scaled down in order to increase the packing density of a memory integrated circuit and to increase the performance of the memory, electron leakage becomes worse.

Thus, what is desired is a nonvolatile memory device with improved data retention and its method of fabrication.

SUMMARY OF THE INVENTION

A nonvolatile memory device and its method of fabrication is described. The electrically erasable nonvolatile memory device of the present invention includes a tunnel dielectric formed on a p-type substrate region. A floating-gate having a work function of greater than 4.1 eV is formed on the tunnel dielectric layer. A dielectric is then formed on the floating-gate and a control gate is then formed on the dielectric over the floating-gate.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is an illustration of a cross-sectional view of a conventional electrically erasable nonvolatile memory device.

Figure 2a is an illustration of a cross-sectional view of an electrically erasable nonvolatile memory device in accordance with the present invention.

Figure 2b is an illustration of an energy diagram of a device having a p- type floating gate.

Figure 3a is an illustration of an overhead view of a portion of a flash memory array. Figure 3b is an illustration of a cross-sectional view taken along a wordline direction through the source rail and showing a plurality of shallow trench isolation regions.

Figure 3c is an illustration of a cross-sectional view taken along the wordline direction through the source rail showing the removal of a portion of the shallow trench isolation regions from the substrate of figure 3b.

Figure 3d is an illustration of a cross-sectional view taken along the wordline direction through the source rail showing the formation of doped regions in the substrate of figure 3c.

Figure 4 is an illustration of a cross-sectional view of a substrate taken along the wordline direction showing the formation of a pad oxide and a nitride layer.

Figure 5 is an illustration of a cross-sectional view taken along the wordline direction showing the formation of trenches in the substrate of figure 4.

Figure 6 is an illustration of a cross-sectional view taken along the wordline direction showing the formation of a first trench oxide on the substrate of figure 5.

Figure 7 is an illustration of a cross-sectional view taken along the word line direction showing the formation of a second trench oxide and the rounding of trench corners on the substrate of figure 6. Figure 8 is an illustration of a cross-sectional view taken along the wordline direction showing the filling of the trench isolation regions of the substrate of figure 7.

Figure 9 is an illustration cross-sectional view taken along the wordline direction showing the removal of the silicon nitride and pad oxide layers from the substrate of figure 8.

Figure 10 is an illustration of the cross-sectional view taken along the wordline direction showing the formation of an n-well photoresist mask over the substrate of figure 9.

Figure 11 is an illustration of the cross-sectional view taken along the wordline direction showing the formation of p- wells in the substrate of figure 10.

Figure 12 is an illustration of a cross-sectional view taken along the wordline direction showing the formation of a sacrificial oxide and the drive of the wells into the substrate of figure 11.

Figure 13 is an illustration of a cross-sectional view taken along the wordline direction showing the formation of a tunnel oxide on the substrate of figure 12.

Figure 14 is an illustration of a cross-sectional view taken along the wordline direction showing the formation of a polysilicon layer on the substrate of figure 13. Figure 15 is an illustration of a cross-sectional view taken along the wordline direction showing the patterning of the first polysilicon layer on the substrate of figure 14.

Figure 16 is an illustration of a cross-sectional view taken along the wordline direction showing the formation of a interpoly dielectric on the substrate of figure 15.

Figure 17 is an illustration of a cross-sectional view taken along the wordline direction showing the removal of the interpoly dielectric from the periphery portion of the integrated circuit.

Figure 18 is an illustration of a cross-sectional view taken along the wordline direction showing the formation of a gate dielectric on the periphery portion of the substrate to figure 17.

Figure 19 is an illustration of a cross-sectional view taken along the wordline direction showing the formation of a second polysilicon film on the substrate of figure 18.

Figure 20 is an illustration of a cross-sectional view taken along the wordline direction showing the planarization of the second polysilicon layer on the substrate of figure 19.

Figure 21a is an illustration of a cross-sectional view taken along the wordline direction showing the formation of a poly 2 patterning mask on the substrate of figure 20. Figure 21b is an illustration of a cross-sectional view taken along the bitline direction showing the patterining of the polysilicon layer, the interpoly dielectric and the first polysilicon lines on the substrate of figure 20.

Figure 22a is an illustration of a cross-sectional view taken along the bitline direction showing the formation of a photoresist mask which reveals the portions of the silicon substrate for the shared source regions and a portion of the shallow transisolation which is to be removed.

Figure 22b is an illustration of a cross-sectional view taken through the shallow trench isolation regions in the bitline direction showing the portion of the shallow trench isolation which is to be removed to generate the source rail.

Figure 23 is an illustration of a cross-sectional view taken along the bitline direction showing the formation of source/ drain regions in the array portion of the integrated circuit of figure 22a.

Figure 24 is an illustration of a cross-sectional view taken along the bitline direction showing the formation of a graded and heavily doped source region in the substrate of figure 23.

Figure 25 is an illustration of a cross-sectional view taken along the bitline direction showing the formation of a thermal oxide and a high temperature oxide over the substrate of figure 24.

Figure 26 is an illustration of a cross-sectional view taken along the bitline direction showing the formation of a silicon nitride layer over the substrate of figure 25. Figure 27 is an illustration of a cross-sectional view taken along the bitline direction showing the formation of spacers and plugs from the silicon nitride layer on the substrate of figure 26.

Figure 28 is an illustration of a cross-sectional view showing the removal of the oxide layer from the substrate of figure 27.

Figure 29 is an illustration of a cross-sectional view taken along the bitline direction showing the formation of a metal layer of the substrate figure 28.

Figure 30 is an illustration of a cross-sectional view taken along the bitline direction showing the formation of a suicide from the substrate of figure 29.

Figure 31 is an illustration of a cross-sectional view taken along the bitline direction showing the formation of a planar interlayer dielectric over the substrate of figure 30.

Figure 32 is an illustration of a cross-sectional view taken along the bitline direction showing the formation of electrical contacts in the substrate of figure 31.

Figure 33 is an illustration of a cross-sectional view taken along the bitline direction showing the formation and patterning of a first level of metallization on the substrate of figure 32. DETAILED DESCRIPTION OF THE PRESENT INVENTION

The present invention is a novel nonvolatile memory device and its method of fabrication. In the following description numerous specific details are set forth in order to provide a through understanding of the present invention. One of ordinary skill in the art, however, will appreciate that these specific details are not necessary in order to practice the present invention. In other instances well known semiconductor fabrication processes and techniques have not been set forth in particular detail in order to not unnecessarily obscure the present invention.

The memory device of the present invention is a memory device of the type which includes a floating gate formed on a tunnel dielectric formed on a p- type substrate region. The memory device includes a control gate which is formed over the floating gate and separated from the floating gate by an interlayer dielectric. According to the present invention the floating gate is formed of p-type polysilicon or of a material with a high intrinsic work function. By forming the floating gate from a material which has a high intrinsic work function, such as p-type polysilicon, or metals such as cobalt, platinum, and tungsten improves the data retention time of the memory cell dramatically. For example, by forming a floating gate from a material having a work function greater than n-type polysilicon (approximately 4.1 electron volts) the data retention time- to failure of the cell can be improved by at least a factor of 10 over a cell which utilizes an n-type polysilicon floating gate.

An example of an electrically erasable nonvolatile memory device in accordance with the present invention is illustrated in Figure 2a. Electrically erasable non-volatile memory device 200 is formed on a p-type region 202 of a single crystalline silicon substrate (e.g., a boron doped monocrystalline silicon

17 3 substrate) having doping density between 1-9x10 atoms/cm . A thin, 60 to 12θA, high quality tunnel dielectric 204, such as a grown silicon dioxide film, is formed on p-type region 202.

A floating gate 206 is formed over tunnel dielectric 204 formed over p- type region 202. According to the present invention floating gate 206 is formed of a material having an intrinsic work function greater than n-type polysilicon (about 4.1 electron volts). In an embodiment of the present invention the work function of floating gate material 206 is greater than or equal to 4.6 electron volts and ideally greater than 5.1 electron volts. In an embodiment of the present invention floating gate 206 is formed from p-type polysilicon doped to a

18 19 3 concentration level between 5x10 -5x10 atoms / cm . In another embodiment of the present invention the p-type polysilicon floating gate is doped with p-type ions (e.g., boron) to a conductivity level so that when cell 200 is erased at least the lower portion of floating gate 206 formed on tunnel dielectric 204 inverts into n-type polysilicon. The inversion occurs only during tunnel erase operations but not during other modes of operation.

In another embodiment of the present invention floating gate 206 is a metal or material having an intrinsic work function greater than the intrinsic work function of the n-type polysilicon. For example, floating gate 206 can be formed from high intrinsic work function metals such as but not limited to cobalt (work function of approximately 5.0 electron volts), platinum (work function of approximately 5.7 electron volts) molybdenum (work function of approximately 4.6 eV) and tungsten (work function of between 4.55-5.3 electron volts) and can be metal suicides such as but not limited to nickel suicide (work function of approximately 4.5 eV) titanium suicide (work function of approximately 4.52 eV), tungsten suicide (work function of approximately 4.55 eV), cobalt suicide (work function of approximately 4.75 eV), and molybdenum suicide (work function of approximately 4.8 eV) and can be other materials such as but not limited to titanium nitride (work function of approximately 4.55 eV). It is to be appreciated that floating gate 206 may be a single layer of material or a composite of different layers of materials so as long as the fabricated floating gate has a work function greater than the work function of n-type polysilicon, and preferably of at least 4.6 eV.

An interlayer or interpoly dielectric 208 comprising, for example, an oxide/nitride/oxide composite stack having a thickness between 150-250A is formed on floating gate 206. A control gate 210 is formed on the interlayer dielectric 208 over floating gate 206. In one embodiment for the present invention control gate 210 is a polycide film (i.e., a film comprising a polysilicon/silicide stack) comprising a lower polysilicon film 212 and an upper suicide film 214 such as but not limited to titanium suicide or tungsten suicide.

An n+ type source region 216 and n+ type drain region 218 are formed along laterally opposite sidewalls of floating gate 206 and extend beneath floating gate 206 as shown in Figure 2a. The portion 220 of p-type region 202 between the source and drain regions 216 and 218 beneath the floating gate 206 defines the channel region of device 200. Memory device 200 is said to be a "n- channel" device because when device 200 is programmed channel region 220 conducts electricity between source region 216 and drain region 218 by inverting portion 220 of p-type region 202 into n-type silicon. Source and drain regions 216 and 218 are heavily doped n-type silicon regions having a doping density of

19 3 at least 1x10 atoms/cm and can have suicide 222 formed thereon in order to decrease the contact resistance to the device. In an embodiment of the present invention device 200 has asymmetric source and drain regions wherein the source region includes an additional high energy high conductivity implant to form a deeper and graded source region 216.

Device 200 also includes a pair of spacers 224 formed along laterally opposite sidewalls of the floating gate /dielectric /control gate stack. Spacers 224 can include a bulk silicon nitride portion 226 and a buffer oxide layer 228. Spacers 224 seal and prevent contamination of tunnel oxide 204 and interlayer dielectric 208 and can be used to form suicide layers 214 and 222 by a self- aligned suicide process.

Memory device 200 is erased by removing stored electrons from floating gate 206. Memory device 200 can be erased by placing a relatively high positive voltage (+5.0 volts) onto source region 216 while applying a negative voltage of approximately -10.0 volts onto control gate 210. The positive voltage on the source region attracts electrons on floating gate 206 and thereby pulls electrons off floating gate 206 through tunnel oxide 204 and into source region 216. Lack of measurable electrons on floating gate 206 is an indication of an erased memory device 200. In order to program memory device 220, electrons are placed on floating gate 206 by grounding source region 216 while a relatively high positive voltage of +6.0 volts is applied to drain region 218 and while approximately 10-12 volts is applied to control gate 210, in order to invert channel region 220 into n-type silicon so that the channel region 220 turns on and electrons flow between source region 216 and drain 218. The high control gate voltage pulls electrons from the inverted channel regions 220 through tunnel dielectric 204 and onto floating gate 206.

Charge loss is reduced in device 200 because floating gate 206 is made from a material having a high intrinsic work function. A high work function floating gate improves data retention because the barrier height seen by tunneling electrons is higher when the work function is higher. For example, shown in Figure 2b is an energy diagram 250 for a device having a p-type polysilicon floating gate. As shown in Figure 2b electrons tunneling from the valence band 252 of a floating gate material have a greater barrier height than that seen by electrons 253 tunneling from the conduction band 254. With p-type poly there are negligible electrons in the conduction band 254. Additionally, electron tunneling from low energy levels in high work function materials can be suppressed by a forbidden transition effect whereby there is no available site in the substrate silicon to tunnel to. For example, as shown in Figure 2b, electrons in the valence band 252 intercept the band gap 256 of the silicon substrate. Still further a high work function floating gate increases the thermal equilibrium threshold voltage (V_τ) of a transistor. Charge loss cannot continue beyond a point where thermal equilibrium is reached based on the laws of thermodynamic so charge loss must stop entirely at a more favorable (higher)

Unfortunately, the increase in barrier height seen by the tunneling electrons which is the root cause of improvement in charge loss also inhibits the desirable tunneling that occurs at high field during erase operations. The increased barrier height can cause the erase to become slow. However, increasing the voltage applied to the cell during erase can overcome the increase in barrier height. In the case of p-type polysilicon this can also be overcome by lowering the p-type doping to allow an inversion of the p-type poly into n-type poly during erase operations.

An example of a layout of a portion of a memory block comprising memory cells 200 is illustrated in Figure 3a. It is to be appreciated that the layout of Figure 3 is just one example of many possible different array configuration for memory devices 220. The layout of Figure 3 is advantageous for at least because it enables a high density placement of memory cells 200.

An illustration of an overhead view of a portion of a flash memory block

310 of a flash memory integrated circuit in accordance with an embodiment of the present invention is illustrated in Figure 3a. Each block 300 comprises a plurality of flash cells layed out in a plurality of rows and columns. The rows are formed in the wordline direction while the columns are formed in bit line direction. Each flash cell comprises a lower floating gate 454 having a relatively high work function (i.e., higher than n+ polysilicon), and interlayer or interpoly dielectric (not shown), a control gate 452, and a source region 464 and a drain region 466. A common control gate 452, (or wordline) couples all flash cells of a row together while a common bit line, 330, couples all the drains 466 of a column of flash cells together as shown in Figure 3a. The bit lines are formed in a first level metallization and uses contacts 320 to couple the drains together.

Each flash cell shares a source 464 with an adjacent flash cell in the column and shares a drain 466 with the other adjacent cell in the column. Shallow trench isolation regions 424 isolate a column of flash cells from an adjacent column of flash cells as shown in Figure 3a. A common source rail 432 which runs parallel to the wordline direction couples a row of shared source regions 464 together. The common source rail 332 is formed through the isolation regions by removing the portion 462 of the isolation region 424 between the shared source regions 464 prior to implanting ions for the formation of source regions 464 as shown in Figure 3c. In this way, the common source regions 464 in a row can be coupled together as shown in Figure 3d thereby requiring only a single contact 322 to be made for every two rows of flash cells (e.g., second and third rows). Since the source rail 332 is used to couple the shared source region 464 together, individual contacts are not necessary at the shared source regions enabling minimum spacing to be utilized between adjacent flash cells having a common source thereby increasing the density of the memory cells.

A method of forming a flash memory integrated a circuit in accordance with embodiments of the present invention will now be explained with respect to cross-sectional illustrations shown in Figures 4-33.

According to the present invention a silicon substrate is provided in which the flash integrated circuit of the present invention is to be fabricated. In an embodiment of the present invention the substrate 400 includes a monocrystalline silicon substrate 402 having a p-type epitaxial silicon film 404 with a dopant density of between 5x10 - 5x10 atoms/cm formed thereon.

The starting substrate need not, however, be a silicon epitaxial film formed on a monocrystalline silicon substrate and can be other types of substrates. For the purpose of the present invention a substrate is defined as the starting material on which devices of the present invention are fabricated.

According to the present invention first isolation regions are formed in substrate 400. In order to fabricate high density integrated circuits the isolation region are preferably shallow trench isolations (STI) regions. An STI can be fabricated by thermally growing a pad oxide layer 406 of about 40θA onto the surface of substrate 400 and then forming a silicon nitride layer 408 having the thickness of approximately 150θA onto the pad oxide layer 406, as shown in Figure 4. (Figures 4-20 are all taken along the wordline direction)

Next, as shown in Figure 5, a photoresist mask 410 is formed using well known masking, exposing, and developing techniques over nitride layer 408 to define locations 412 where isolation regions are desired. Isolation regions will be used to isolate a column of cells from an adjacent column of cells and for isolating the periphery active regions. Next, well known etching techniques are used to remove silicon nitride layer 108 and pad oxide layer 406 from locations 412 where isolation regions are desired. Nitride layer 408 can be plasma etched using a chemistry comprising sulfur hexaflouride (SF₆) and helium (He) and pad

oxide 406 can be plasma etched with carbon hexaflouride (C₂F₆) and helium

(He).

Next, as shown in Figure 5 silicon substrate 406 is etched to form trenches 414 where isolation regions are desired. The silicon trench etching step of the present invention forms a trench 414 with tapered sidewall 416. Sidewalls 416 are tapered or sloped to help enable a low source resistance rail to be formed. Sidewalls 416 are formed with a slope of between 60° to 80° from horizontal (i.e., from the silicon substrate surface) and preferably at 65° from horizontal.

Tapered sidewalls 416 can be formed by plasma etching with chlorine (Cl₂) and helium (He). In an embodiment of the present invention trenches 414 are formed to a depth between 3000 to 4000 A into silicon substrate 400.

Next, as shown in Figure 6, photoresist mask 410 is removed and a thin, approximately 400 - 30θA thermal oxide 413 is grown over the sidewalls of trench 414. Thermal oxide 413 can be grown by heating substrate 400 to a temperature between 900-1000°C while exposing the substrate to an oxidizing ambient such as but not limited to 0₂. Next, the thermal oxide 413 is etched away using a wet etchant such as hydroflouric acid (HF). Next, as shown in Figure 7, (along the wordline direction) a second thermal oxide 418 having a thickness between 300-600A is grown on the silicon sidewalls of trench 414. In an embodiment of the present invention thermal oxide 418 is grown with a two step oxidation process, at first oxidation occurring in a dry ambient, such as 0₂, followed by a second oxidation occurring in a wet ambient (i.e., in an ambient including water (H20)). The oxide growth/etch/oxide growth process of the present invention rounds the silicon corners 419 of trench 414. It is to be appreciated that sharp trench corners can cause a weakness in the subsequently formed tunnel oxide at the corners. A weak tunnel oxide at the trench corners can cause cells in a single block to erase differently when tunneling electrons off the floating gate. By rounding the trench corners with the oxide growth /etch /oxide growth process of the present invention corners are rounded and all memory cells in a given memory block can erase at the same rate. Rounded corners 419 of trench 414 enable the reliable integration of shallow trench isolation (STI) regions with flash memory cells. Corner rounding also improves the performance of cmos devices in the periphery. In an alternative method for rounding trench corners 419 one can first expose trench 414 to an HF dip to remove a portion of the pad oxide beneath the silicon nitride film and then grow oxide film 413 to round the corners. If desired trench oxide 413 can then be etched away followed by the formation of oxide 418.

Next, as shown in Figure 8 a trench fill material 420 such as silicon oxide, is blanket deposited by chemical vapor deposition (CVD) over silicon nitride layer 306 and thermal oxide layer 418 in trench 414. The dielectric fill material 420 is then polished back by chemical mechanical polishing until the top surface 422 of the isolation region is substantially planar with the top surface of silicon nitride layer 408 and all oxide removed from the top of the silicon nitride as shown in Figure 8. Next, as shown in Figure 9, silicon nitride layer 408 and pad oxide layer 406 are removed with well known techniques to form a shallow, compact, and planar isolation region 424.

Next, n-type and p-type well implants are made. In one embodiment of the present invention where the peripheral circuitry utilizes CMOS circuitry (i.e. utilizes nMOS and pMOS transistors) and n-type implant is made as shown in Figure 10. A photoresist mask 426 is formed over the entire array portion of the integrated circuit and over those portions of the periphery which are to be fabricated into n-type devices. N-type dopants, such as phospherous or arsenic,

12 2 can be ion implanted at dose between 3-8 xlO atom/cm and at an energy between 400 - 800 KeV to form n-type wells in substrate 400 to act as the channel regions for the pMOS devices in the periphery.

Next, as shown in Figure 11, photoresist mask 426 is removed with well known techniques, and a second photoresist mask (now shown) is formed over the periphery of substrate 400 to define the locations where p-well implants are to be made. The p-well implant forms p- wells 428 between shallow trench isolation regions 424. The pwell regions extend deeper into substrate 400 then STI regions 424. P-wells 428 can be formed by well known ion implantation techniques utilizing boron (B ) at an energy of between 300-500 KeV and a dose

12 13 2 of between (5x10 - 2x10 atoms/cm ). Additionally, the p-well implant can be used to form p-wells in the periphery portion of integrated circuit to form channel regions for the nMOS devices in the peripheral. A p-well photoresist mask can be used to prevent doping of the pmos regions in the periphery.

Next, as shown in Figure 9, the p-well photoresist mask is removed and substrate 400 heated to drive the n-type and p-type wells to the desired depth. A sacrificial oxide layer 430 having a thickness of between 400-300A is grown over substrate 400 during the drive step. Next, p-type dopants can be implanted into the array portion of the integrated circuit in order to optimize the electrical characteristics of the flash cell.

The sacrificial oxide layer 430 is then stripped off by well known techniques, such as an HF dip, and a high quality tunnel oxide layer 132 having a thickness between 60-120A is grown over substrate 400 as shown in Figure 13. A high quality tunnel oxide can be formed by thermal oxidation of the silicon substrate by exposing silicon substrate 400 to an oxidizing ambient, such as 0₂ while heating substrate 400 to a temperature of between 750 - 950°C in either a furnace or a rapid thermal processor (RTP).

Next, a floating gate material 134 is blanket deposited over substrate 100 including isolation regions 124 as shown in Figure 14. The floating gate material layer is a layer which will be used to form the floating gates with the electrically erasable nonvolatile memory device of present invention. Floating gate material 134 is a film or a composite of films which has a work function greater than the work function of n+ polycrystalline silicon (approximately 4.1 electron volts). In an embodiment of the present invention the work function of the floating gate material 134 is greater than or equal to 4.6 electron volts and ideally greater than or equal to 5.1 electron volts.

In an embodiment of the present invention floating gate material 134 is p- type polycrystalline silicon which is doped to a concentration level between

17 20 3

1x10 - 1x10 atoms/cm . In one embodiment of the present invention the

18 19 floating gate material is polysilicon doped to a level between 5x10 - 5x10

3 atoms /cm so that when the fabricated electrically erasable nonvolatile memory device is erased, at least the bottom portion of the p-type polycrystalline silicon floating gate inverse into n-type polysilicon crystalline silicon. A suitable p-type polysilicon film can be formed by depositing a polysilicon film by for example chemical vapor deposition to a thickness between 1000-3000 A. The polycrystalline film can then be doped with p-type impurities (e.g., boron) during the deposition of the polysilicon film (i.e., insitu doping) or by ion implantation after the polysilicon film has been formed. An undoped polysilicon film can be suitably doped with boron atoms by implanting boron

11 12 15

(B ) at an energy between 1-30 KeV and a dose of between 1x10 - 3x10

2 atoms /cm to enable the fabrication of a p-type polycrystalline silicon floating gate electrode.

It is to be appreciated that because oxides, such as potentially tunnel dielectric 432 are poor diffusion barriers to boron, care should be taken to anticipate additional doping of the channel region (p-well 428) of the device by subsequent out diffusion of p-type impurities from the p-type polycrystalline floating gate.

In an embodiment of the present invention floating gate material 434 is a metal having a work function greater than or equal to 4.6 electron volts and preferably greater than 5.1 electron volts. In one embodiment floating gate material 434 is cobalt, in another embodiment of the present invention floating gate material 434 is molybdenum, and in yet another embodiment of the present invention floating gate material 434 is tungsten. It is to be appreciated that, as set forth above, that many materials, metals, and /or suicides having a suitable work function can be used for use as floating gate material 434. A metal or suicide floating gate material 434 can be formed by any well known technique including sputter deposition and chemical vapor deposition.

Next, as shown in Figure 15, a photoresist mask 436 is formed over substrate 100 to initially define the locations where floating gate lines are to be formed from floating gate material layer 434. Next, as also shown in Figure 13, the floating gate material layer is etched with well known techniques in alignment with photoresist mask 436 to pattern the floating gate material layer 434 into a plurality of floating gate lines 438. The patterning of the floating gate material layer 434 defines a plurality parallel lines in the floating gate material layer that run into and out of the page of Figure 13. (i.e., lines 138 extend in the bit line direction).

Next, as shown in Figure 16, photoresist layer 136 is removed. An interlayer or interpoly dielectric 440 is then blanket formed over and around the patterned floating gate lines 438 and over trench isolation regions 424. In an embodiment of the present invention interpoly dielectric is a composite oxide comprising a lower thermally grown oxide film, a middle deposited silicon nitride film and a top deposited oxide film. Such an the interlayer dielectric is sometimes referred to as a ONO dielectric. It is to be appreciated however, that other well known interlayer dielectrics may be utilized. In an embodiment of the present invention the ONO stack has a thickness between 150-250A. At this time, if desired, boron ions can be implanted into the periphery portion of the integrated circuit in order to adjust the threshold voltage of the nMOS devices, and arsenic and phosphorus can be implanted into pMOS devices to adjust their threshold voltages. Next, as shown in Figure 17, a photoresist mask 442 is formed over substrate 400 and covers the array portion of the integrated circuit and exposes the periphery portion of the integrated circuit. Next, as shown in Figure 17, the interlayer dielectric 440 is removed from the peripherial portion of the integrated. Next, as shown in Figure 18, a gate dielectric layer 444 is grown on the silicon substrate 100 in the periphery of integrated circuit. Next, as shown in Figure 19, a polysilicon layer 446 is blanket deposited over substrate 400. The polysilicon layer 446 is formed over the interlayer dielectric 440, over floating gate lines 438, and over interlayer dielectric 440 over the shallow trench isolation regions 424 in the array portion of integrated circuit and is formed over the gate oxide layer 444 in the peripherial portion of integrated circuit. In an embodiment of the present invention polysilicon layer 446 is deposited to a thickness between 3000-5000A. Polysilicon film 446 can be formed by any well known techniques such as by chemical vapor deposition and can be insitu doped or subsequently doped by ion implantation if desired. In an embodiment of the present invention polysilicon film 446 remains undoped at this time and is subsequently doped by the cell and cMOS source /drain implant.

Next, as shown in Figure 20, a polysilicon layer 446 is planarized by chemical mechanical polishing in order to form a planar top surface 448. In an embodiment of the present invention polysilicon layer 446 is polished until approximately between 2000-2500A of polysilicon remains above interlayer dielectric 440. The planar surface 448 of polysilicon layer 446 enables improved lithography for the subsequent patterning or delineation of polysilicon layer 446. Polishing of polysilicon layer 446 is crucial for enabling good critical dimension (CD) control during subsequent patterning of polysilicon layer 446. Polishing of polysilicon layer 446 helps enable high density fabrication of flash cells.

Next, as shown in Figures 21a and 21b, a photoresist mask 450 is formed over substrate 400 and the exposed portions of polysilicon film 446, interlayer dielectric 440, and floating gate lines 438 are anisotropically etched in alignment with photoresist mask 450 in order to form a plurality of flash cells and control lines. Figure 21a is a cross-sectional view of substrate 400 taken along the word line direction while Figures 21b is a cross-sectional view taken along the bit line direction (Figure 21a is perpendicular to the cross-section of Figure 21b). As shown in Figures 21a and 21b, the masking and etching processes patterns second polysilicon layer 446 into a plurality of control gate lines 452, as shown in Figure 21b. Each of the control gate lines 452 extend in the word line direction and pass over each of the poly floating gates along a row in a word line direction as shown in Figure 21. Additionally, as shown in Figure 21 the masking and etching process also removes the exposed portion of floating gate lines 438 in order to define a plurality of discrete floating gates 454. That is, the masking and etching steps remove the portion of polysilicon lines 438 which are not covered by control gate lines 452 as shown in Figure 21b. Additionally, as shown in Figure 21b, the masking and etching steps form a plurality of floating gate 454 /dielectric 440 /poly452/ stacks 456. As shown in Figure 21b, a cell stack in the column are separated on one side from the adjacent cell by the minimum spacing 458 which can achieved by the photolithography /etching technique used. For example, if the photolithography /etching technique can form lines having a 0.25 micron dimension then the cells which have a shared source will be separated by the minimum 0.25 micron dimension. Additionally, adjacent stacks which share a common drain are separated by dimension 459 which are large enough to form a metal contact to the common drain regions. Polysilicon layer 446, can be anisotropically etched utilizing a plasma etch comprising the chemistry of HBr, chlorine (C12) and helium (He) and ONO dielectric 140 can be plasma etched using C₂F₆ and 0₂. If floating gate material 434 is p-type polysilicon then it can be etched in the same manner as polysilicon layer 446, if floating gate material 434 is a metal than any suitable anisotropic etching technique for the metal such as plasma etching or reactive ion etching may be used.

Next, as shown in Figure 22a and 22b, a mask 160 is formed over substrate 400. Figure 20a is a cross-sectional view through the cell source/ drain region taken along the bit line direction while Figure 20b is a cross-sectional view through a STI region (424) taken along the bit line direction. Mask 460 defines location where a source rail will be formed which connects a row of shared source regions. Mask 460 exposes portion 458 of substrate 400 between each of the flash cell pairs where the common source is to be formed. The mask also exposes the portion 462 of shallow trench isolation region located between the common source regions making up a row of common source regions see also Figure 3b. Next, as also, shown in Figure 22a and Figure 22b substrate 400 is exposed to an oxide etchant which is highly selective to silicon (i.e., exposed to an etchant which etches oxide but not silicon). An etchant having an at least 20:1 selectivity between oxide and silicon is preferred. The oxide etchant removes the portion of shallow trench isolation regions exposed by mask 462. The exposed shallow isolation region is etched until all of the exposed oxide is removed to expose the underlying portion of p-type epitaxial substrate (see also Figure 3c). Removing portions 462 of STI regions 424 forms a continuous row of silicon which will eventually form a continuous source rail for electrically coupling a row of shared source regions see also Figure 2c.

Next, as shown in Figure 23 (along the bit line direction) n-type source/drain implants are made into the array. According to the present invention n-type dopants are implanted into substrate 400 on opposite sides of

75 stacks 456. In an embodiment of the present invention arsenic (As ) ions are blanket implanted into the array portion of substrate 400 at a dose of between 1.0

15 2 to 3.0x10 atom/cm at an energy of between 10-20 KeV while the periphery is masked. The n-type source /drain implant use a 90° implant angle (i.e., ions are implanted perpendicular to the surface of substrate 400) as shown in Figure 23. The ion implantation step forms the shared source regions 464 and forms a shared drain region 466 between flash cells. In this way each flash cell shares a drain with an adjacent flash cell in the column and shares a source with the other adjacent flash cell in the column. Additionally, the source/drain implant also places dopants into substrate portion 463 were STI portion 462 was removed. (Figure 3d) Because the source/drain ion implant step in the array is not masked the control gate 452 acts as the mask preventing the n-type dopants from doping the channel region of the flash cells. The source /drain implant step also dopes the second polysilicon layer in the array alleviating the need for a separate doping step to dope the floating gate layer. The relatively low energy source /drain implant forms shallow and abrupt source /drain regions.

Next, as shown in Figure 24, (along the bit line direction) a mask 468 similar to mask 460 is formed over substrate 400. Mask 468 exposes the common source regions 464 and the doped silicon regions 463 between the common source region 464 where portion 462 of STI regions 424 were removed. Next, as shown in Figure 22 second ion implantation of n-type dopens can be formed into the common source regions and into the doped silicon substrate regions 463 in order to increase the conductivity type of a source region and to increase the conductivity of the source rail to thereby reduce the resistivity of the rail and improve performance. The additional source implant can be carried out

31 utilizing a first doping of phospherous atoms (P ) at an energy between 10-20

14 2

KeV and at a dose of between 1-10x10 atoms/cm followed by a second doping

with arsenic atoms (As ) at a dose between 2-5x10 atoms/cm at an energy between 16-20 KeV. Like the source/drain implant the source implant implants ions perpendicular (90°) to the surface of the substrate. The source/drain implant and the source implant create a low resistance shared source regions 464 and a low resistance source rail in the substrate portion 463 connecting the shared source /drain regions 464. By utilizing the additional source doping techniques shown in Figure 22, asymmetrical source and drain doping profiles are achieved for the flash cells. The drain regions have a relatively shallow and uniform doping profile, while the sources 464 have a relatively deep and graded profile. Additionally, shared source regions 464 are doped to a higher concentration in order to help reduce the source rail resistance. The ion implantation steps create a source rail having a resistance of between 400-300 ohms /cell.

Referring to Figures 3a -3d, the low resistance source rail fabrication aspect of the present invention is further described. Figure 3a is an over head view of the array portion of integrated circuit. Figure 3b is a cross-sectional view of Figure 3b taken in the wordline direction through the shared source regions after formation of mask 160 (in Figure 20) and prior to the etching of STI portion 462. As is readily apparent in Figure lb the masking step shown in Figure 22 exposes the silicon substrate 458 where the shared source drain regions are to be regions formed and exposes the STI portion 462 located between silicon substrate 458. Next, as shown in Figure 3d, the highly selective oxide etch of Figure 22 removes those portions 462 of the STI regions between regions 458 in a row of the array to reveal substrate portions 463 beneath the removed portions 462. Next, as shown in Figure 3d, during the source /drain doping described with respect to Figures 23 and the source doping shown in Figure 24, substrate area 450 is doped to form common source region 464. Additionally, the doping of Figures 23 and 24 also doped the silicon portion 463 between shared source regions 464 shown in Figure 3d. Thus, each shared source region in a row is coupled by a doped substrate region 463 to the adjacent shared source region 464 as to form a source rail 332 for a row of cells. A single contact point 322(which is eventually silicided) is used to electrically connect the source rail 332 to circuitry of the integrated circuit. Because sidewalls 416 of STI 424 where adequately sloped during the formation of trench 414, 90° angled implantation steps can be used to adequately dope the sidewalls of silicon region 463 without the use of an elaborate doping technique such as large angled implant. The source rail 332 is heavily doped silicon having an n-type doping

19 3 density of at least 5x10 atoms/per cm . The minimum depth of the source rail

332 which occurs at the sidewalls 416 is at least 0.1 microns thereby enabling a low resistance source rail 200 to be formed.

Next, the second polysilicon layer in the peripherial portion of integrated circuit can now be masked exposed and etched to pattern the second polysilicon layer into gates in the peripherial portion of the integrated circuit. This step can be formed prior to forming cell gates and cell source /drain regions.

Next, as shown in Figure 25, (along the bit line direction), a thin thermal oxide 470 is grown over the top and over the sidewalls of the flash cells and over the exposed portions of a silicon substrate 400 (e.g., source/drain regions 464 and 466 and source rail portions 463). The thermal oxide passivates the sidewalls of the flash cells as well as thickens the oxide near the gate edges. Next, a thin, approximately 20θA, high temperature oxide 472 (HTO) is blanket deposit by CVD over the thermal oxide 470 as shown in Figure 22. The high temperature oxide acts as an etch stop for a subsequent silicon nitride spacer etch step.

At this time one can form n-type tip regions in the periphery portion of the substrate to form n-type tip regions for the nMOS devices in the periphery. Additionally, at this time p-type tip implants for the periphery portion of the circuit can be made. During the p-type and n-type tip implants of the periphery portion of the circuit a mask covers the array portion of the substrate so that no doping of the array portion occurs. Next, a silicon nitride film 474 is blanket deposited over substrate 400 as shown in Figure 26 (taken along the bit line direction). Silicon nitride film 474 will be used to form spacers. The deposition thickness of the silicon nitride film 474 dictates the width of the subsequently formed spacers. Silicon nitride layer 474 is formed to a thickness at least half the distance 473 (see Figure 23) between flash cells having a shared source 464 so that the narrow source space 473 between cells having shared source is completely filled with silicon nitride 474 as shown in Figure 24. In, an embodiment of the present invention silicon nitride film 474 is deposited to a thickness of between 1200- 2500 A. In a case when the narrow source space 473 between the flash cell having a shared source is approximately 0.25 microns, silicon nitride film 474 is formed to a thickness of approximate 125θA. Any well known technique which can be used to deposit a comformal silicon nitride layer, such as chemical vapor deposition utilizing source gases comprising ammonia NH₃ and silane SiH₄ can be used to deposit silicon nitride film 474.

Next, as shown in Figure 27 (along the bit line direction) silicon nitride film 474 is anisotropically etched to form a plurality of spacers 476 which run along sidewalls of each flash stack. Additionally, the anisotropic etch leaves a silicon nitride stud 478 in the narrow source gap between the cells sharing a source region. Silicon nitride stud 478 prevents contaminants from subsequent processing steps from adversely effecting the reliability and quality of the tunnel oxide and interpoly dielectric. Deposited oxide layer 472 acts as an etch stop for the anisotropic silicon nitride etch step. Any anisotropic etching technique which preferentially etches silicon nitride as compared to silicon dioxide can be used, such as plasma etching utilizing the chemistry comprising sulfur hexaflouride (SF₆) and helium (He). The silicon nitride etch step also forms spacers 476 which run along laterally opposite sidewalls of patterned polysilicon layer 446 in the peripheral portion of the integrated circuit. Next, as shown in Figure 28 (along the bit line direction) an etch step is used to remove the oxide films 472 and 470 from the active regions not protected by the nitride spacers as well as from the top of the second polysilicon layer. A plasma etch using a chemistry comprising carbon hexaflouride (C₂F₆) and helium can be used to remove oxide films 472 and 470. Next, at this time an n+source/drain implant mask can be formed which covers the entire array portion of integrated circuit and covers the pMOS portion of the periphery of the integrated circuit and then heavy n+source/drain implants made for the nMOS devices. Similarly at this time a p+source/ drain implant mask can be formed over the array portion of integrated circuit and over those portion of the periphery used to form nMOS devices and then heavy p+source /drain implants made into the peripherial circuit. During the n+source/drain implant and p+source/drain implant made into the peripherial circuit, the array portion is masked in order to prevent the relatively deep implants made into the periphery from affecting the relatively shallow drain 466 and the graded source 464 formed in the array portion of integrated circuit.

Next, as shown in Figure 29, (along the bit line direction), a metal film 480 is blanket deposited over substrate 400. Any metal film which can react with silicon to form a low resistance metal suicide when heated to a suitable temperature may be utilized. Prior to metal film deposition a short HF dip can be used to remove any native oxides. In a preferred embodiment of the present invention the metal film 480 is titanium deposited to a thickness between 200 - 50θA. Any well known technique such as but not limited to sputtering, can be

28 used to blanket deposit metal film 480. If desired, silicon atoms (Si ) can be

5 2 implanted into metal film 480 at a dose of between 2-4x10 atoms/cm and at an energy between 20-30 KeV. Next, as shown in Figure 30, (along the bit line direction) substrate 400 is heated to a temperature sufficient to cause metal film 480 to react with silicon to form a metal silicide. Metal silicide forms on those locations where silicon is available for reaction with the metal and is indirect contact with the metal. As such, metal silicide 482 forms on the top of polysilicon control gates, on the drain regions 466, and on the source rail contact regions (not shown) as well as on the source /drain regions and on the gate of MOS devices in the periphery of integrated circuit and polysilicon interconnects. Metal film 480 remains unreacted over areas where there is no silicon available for reaction such as dielectric layers, including sidewall spacers 476, silicon nitride plug 478, and shallow trench isolation regions 424. In a preferred embodiment of the present invention, silicide 482 formed is low resistance titanium silicide (TixSiy) preferably in the C-54 phase. Any suitable heating or annealing process can be used to form metal silicide 482 including a furnace anneal or a rapid thermal anneal.

Next, as also shown in Figure 31, unreacted metal is etched away with an etchant which selectively removes the unreactive metal but does not remove the formed metal silicide 482. A wet etchant comprising H₂0₂/NH₄OH/H₂0 can be utilized to selectively remove the titanium metal without etching the titanium silicide.

Next, as illustrated in Figure 32, (along the bit line direction), and interlayer dielectric 484 is blanket deposited over substrate 400. Interlayer dielectric 484 can be any suitable dielectric such as silicon dioxide and can be a composite dielectric comprising a plurality of different deposited dielectrics. Next, as also shown in Figure 31, interlayer dielectric 484 is planarized by chemical mechanical polishing to form a planar top surface 486. ILD layer 484 should be deposited to a thickness sufficient to enable a sufficient amount of dielectric to be removed so that a sufficiently planar top surface 484 can be achieved while still leaving a sufficient amount of dielectric, for example between 3500-4500A of interdielectric, above the highest features (e.g., silicon flash cells) to sufficiently isolate the features from a subsequently formed metal line on planar surface 486.

Next, electrical contacts 488 are formed through interlayer dielectric 484 as shown in Figure 32, (taken along the bit line direction). In the present invention electrical contact 488 are formed to each of the shared drain regions, to each of the control gates, and to each source rail contact area, as well as to source /drain regions and gates of the pMOS and nMOS devices in the peripherial integrated circuit. In the present invention all contacts 488 are made to low resistance silicide regions 482. Contacts 488 can be formed by any well known techniques. In an embodiment of the present invention contacts 488 are formed by forming a photoresist mask over interlayer dielectric 484 which defines locations where contacts 488 are desired. Using the mask via holes are then etched through the interlayer dielectric 484 down to the silicide regions 482. An etchant which preferentially etches interlayer dielectric 484 but which does not etch silicide 482 is preferably used. The mask is then removed and a barrier layer such as but not limited to titanium /titanium nitride is blanket deposited over the interlayer dielectric and into the via openings. Next, a tungsten film can be blanket deposited by chemical vapor deposition over the barrier layer and into the formed via openings. The tungsten film is formed to a thickness which completely fills the via openings. The tungsten film and the barrier layers can then be chemically mechanically polished back to remove the films from the top surface of interlayer dielectric thereby form Ti/TiN/W contacts 488.

Next, as shown in Figure 31, taken along the bit line direction a first level of metallization such as aluminum is blanket deposited by any well known technique such as sputtering over the planar surface of ILD 484. Metal film 490 may or may not include barrier layer such as titanium and /or a capping layer such as titanium /titanium nitride if desired. Next, the metal film is patterned using well known photolithography and etching techniques as shown in Figure 31.

Patterned metal 1 can be used to form bit lines in the array portion which contact the shared drains through contact 488 as shown in Figure 33. The back end processing techniques illustrated in Figures 31, 32 and 33 can be continued to add as many levels of metallization as desired to interconnect the various devices and memory cells fabricated on substrate 400. After the last level of metallization is formed and patterned well known passivation films are formed in order to hermetically seal the integrated circuit. At this point the fabrication of a nonvolatile integrated circuit in accordance with the present invention is complete.

Claims

TN THE CLAIMSWe claim:

1. A nonvolatile memory device comprising: a tunnel dielectric formed on a p-type silicon region; a floating-gate formed on said tunnel dielectric layer, said floating-gate having a work function of greater than 4.1 electron volts; a dielectric layer on said floating-gate; and a control gate on said dielectric layer.

2. The memory device of claim 1 wherein said floating-gate is p-type polysilicon.

3. The memory device of claim 2 wherein said p-type polysilicon floating gate

17 20 3 is doped with boron atoms to a doping density of 1x10 - 1x10 atoms/cm .

4. The memory device of claim 2 wherein said floating-gate is doped with p- type impurities to a level such that during electrical erase of the nonvolatile memory the floating-gate forms an n-type surface layer in said floating-gate.

5. The memory device of claim 1 wherein said floating gate comprises a metal.

6. The memory device of claim 5 wherein said floating-gate comprises platinum.

7. The memory device of claim 5 wherein said floating-gate comprises cobalt.

8. The electrical memory device of claim 5 wherein said floating-gate comprises tungsten.

9. The nonvolatile memory device of claim 1 wherein said floating gate comprises a material selected from the group consisting of cobalt, platinum, molybdenum, tungsten, nickel silicide, titanium silicide, tungsten silicide, cobalt silicide, molybdenum silicide and titanium nitride.

10. A nonvolatile memory device comprising: a tunnel dielectric formed on a p-type silicon region; a p-type polysilicon floating-gate formed on said tunnel dielectric; a dielectric formed on said p-type polysilicon floating-gate; and a control gate formed on said dielectric on said p-type polysilicon floating gate.

11. The memory device of claim 10 wherein said p-type polysilicon floating-

18 19 gate is doped with boron atoms to a doping density of 5x10 - 5x10

atoms /cm .

12. The memory device of claim 10 wherein said p-type polysilicon floating- gate is doped to a level so that while erasing said memory device said floating inverts forming n-type surface layer on said tunnel dielectric.

13. A method of forming a nonvolatile memory comprising: forming a tunnel dielectric on a p type silicon region; forming a floating-gate on said tunnel dielectric, wherein said floating- gate has a work function of greater than 4.1 electron volts; forming a dielectric layer on said floating-gate; and forming a control gate on said dielectric layer on said floating gate.

14. The method of claim 13 wherein said floating-gate is formed from p-type polysilicon.

15. The method of claim 13 wherein said floating-gate comprises a metal.

16. The method of claim 15 wherein said metal is selected from the group consisting of platinum, cobalt, and tungsten.

17. The method of claim 13 wherein said floating gate comprises a metal- silicide.

18. The method of claim 13 wherein said floating gate comprises titanium nitride.

19. The method of claim 13 wherein said floating gate comprises a material selected from the group consisting of cobalt, platinum, molybdenum, tungsten, nickel silicide, titanium silicide, tungsten silicide, cobalt silicide, molybdenum silicide and titanium nitride.