WO2001028097A1 - Heterogeneous interconnection architecture for programmable logic devices - Google Patents
Heterogeneous interconnection architecture for programmable logic devices Download PDFInfo
- Publication number
- WO2001028097A1 WO2001028097A1 PCT/US2000/028189 US0028189W WO0128097A1 WO 2001028097 A1 WO2001028097 A1 WO 2001028097A1 US 0028189 W US0028189 W US 0028189W WO 0128097 A1 WO0128097 A1 WO 0128097A1
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- WO
- WIPO (PCT)
- Prior art keywords
- wires
- pld
- interconnect
- switches
- speed
- Prior art date
Links
- 230000008878 coupling Effects 0.000 claims description 9
- 238000010168 coupling process Methods 0.000 claims description 9
- 238000005859 coupling reaction Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 28
- 239000000872 buffer Substances 0.000 description 21
- 238000010586 diagram Methods 0.000 description 11
- 230000006870 function Effects 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000015654 memory Effects 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000011664 signaling Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001530205A JP4847663B2 (en) | 1999-10-12 | 2000-10-12 | Heterogeneous interconnect architecture for programmable logic devices |
EP00972101A EP1224737A1 (en) | 1999-10-12 | 2000-10-12 | Heterogeneous interconnection architecture for programmable logic devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/478,097 | 1999-10-12 | ||
US09/478,097 US6590419B1 (en) | 1999-10-12 | 1999-10-12 | Heterogeneous interconnection architecture for programmable logic devices |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001028097A1 true WO2001028097A1 (en) | 2001-04-19 |
WO2001028097A9 WO2001028097A9 (en) | 2002-05-10 |
Family
ID=23898500
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/028189 WO2001028097A1 (en) | 1999-10-12 | 2000-10-12 | Heterogeneous interconnection architecture for programmable logic devices |
Country Status (4)
Country | Link |
---|---|
US (2) | US6590419B1 (en) |
EP (1) | EP1224737A1 (en) |
JP (2) | JP4847663B2 (en) |
WO (1) | WO2001028097A1 (en) |
Cited By (5)
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WO2004079909A2 (en) * | 2003-03-03 | 2004-09-16 | Xilinx, Inc. | Fpga architecture with mixed interconnect resources |
US7389485B1 (en) | 2006-03-28 | 2008-06-17 | Xilinx, Inc. | Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures |
US7893712B1 (en) | 2009-09-10 | 2011-02-22 | Xilinx, Inc. | Integrated circuit with a selectable interconnect circuit for low power or high performance operation |
US8987868B1 (en) | 2009-02-24 | 2015-03-24 | Xilinx, Inc. | Method and apparatus for programmable heterogeneous integration of stacked semiconductor die |
US9015023B2 (en) | 2010-05-05 | 2015-04-21 | Xilinx, Inc. | Device specific configuration of operating voltage |
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US6590419B1 (en) * | 1999-10-12 | 2003-07-08 | Altera Toronto Co. | Heterogeneous interconnection architecture for programmable logic devices |
US6465884B1 (en) * | 2000-05-24 | 2002-10-15 | Agere Systems Guardian Corp. | Semiconductor device with variable pin locations |
US6724220B1 (en) | 2000-10-26 | 2004-04-20 | Cyress Semiconductor Corporation | Programmable microcontroller architecture (mixed analog/digital) |
US7765095B1 (en) | 2000-10-26 | 2010-07-27 | Cypress Semiconductor Corporation | Conditional branching in an in-circuit emulation system |
US8176296B2 (en) | 2000-10-26 | 2012-05-08 | Cypress Semiconductor Corporation | Programmable microcontroller architecture |
US8103496B1 (en) | 2000-10-26 | 2012-01-24 | Cypress Semicondutor Corporation | Breakpoint control in an in-circuit emulation system |
US8149048B1 (en) | 2000-10-26 | 2012-04-03 | Cypress Semiconductor Corporation | Apparatus and method for programmable power management in a programmable analog circuit block |
US7024653B1 (en) * | 2000-10-30 | 2006-04-04 | Cypress Semiconductor Corporation | Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD) |
US6605962B2 (en) * | 2001-05-06 | 2003-08-12 | Altera Corporation | PLD architecture for flexible placement of IP function blocks |
US6621325B2 (en) * | 2001-09-18 | 2003-09-16 | Xilinx, Inc. | Structures and methods for selectively applying a well bias to portions of a programmable device |
US7406674B1 (en) | 2001-10-24 | 2008-07-29 | Cypress Semiconductor Corporation | Method and apparatus for generating microcontroller configuration information |
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US6971004B1 (en) | 2001-11-19 | 2005-11-29 | Cypress Semiconductor Corp. | System and method of dynamically reconfiguring a programmable integrated circuit |
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US7844437B1 (en) | 2001-11-19 | 2010-11-30 | Cypress Semiconductor Corporation | System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit |
US8103497B1 (en) | 2002-03-28 | 2012-01-24 | Cypress Semiconductor Corporation | External interface for event architecture |
US7154299B2 (en) * | 2002-04-05 | 2006-12-26 | Stmicroelectronics Pvt. Ltd. | Architecture for programmable logic device |
US7308608B1 (en) | 2002-05-01 | 2007-12-11 | Cypress Semiconductor Corporation | Reconfigurable testing system and method |
US7761845B1 (en) | 2002-09-09 | 2010-07-20 | Cypress Semiconductor Corporation | Method for parameterizing a user module |
US7084666B2 (en) * | 2002-10-21 | 2006-08-01 | Viciciv Technology | Programmable interconnect structures |
US6831480B1 (en) * | 2003-01-07 | 2004-12-14 | Altera Corporation | Programmable logic device multispeed I/O circuitry |
US7306977B1 (en) * | 2003-08-29 | 2007-12-11 | Xilinx, Inc. | Method and apparatus for facilitating signal routing within a programmable logic device |
US7243312B1 (en) | 2003-10-24 | 2007-07-10 | Xilinx, Inc. | Method and apparatus for power optimization during an integrated circuit design process |
US7622947B1 (en) * | 2003-12-18 | 2009-11-24 | Nvidia Corporation | Redundant circuit presents connections on specified I/O ports |
DE102004006769B3 (en) * | 2004-02-11 | 2005-08-11 | Infineon Technologies Ag | readout device |
US7295049B1 (en) | 2004-03-25 | 2007-11-13 | Cypress Semiconductor Corporation | Method and circuit for rapid alignment of signals |
US8069436B2 (en) | 2004-08-13 | 2011-11-29 | Cypress Semiconductor Corporation | Providing hardware independence to automate code generation of processing device firmware |
ITMI20041675A1 (en) * | 2004-08-30 | 2004-11-30 | St Microelectronics Srl | SWITCHING BLOCK AND RELATED SWITCHING MATRIX, IN PARTICULAR FOR FPGA ARCHITECTURES. |
US7181712B2 (en) * | 2004-10-27 | 2007-02-20 | Lsi Logic Corporation | Method of optimizing critical path delay in an integrated circuit design |
US7332976B1 (en) | 2005-02-04 | 2008-02-19 | Cypress Semiconductor Corporation | Poly-phase frequency synthesis oscillator |
US7400183B1 (en) | 2005-05-05 | 2008-07-15 | Cypress Semiconductor Corporation | Voltage controlled oscillator delay cell and method |
US7268587B1 (en) | 2005-06-14 | 2007-09-11 | Xilinx, Inc. | Programmable logic block with carry chains providing lookahead functions of different lengths |
US7256612B1 (en) | 2005-06-14 | 2007-08-14 | Xilinx, Inc. | Programmable logic block providing carry chain with programmable initialization values |
US7253658B1 (en) | 2005-06-14 | 2007-08-07 | Xilinx, Inc. | Integrated circuit providing direct access to multi-directional interconnect lines in a general interconnect structure |
US7276934B1 (en) | 2005-06-14 | 2007-10-02 | Xilinx, Inc. | Integrated circuit with programmable routing structure including diagonal interconnect lines |
US7804719B1 (en) | 2005-06-14 | 2010-09-28 | Xilinx, Inc. | Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode |
US7202698B1 (en) * | 2005-06-14 | 2007-04-10 | Xilinx, Inc. | Integrated circuit having a programmable input structure with bounce capability |
US7274214B1 (en) | 2005-06-14 | 2007-09-25 | Xilinx, Inc. | Efficient tile layout for a programmable logic device |
US7375552B1 (en) | 2005-06-14 | 2008-05-20 | Xilinx, Inc. | Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure |
US7265576B1 (en) | 2005-06-14 | 2007-09-04 | Xilinx, Inc. | Programmable lookup table with dual input and output terminals in RAM mode |
US8085067B1 (en) | 2005-12-21 | 2011-12-27 | Cypress Semiconductor Corporation | Differential-to-single ended signal converter circuit and method |
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US20070273403A1 (en) * | 2006-05-26 | 2007-11-29 | Tai-Cheng Wang | Clock Tree For Programmable Logic Array Devices |
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US8026739B2 (en) | 2007-04-17 | 2011-09-27 | Cypress Semiconductor Corporation | System level interconnect with programmable switching |
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JPWO2012032937A1 (en) * | 2010-09-08 | 2014-01-20 | 日本電気株式会社 | Reconfigurable circuit |
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US9000490B2 (en) | 2013-04-19 | 2015-04-07 | Xilinx, Inc. | Semiconductor package having IC dice and voltage tuners |
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US11468002B2 (en) | 2020-02-28 | 2022-10-11 | Untether Ai Corporation | Computational memory with cooperation among rows of processing elements and memory thereof |
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US5504440A (en) * | 1994-01-27 | 1996-04-02 | Dyna Logic Corporation | High speed programmable logic architecture |
US5543732A (en) * | 1995-05-17 | 1996-08-06 | Altera Corporation | Programmable logic array devices with interconnect lines of various lengths |
US5914616A (en) * | 1997-02-26 | 1999-06-22 | Xilinx, Inc. | FPGA repeatable interconnect structure with hierarchical interconnect lines |
WO2000052826A2 (en) * | 1999-03-04 | 2000-09-08 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
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-
1999
- 1999-10-12 US US09/478,097 patent/US6590419B1/en not_active Expired - Lifetime
-
2000
- 2000-10-12 EP EP00972101A patent/EP1224737A1/en not_active Withdrawn
- 2000-10-12 JP JP2001530205A patent/JP4847663B2/en not_active Expired - Fee Related
- 2000-10-12 WO PCT/US2000/028189 patent/WO2001028097A1/en not_active Application Discontinuation
-
2003
- 2003-05-30 US US10/449,753 patent/US6828824B2/en not_active Expired - Fee Related
-
2011
- 2011-01-21 JP JP2011011466A patent/JP5285718B2/en not_active Expired - Fee Related
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US5504440A (en) * | 1994-01-27 | 1996-04-02 | Dyna Logic Corporation | High speed programmable logic architecture |
US5543732A (en) * | 1995-05-17 | 1996-08-06 | Altera Corporation | Programmable logic array devices with interconnect lines of various lengths |
US5914616A (en) * | 1997-02-26 | 1999-06-22 | Xilinx, Inc. | FPGA repeatable interconnect structure with hierarchical interconnect lines |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004079909A2 (en) * | 2003-03-03 | 2004-09-16 | Xilinx, Inc. | Fpga architecture with mixed interconnect resources |
WO2004079909A3 (en) * | 2003-03-03 | 2005-01-20 | Xilinx Inc | Fpga architecture with mixed interconnect resources |
US6930510B2 (en) | 2003-03-03 | 2005-08-16 | Xilinx, Inc. | FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same |
US6960934B2 (en) | 2003-03-03 | 2005-11-01 | Xilinx, Inc. | FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same |
US7138828B2 (en) | 2003-03-03 | 2006-11-21 | Xilinx, Inc. | FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same |
US7389485B1 (en) | 2006-03-28 | 2008-06-17 | Xilinx, Inc. | Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures |
US8987868B1 (en) | 2009-02-24 | 2015-03-24 | Xilinx, Inc. | Method and apparatus for programmable heterogeneous integration of stacked semiconductor die |
US7893712B1 (en) | 2009-09-10 | 2011-02-22 | Xilinx, Inc. | Integrated circuit with a selectable interconnect circuit for low power or high performance operation |
US9015023B2 (en) | 2010-05-05 | 2015-04-21 | Xilinx, Inc. | Device specific configuration of operating voltage |
Also Published As
Publication number | Publication date |
---|---|
JP5285718B2 (en) | 2013-09-11 |
JP2003511947A (en) | 2003-03-25 |
US6828824B2 (en) | 2004-12-07 |
US20040017222A1 (en) | 2004-01-29 |
WO2001028097A9 (en) | 2002-05-10 |
EP1224737A1 (en) | 2002-07-24 |
JP4847663B2 (en) | 2011-12-28 |
JP2011087334A (en) | 2011-04-28 |
US6590419B1 (en) | 2003-07-08 |
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