WO2001040815A1 - Testing electrical circuits - Google Patents
Testing electrical circuits Download PDFInfo
- Publication number
- WO2001040815A1 WO2001040815A1 PCT/EP2000/011294 EP0011294W WO0140815A1 WO 2001040815 A1 WO2001040815 A1 WO 2001040815A1 EP 0011294 W EP0011294 W EP 0011294W WO 0140815 A1 WO0140815 A1 WO 0140815A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- currents
- voltage
- logic
- fully differential
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
- G01R31/3163—Functional testing
Definitions
- the invention relates to a method of and apparatus for testing fully differential electrical circuits, to a method of designing such circuits, and to circuits designed by such a method.
- the invention may be applied to both analogue and digital circuits.
- differential circuits Due to their structure fully differential circuits are inherently redundant circuits. Some self-testing proposals have been made that are based on this property. Those test strategies are based on observing the balance of differential voltage signals at the output of each block in the circuit. The differential voltage signals are transformed into a single ended code that is analysed using a window comparator (checker). An error signal is generated when a code falls outside the valid code space.
- the invention provides a method of testing a fully differential analogue circuit comprising the steps of exciting the circuit with a common mode signal, monitoring two symmetrical branch current signals resulting from the common mode excitation signal, and providing an indication of whether the two branch current signals are correlated.
- the invention is based on the realisation that when a fully differential circuit is excited with an input stimulus that is a pure common mode input signal, i.e. no differential mode signal is applied, the circuit response is a common mode output signal as well, and a proper correlation of two branch currents in the symmetrical structure of the circuit is observed.
- Each of the branch currents in the symmetrical structure of the fully differential circuit depends on: the common mode input signal, the differential mode input signal, the circuit topology and the bias conditions. Therefore, due to inherent properties of fully differential circuits, when no differential mode input signal is applied both branch currents in the symmetrical structure should be correlated. However, any defect due, for example to the fabrication process that affects the topology of the fully differential circuit, will lead to a mis-correlation of those branch currents, whether in their quiescent component or in their dynamic component.
- the indication as to whether the two branch signals are correlated may conveniently be in digital form.
- the method may further comprise the steps of:- i) sampling each branch current, ii) subtracting the sampled current and producing a voltage representing the subtracted currents, iii) applying the voltage produced in step ii) to a first arrangement to generate a logic 1 when the voltage is equal to or lower than a given value and a logic 0 when the voltage is higher than the given value, iv) applying the voltage produced in step ii) to a second arrangement to generate a logic 0 when the voltage is equal to or higher than the given value and a logic 1 when the voltage is lower than the given value, v) exclusively ORing the outputs of the first and second arrangements, and vi) indicating correlation in dependence on the result of the exclusive ORing.
- the given value may be a band of values.
- the first and second arrangements may be amplifiers having different threshold values.
- the invention further provides an integrated circuit including a fully differential circuit, the integrated circuit comprising a monitor circuit, said monitor circuit comprising means for sampling currents in symmetrical branches of the differential circuit, means for subtracting the sampled currents and producing an output voltage representing the subtracted currents, a first arrangement for generating a logic 1 when the voltage is equal to or lower than a given value and a logic 0 when the voltage is higher than the given value, a second arrangement for generating a logic 0 when the voltage is equal to or higher than the given value and a logic 1 when the voltage is lower than the given value, an exclusive ORgate having inputs to which the outputs of the first and second arrangements are applied, and an output indicating whether the differential circuit is faulty connected to the output of the exclusive ORgate.
- an integrated circuit containing a fully differential circuit can be provided with a self test facility for the fully differential part.
- This can provide a simplification in the testing of such circuits. That is, by selecting an appropriate part of a circuit and reconfiguring it for test purposes and then monitoring and analysing the branch currents at that part of the circuit the correct functioning of the circuit can be tested for without requiring external test equipment or access to the internal circuitry apart from being able to control the reconfiguration and access the results of the correlation.
- the given value may be a band of values.
- the first and second arrangements may be amplifiers having different threshold values. This gives a convenient way of achieving a suitable tolerancing of the testing for equality which can take into account normal process variations.
- the invention further provides a method of designing for testability fully differential electrical circuits including a test structure comprising the steps of: i) designing a fully differential circuit to perform a desired function, ii) selecting one or more parts of the circuit that pass symmetrical currents when a common mode signal is applied to the input of the circuit when the circuit is fault free, iii) providing switching means for causing said one or more parts to adopt a first configuration to enable the branch currents to be monitored for test purposes and a second configuration for normal circuit operation, and iv) providing monitoring means for monitoring the branch currents when said one or more parts adopt the first configuration.
- the invention still further provides a fully differential electrical circuit comprising a monitoring circuit for monitoring the currents in symmetrical branches of the circuit when excited by a common mode input signal, switching means for modifying a part of the circuit for test purposes to enable the current monitoring to take place and to restore said part of the circuit to its normal circuit function at other times, and test means for determining whether the currents in the symmetrical branches are substantially equal under test conditions.
- the circuit includes the means for checking its functionality.
- the circuit By applying a common mode signal to its input and activating the test function the circuit is modified to enable symmetrical branch currents to be monitored and their correlation can be used to indicate correct circuit topology. This simplifies the testing of integrated circuits, which with their increasing complexity are becoming more expensive to test to ensure their functionality.
- Figure 1 shows a differential amplifier to which the method of testing according to the invention may be applied
- Figure 2 shows an on chip monitor for monitoring branch current
- Figure 3 shows symmetrical branch currents measured in a fault free circuit
- Figure 4 shows symmetrical branch currents measured in a faulty circuit
- Figure 5 shows the output signals VTI and VT2 from the branch current monitor.
- Figure 1 is a schematic circuit diagram of a differential amplifier having inputs 1 and 2 to which input signals Vips and Ving are applied. The inputs 1 and 2 are fed to a differential pair of transistors T1 and T2 whose tail current is defined by transistors T3 and T4 and bias voltages V i and V b2 .
- Two chains of transistors T5, T6, T7, T8 and T9, T10, T1 1 , T12 are connected between the supply rails Vd d and V ss , the transistors of each chain being fed with bias voltages V ⁇ , V b2 , V b3 and V b , respectively.
- the drain contacts of transistors T1 and T2 are connected to the drain contacts of transistors T8 and T12 respectively.
- a further differential pair of transistors T20 and T21 have a tail current defined by transistors T13 and T14 and bias voltages V b1 and V 2 and have a bias voltage V ba ⁇ applied to their gate contacts.
- the outputs of the further differential pair are fed to the junctions of transistors T6 and T7 and transistors
- a differential output stage comprising the series arrangement of transistors T30 and T31 from the junction of which a first output signal V ong is derived and fed to an output 3 and the series arrangement of transistors T32 and T33 from the junction of which a second output signal V 0Ps is derived and fed to an output 4.
- the differential input signal is formed by V,p S and V ⁇ ng and that the differential output signal is formed by V ops and V ong .
- the junction of transistors 11 and T8 is connected via a capacitor C1 to the junction of transistors T30 and T31 , while the junction of transistors T11 and T12 is connected via a capacitor C2 to the junction of transistors T32 and T33.
- the series arrangement of transistor T15 and a diode connected transistor T16 is connected between the tail of the further differential pair and the supply rail V ss .
- a control signal V m , d which is a feedback signal derived from the output of the amplifier is connected to the gate contact of transistor T15.
- the amplifier shown in Figure 1 is an example of a fully differential circuit in which the method of the present invention may be formed and into which a monitoring circuit according to the invention may be inserted. The particular form and operation of the amplifier is not part of the current invention and consequently will not be further described herein except in that the responses shown in Figures 3 to 5 derive from this particular circuit.
- Figure 2 is a schematic circuit diagram of a monitor for determining whether currents in the two symmetrical branches of a differential circuit are equal and shows how such a monitor may be implemented in the amplifier of Figure 1.
- the transistors T20 and T21 of Figure 1 have switches S1 and S2 inserted between their gate contacts and the bias source V ba ⁇ . They have further switches S3 and S4 inserted between their gate and drain contacts.
- switches S1 and S2 are closed and switches S3 and S4 are open and during the test process the switches S1 and S2 are open and switches S3 and S4 are closed.
- the operation of these switches is controlled by means of a signal applied to the circuit when the test process is invoked.
- inputs 1 and 2 are excited by a common mode signal, which means that if the circuit is operating correctly the currents in the symmetrical branches will be equal.
- the currents through transistors T20 and T21 which are now configured as non-linear resistors, will be equal, within normal circuit tolerances.
- the drain currents through transistors T20 and T21 are mirrored by transistors T213 and T214 and subtracted using the current mirror formed by transistors T215 and T216 to produce a resulting output voltage VRL which is applied to the gate contacts of a pair of transistors T219 and T221 connected across the supply rails V dd and V ss to form a first amplifier and to the gate contactss of a further pair of transistors T222 and T223 which are also connected across the supply rails V dd and V ss to form a second amplifier.
- the outputs of the first and second amplifiers are fed to respective inputs of an EXORgate 9 the state of whose output 10 will give an indication of whether the circuit is faulty.
- the voltage at the junction of transistors T214 and T215, that is VRL will be equal to half the supply voltage and the first amplifier formed by transistors T219 and T221 is designed to produce a logic 1 output when VRL has that value.
- the second amplifier formed by transistors T222 and T223 is designed to produce a logic 0 output when VRL has that value.
- the switching thresholds of the first and second amplifiers can be set by appropriate dimensioning of transistors T219, T221 , T222, and T223 and provided that VRL lies between these threshold values (which may be regarded as the given value) then the output of the first amplifier will be a logic 1 and that of the second amplifier a logic 0.
- the operation may be summarised as on-chip monitor consisting of the following functional steps:
- step 2 To amplify the resulting signal from step 2 to generate a logic 1 whenever it is equal or lower than the mid point of the supply voltages, and a logic 0 if higher than the mid point of the supply voltages. (In the amplifier comprising transistors T219 and T221);
- step 2 To amplify the resulting signal from step 2 to generate a logic 0 whenever it is equal or higher than the mid point of the supply voltages, and a logic 1 if lower than the mid point of the supply voltages. (In the amplifier comprising transistors T222 and T223); and
- the voltage VRL will be at an intermediate value (nominally half the supply voltage) when the two currents are correlated and will tend to one of the supply rails when mis-correlation occurs depending on the sign of the mis-correlation monitored.
- a number of simulations have been carried out to investigate the effect upon those branch currents of different defects that may occur in a microelectronic implementation of the circuit shown in Figure 1. Results show that a mis-correlation may occur either in the quiescent level and/or in the transient behaviour of the branch currents.
- Figure 3 shows simulation results for a fault free circuit.
- Figure 4 shows the simulation result for a fault that produce a mis-correlation in the transient spikes of the branch currents.
- Figure 5 shows the branch current monitor output signals VT1 and VT2, from the first and second amplifiers that are EXORed to generate the digital test signature. That is the signals VT1 and VT2 are the signals applied to the inputs of the EXOR gate 9. These signals correspond to the same fault simulated to generate the currents shown in Figure 4. From Figure 4 and Figure 5 it can be observed how the difference in the first transient spike is big enough to excite an error output code from the branch current monitor. However, the difference in the second transient spike, although it exists, is not large enough to produce a clear digital output level in VT1.
- the branch current monitor shown in Figure 2 is tolerant to normal process variations, i.e. test intermediate outputs VT1 and VT2 allow for a variation margin in VRL larger than ⁇ 140 mV before giving an error output code. That is the given value has a band of values of ⁇ 140mV about the given value, which in this case is the supply voltage/2. The variation of this signal due to normal process fluctuation in this particular circuit has been measured to be up to ⁇ 70 mV.
- a method of designing fully differential electrical circuits comprising the steps of: i) designing a fully differential circuit to perform a desired function, such as the amplifier shown in Figure 1 ; ii) selecting one or more parts of the circuit that pass symmetrical currents when a common mode signal is applied to the input of the circuit when the circuit is fault free, that is in this particular case the transistors T20 and T21 ; iii) providing switching means for causing said one or more parts to adopt a first configuration to enable the branch currents to be monitored for test purposes and a second configuration for normal circuit operation, that is the switches S1 to S4; and iv) providing monitoring means for monitoring the branch currents when said one or more parts adopt the first configuration, that is the current mirroring and subtraction arrangement T213 to T216, the first amplifier T219 and T221 , the second amplifier T222 and T223, and the EXOR gate 9.
- the design methodology uses the property of fully differential circuits that when excited by common mode signals equal currents flow in symmetrical branches and selects nodes where these currents can be monitored.
- a monitoring circuit is built in which can monitor these symmetrical currents under test conditions and indicate whether correlation exists under both quiescent and transient conditions.
- a fully differential electrical circuit may comprise a monitoring circuit for monitoring the currents in symmetrical branches of the circuit when excited by a common mode input signal, that is transistors T213 to T216.
- Switching means that is switches S1 to S4 are provided for modifying a part of the circuit, that is transistors T20 and T21 , for test purposes to enable the current monitoring to take place and to restore said part of the circuit to its normal circuit function at other times.
- Test means are provided for determining whether the currents in the symmetrical branches are substantially equal under test conditions, that is amplifiers T219 and T221 and T222 and T223 and EXOR gate 9.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001542224A JP2003515746A (en) | 1999-11-27 | 2000-11-10 | How to test an electrical circuit |
KR1020017009399A KR20010101713A (en) | 1999-11-27 | 2000-11-10 | Testing electrical circuits |
EP00985036A EP1149296A1 (en) | 1999-11-27 | 2000-11-10 | Testing electrical circuits |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB9927996.0A GB9927996D0 (en) | 1999-11-27 | 1999-11-27 | Method of and apparatus for testing analogue circuits |
GB9927996.0 | 1999-11-27 | ||
GB9930853.8 | 1999-12-24 | ||
GBGB9930853.8A GB9930853D0 (en) | 1999-12-24 | 1999-12-24 | Testing electrical circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001040815A1 true WO2001040815A1 (en) | 2001-06-07 |
Family
ID=26316094
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2000/011294 WO2001040815A1 (en) | 1999-11-27 | 2000-11-10 | Testing electrical circuits |
Country Status (5)
Country | Link |
---|---|
US (1) | US6469520B1 (en) |
EP (1) | EP1149296A1 (en) |
JP (1) | JP2003515746A (en) |
KR (1) | KR20010101713A (en) |
WO (1) | WO2001040815A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6675344B1 (en) * | 2000-05-01 | 2004-01-06 | Hewlett-Packard Development Company, L.P. | Multiple ECC schemes to improve bandwidth |
US8742778B2 (en) | 2012-01-18 | 2014-06-03 | International Business Machines Corporation | Testing protection schemes of a power converter |
GB201801995D0 (en) | 2018-02-07 | 2018-03-28 | Analog Devices Global Unlimited Co | A method of and apparatus for detecting open circuit conditions at an input to a signal chain and for detecting channel imbalance in a differential signal |
EP3524988B1 (en) * | 2018-02-07 | 2022-03-30 | Analog Devices International Unlimited Company | A method of and apparatus for detecting channel imbalance in a differential signal system comprising a differential amplifier |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5495173A (en) * | 1994-07-05 | 1996-02-27 | Motorola, Inc. | Method and apparatus for characterizing a differential circuit |
GB2314712A (en) * | 1996-01-23 | 1998-01-07 | Advantest Corp | Comparator for semiconductor testing device |
EP0987554A1 (en) * | 1998-09-15 | 2000-03-22 | Vibro-Meter Sa | Measuring circuit |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4553098A (en) * | 1978-04-05 | 1985-11-12 | Hitachi, Ltd. | Battery checker |
US4263549A (en) * | 1979-10-12 | 1981-04-21 | Corcom, Inc. | Apparatus for determining differential mode and common mode noise |
US4837502A (en) * | 1983-11-04 | 1989-06-06 | Grumman Aerospace Corporation | Computer-aided, logic pulsing probe for locating faulty circuits on a printed circuit card |
US4996488A (en) * | 1987-10-01 | 1991-02-26 | Nave Mark J | Measuring and limiting EMI with a selectable mode reflection network |
FR2661291A1 (en) * | 1990-04-19 | 1991-10-25 | Philips Composants | DIFFERENTIAL FOLLOWING CIRCUIT. |
US5087884A (en) * | 1990-06-28 | 1992-02-11 | Vtc Bipolar Corporation | Open head detection circuit and method |
US5561378A (en) * | 1994-07-05 | 1996-10-01 | Motorola, Inc. | Circuit probe for measuring a differential circuit |
-
2000
- 2000-11-10 JP JP2001542224A patent/JP2003515746A/en active Pending
- 2000-11-10 KR KR1020017009399A patent/KR20010101713A/en not_active Application Discontinuation
- 2000-11-10 WO PCT/EP2000/011294 patent/WO2001040815A1/en not_active Application Discontinuation
- 2000-11-10 EP EP00985036A patent/EP1149296A1/en not_active Withdrawn
- 2000-11-27 US US09/722,813 patent/US6469520B1/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5495173A (en) * | 1994-07-05 | 1996-02-27 | Motorola, Inc. | Method and apparatus for characterizing a differential circuit |
GB2314712A (en) * | 1996-01-23 | 1998-01-07 | Advantest Corp | Comparator for semiconductor testing device |
EP0987554A1 (en) * | 1998-09-15 | 2000-03-22 | Vibro-Meter Sa | Measuring circuit |
Non-Patent Citations (1)
Title |
---|
HERETH K: "OPERATIONSVERSTARKER IM BENCHTOP-TEST", ELEKTRONIK,DE,FRANZIS VERLAG GMBH. MUNCHEN, vol. 38, no. 6, 17 March 1989 (1989-03-17), pages 50 - 55, XP000111318, ISSN: 0013-5658 * |
Also Published As
Publication number | Publication date |
---|---|
EP1149296A1 (en) | 2001-10-31 |
KR20010101713A (en) | 2001-11-14 |
JP2003515746A (en) | 2003-05-07 |
US6469520B1 (en) | 2002-10-22 |
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