WO2001044012A2

WO2001044012A2 - Data exchange on a data bus

Info

Publication number: WO2001044012A2
Application number: PCT/DE2000/004462
Authority: WO
Inventors: Stefan Goss; Markus Kucera; Roman Nossal
Original assignee: Siemens Aktiengesellschaft
Priority date: 1999-12-16
Filing date: 2000-12-14
Publication date: 2001-06-21
Also published as: DE19960800A1; WO2001044012A3; EP1238495A2

Abstract

The invention relates to a method for exchanging data on a data bus. According to the inventive method, data is transmitted on a bus line (1; 2) by changing between defined levels for a dominant state and a recessive state. The bus line is split into at least two branches (11; 21) when the level for the dominant state exceeds a predetermined time interval. The data exchange can be continued on the branch of the data bus that is not subject to the default.

Description

description

Data exchange on a data bus

The invention relates to a method for data exchange on a data bus and a data bus with at least one bus line with defined levels for a dominant and a recessive state, in particular for motor vehicle technology.

Data buses are becoming increasingly popular in automotive technology. In the event of a short circuit in a bus line or in contact with another potential (external short circuit), there can be a total loss of communication. A defective bus subscriber can also bring the data exchange to a standstill if he permanently sets the bus line to a certain potential. This is particularly problematic for safety-related applications in a motor vehicle.

From the published patent application DE 195 15 194 AI, a communication network for a vehicle is known in which an erroneous operation of control devices is to be prevented. For this purpose, a large number of control devices are connected to bus bars. The bus bars can be connected to one another and separated from one another via a switching device, so that the control devices can be separated into groups that use different communication methods. However, there is no protection against a defect in a bus line.

The patent specification EP 0 412 085 B1 relates to a network interface in which an interruption or short circuit on the bus line connected to the network interface can be detected even when the network work interface is in an inactivated operating mode ("sleep ode"). It is an object of the invention to provide a method for data exchange on a data bus and a data bus which allow at least partial maintenance of the data exchange, even if a fault has occurred on a bus line.

This goal is achieved with a method and a data bus as defined in the independent patent claims. Advantageous developments of the invention are specified in the subclaims.

By separating the bus line in at least two bus branches, at least one data exchange can take place in the event of a fault on a bus line in which the bus level is incorrectly present (stuck at dominant state or stuck at recessive state) or in which the undefined level is present to be continued on a bus branch. Such a fault can occur, for example, in the event of a local short circuit to ground or an external short circuit to a power supply.

In a particularly preferred embodiment, the bus branches are reconnected when the error disappears or when the data bus is reset when it is switched on again. Alternatively, the bus branches can only be connected when the device is switched on again.

The data exchange on the data bus is preferably carried out using pulse-code-modulated data m NRZ (no return to zero) and bit stuffing to interrupt long high or low bit sequences.

Furthermore, the bit stream can be encoded by means of a self-synchronizing coding. Preferred areas of application of the invention are safety-relevant applications in motor vehicles, such as, for example, a data bus for an electromechanical brake or steering,

An bus branch advantageously connects two actuators of an electromechanical brake. This means that two wheels can be braked by a bus branch that has remained intact, similar to a conventional hydraulic dual-circuit system. The actuators connected by the bus branch are preferably arranged diagonally on different vehicle axles.

Further features, advantages and possible applications of the invention result from the following description of an exemplary embodiment in conjunction with the drawing.

The figure shows a data bus with an isolating circuit.

The data bus shown has two bus lines 1 and 2 for connecting bus subscribers or computing units (not shown). The computing units are connected in parallel to the data bus. The computing units are control systems and controllers connected to them, which issue received control commands to electric motors that actuate wheel brakes.

Data is transmitted on the bus lines by switching between defined levels for a dominant state and for a recessive state. The dominant state is the higher priority state. In the present case, a voltage of 3.5 V is applied to one bus line and a voltage of 1.5 V to the other bus line in the dominant state. In the recessive state, both bus lines are supplied with 2.5V. This corresponds to the "unoccupied" state. If the dominant state and the recessive state occur simultaneously, the dominant state consequently "overwrites" the recessive state. The connected computing units cause a change between the dominant state and the recessive state for data transmission. The dominant state can be a certain voltage or current level to which the logic state high or low is assigned. The level is formed from the difference between the levels on the two bus lines 1 and 2.

The bus lines 1, 2 are monitored by an isolating circuit 3.

The isolating circuit 3 comprises a monitoring logic 31 for recognizing a dominant state which persists in an erroneous manner, which is referred to below as SADS (stuck at dominant state). An SADS error occurs when a defective bus subscriber or an electrical contact between the power supply line and a bus line (external fault) causes the dominant state to be present for longer than a defined time interval. The time interval is determined depending on the coding.

The monitoring logic 31 contains a receiver or a transceiver 311 and a status monitoring 312. The status monitoring 312 permanently monitors the logic level which is transmitted from the transceiver 311 to the status monitoring 312 on a receiving line.

An SADS error is detected by the status monitor 312, which monitors the receive line. If the bit representation on the reception line, which corresponds to the dominant state, is present longer than a predetermined time interval, then a SADS error is recognized.

Furthermore, the isolating circuit 3 has a measuring unit 32 for recognizing a recessive state which is erroneously persistent, which is referred to below as SARS (stuck at recessive state). An SARS error occurs when as a result of an external short circuit or a short circuit, the dominant state can no longer be set. This error is recognized by the measuring unit 32 through a resistance measurement. The resistance between the two bus lines 1 and 2 is specified by the terminating resistors. The resistance measurement must not impair communication on the bus lines. This is ensured by a known diode resistance circuit, not shown in the figure. This enables a resistance measurement to be carried out at any time.

A switch control 33 separates the data bus into two bus branches 11 and 21 via isolating switches 34 and 35 if the monitoring logic has detected an SADS error or the measuring unit 32 has detected a SARS error. When the bus lines 1, 2 are disconnected, the isolating switches 34 and 35 are each switched to a terminating resistor 36 or 37. As a result, in each of the two bus branches, the two bus lines 1 and 2 are connected to one another via the terminating resistors and consequently terminated correctly. Since a single error can affect only one of the bus branches 11 or 21, it is possible to maintain data exchange on the other bus branch. This is particularly useful if a control unit that controls actuators connected to the bus lines is either designed redundantly for each bus branch or has separate connections to the bus branches.

After the data bus has been disconnected, monitoring by the monitoring logic 31 and the measuring unit 32 is continued. If it is determined that there is no longer a SADS or SARS error or that there is no impermissible potential on the bus lines, then the bus branches 11 and 21 are interconnected again.

In addition, the bus branches 11 and 21 are interconnected when the system is reset as a result of the system being switched off and on again (power-on reset).

Claims

claims

1. A method for data exchange on a data bus, wherein

Data are transmitted on a bus line (1; 2) by switching between defined levels for a dominant state and a recessive state,

- the bus line m is separated at least two branches (11; 21) if the level for the dominant state on the bus line (1; 2) is present longer than a predetermined time interval,

- The data exchange of at least one of the branches (11; 21) is continued.

2. The method according to claim 1, characterized in that the bus line (1; 2) m at least two branches (11; 21) is separated if there is a short circuit or external fault on the bus line.

3. The method according to any one of the preceding claims, characterized in that when the bus lines (1; 2) are separated, each branch (11; 21) is provided with a terminating resistor (35; 36).

4. The method according to any one of the preceding claims, characterized in that the bit stream is encoded by NRZ and bit stuffing.

5. The method according to any one of the preceding claims, characterized in that the bit stream is encoded by means of a self-synchronizing coding.

6. The method according to any one of the preceding claims, characterized in that the separate bus branches (11; 21) are reconnected when the power supply of the data bus is switched on again.

7. The method according to any one of the preceding claims, characterized in that the levels of the separate bus branches (11; 21) are monitored, and that the bus branches are reconnected when the defined levels are reached again.

8. Data bus for connecting computing units, which has:

- at least one bus line (1; 2) with defined levels for a dominant state and for a recessive state,

- A separating circuit (3) which separates the bus line (1; 2) into two branches (11; 21) which continue to operate autonomously if the level for the dominant state of the bus line (1; 2) is present longer than a predetermined time interval.

9. Data bus according to the preceding claim, characterized in that a measuring unit (32) is provided for the detection of a short circuit or an external short circuit.

10. Data bus according to one of the preceding claims directed to a data bus, characterized in that em bus branch (11; 21) connects two actuators emer electromechanical brake, which are arranged diagonally on different vehicle axes.