WO2001045164A1

WO2001045164A1 - Method for interconnecting integrated circuits

Info

Publication number: WO2001045164A1
Application number: PCT/FR2000/003508
Authority: WO
Inventors: Françis STEFFEN
Original assignee: Stmicroelectronics
Priority date: 1999-12-14
Filing date: 2000-12-13
Publication date: 2001-06-21
Also published as: FR2802337A1

Abstract

The invention relates to a method for interconnecting at least two integrated circuit boards, wherein one printed circuit board has contacts (65, 66) on a rear surface and conductive feed-throughs (60) electronically linking the contacts (65,66) on the rear surface to a region of the integrated circuit (51) on the front surface, the rear surface contacts being welded or glued to the front surface contacts (64) of another silicon wafer. The invention also relates to a method for the production of said conductive feed-throughs, comprising the following steps: troughs (50) having a given depth are made on the front surface of a silicon wafer; an electrically insulating material (61) is deposited on the walls of said troughs; at least one electrically conductive material (62,63) is deposited on the insulated walls of the troughs, and the silicon circuit wafer (50) is thinned down by chemical and/or mechanical abrasion of the rear surface thereof until the conductive material (62,63) deposited in the troughs is reached.

Description

METHOD FOR INTERCONNECTING INTEGRATED CIRCUITS

The present invention relates to techniques for interconnecting integrated circuits, and more particularly to techniques for direct interconnection by stacking integrated circuit wafers.

Since the appearance of integrated circuits on silicon wafers, the methods of interconnecting integrated circuits have been the subject of much research and development. Recall that an integrated circuit is in the form of a small silicon wafer (or silicon chip) which has on its front face an integrated circuit region and contact pads electrically connected to the integrated circuit region . In many embodiments, the integrated circuit wafers are enclosed in boxes provided with metal pins and their interconnection is ensured by printed circuit boards having metallized areas on which the pins of the boxes are welded.

The disadvantage of this interconnection technique is that it leads to bulky electronic systems despite the various advances made in the field of printed circuits. We have thus developed, in parallel, direct mounting techniques of integrated circuits on an interconnection support, for applications where a high level of integration is necessary.

FIG. 2 schematically represents a first conventional technique for transferring an integrated circuit board 1 onto an interconnection support 10, known as a "flip" chip "(" chip upside down "). The plate 1 is mounted" upside down "on the support 10, its active face 2 being oriented downwards. The contact pads 3 of the plate are directly fixed on metallized areas 11 of the interconnection support 10 by means of a fusible alloy such as tin-lead or an electrically conductive adhesive, forming protuberances

("bumps") on the surface of the contact pads 3. The interconnection support 10 can be a printed circuit board or a support of smaller dimensions such as a thick film hybrid circuit ("thic film") or a layered circuit thin ("thin film") on ceramic substrate (A1 ₂ 0 ₃ ).

FIG. 2 schematically represents a second conventional technique for mounting an integrated circuit board 20 on an interconnection support 10, called "chip and ire" ("chip and wire"). The silicon wafer 20 is mounted this time "at the place" and its contact pads 21 are connected to metallized pads 11 of the interconnection support 10 by ultrasonic wiring ("ultrasonic wire bonding"), that is to say - say by means of metal wires 22 welded with ultrasound.

However, as an integrated circuit wafer has a large surface area with regard to its thickness, the search for even more integration has led those skilled in the art to consider the concept of "stacking integrated circuits".

By way of example, FIG. 3 represents a stack of two integrated circuit boards 20, 30 having their active faces oriented upwards. The contact pads 21, 31 of each plate 20, 30 are, as in the previous assembly, connected to metallized pads 11 of the interconnection support 10 by metal wires 22. This technique quickly finds its limits beyond two, or even three stacked integrated circuits, due to the "staircase" profile that the assembly must present. Indeed, the plate 30 must be of a surface smaller than that of the plate 20, so as not to mask the contacts 21 of the latter. In addition, the fact that the contacts 31 of the upper plate are located at a greater distance from the pads 11 of the interconnection support 10 makes the wiring operations more delicate. The son loops 22 are longer and more fragile and many difficulties arise in the context of industrial production.

FIG. 4 represents a recent technique for stacking several integrated circuits, which has the advantage of being reproducible on an industrial scale without crippling problems of reliability. Each integrated circuit board 40 is arranged in a micro-housing 45 constituted by a polyimide frame 46 filled with resin 47. The electrical connection of the integrated circuit boards 40 is ensured by flat conductors 48

("leads") extending outside the micropacks

45 to form metal legs 49 of small dimensions. The tabs 49 of the same rank of the micro-housings 45 are welded together, at their ends, to the metallized areas 11 of an interconnection support 10.

In practice, the total thickness of the stack of four integrated circuits shown in FIG. 4 does not exceed 0.5 millimeters, the plates 40 being of a thickness of the order of 30 to 50 micrometers and the micro-housings 45 with a thickness of the order of 100 micrometers. It should be noted that such a stacking technique has only become possible due to recent progress made in the field of techniques for thinning silicon wafers. Lcium sil wafers indeed have an initial thickness of several hundred micrometers when the integrated circuits are installed there (at this stage, they are called "wafers") and are then thinned from their back side by so-called "backlappmg" processes combining chemical etching and mechanical abrasion , before being cut into individual integrated circuit boards. At present, we manage to thin silicon wafers up to 30 to 50 micrometers and there is no doubt that this thickness will be further reduced in the future.

Despite the high degree of integration offered by the stack which has just been described, the polyimide micro-housings 45 prove to be of a non-negligible cost price and their manufacture requires considerable know-how and industrial tools.

The objective of the present invention is to provide an alternative solution for stacking silicon wafers, which has the advantage of being simple and which can be implemented by means of conventional techniques for transferring chips onto a support. interconnection, in particular the "flip chip" technique mentioned above.

More particularly, an objective of the present invention is to provide a means for interconnecting integrated stacked circuits.

To achieve this objective, the present invention is based on a simple but no less inventive idea in its application to integrated circuit boards, which is to provide integrated circuit boards comprising contacts on the rear face electrically connected by conductive bushings to the regions of integrated circuits on the front panel. Such conductive bushings make it possible to directly connect the rear face of a silicon wafer on the front face of another wafer or connector; the rear face of a silicon wafer with metallized areas of an interconnection support.

However, making crossings in a silicon wafer with a thickness of several hundred micrometers is an unacceptable technical operation.

Thus, the present invention firstly provides a method of manufacturing conductive bushings in a silicon wafer, comprising the steps of producing cuvettes of a determined depth on the front face of the silicon wafer; depositing on the walls of the bowls an electrically insulating material; deposit at least one electrically conductive material on the insulated walls of the cuvettes, and thin the silicon wafer, by chemical and / or mechanical abrasion of its rear face, until reaching the conductive material deposited in the cuvettes.

According to one embodiment, the step of depositing on the walls of the cuvettes a conductive material comprises a step of filling the cuvettes with at least one conductive material.

According to one embodiment, the cuvettes are produced before the implantation of an integrated circuit region on the silicon wafer.

According to one embodiment, the cuvettes are produced after the implantation of an integrated circuit region on the silicon wafer. According to one embodiment, there is provided a step consisting in depositing on the rear face of the wafer at least one layer of an electrically insulating material, and a step consisting in producing on the rear face contact pads connected to the conductive bushings .

According to one embodiment, a step of cutting the silicon wafer is provided, passing through the middle of the conductive bushings to obtain at least one silicon wafer comprising conductive bushings sectioned along their longitudinal axis, along the sides of the wafer. .

The present invention also provides a method for interconnecting at least two integrated circuit boards, comprising the steps consisting in providing an integrated circuit board comprising rear panel contacts electrically connected to an integrated circuit region on the front panel through conductive bushings passing through. the wafer right through, and soldering or bonding the contacts on the rear face of the wafer to contacts on the front face of another silicon wafer.

According to one embodiment, the conductive bushings include practical orifices in the silicon wafer, an electrically insulating layer covering the walls of the orifice, and at least one electrically conductive material covering the insulated walls of the orifice or completely filling the 'orifice.

According to one embodiment, the conductive crossings are sectioned along their longitudinal axis and run along the sides of the plates. The present invention also relates to a silicon wafer comprising an integrated circuit region located on its front face, conductive bushings connected to the integrated circuit region, passing right through the wafer and emerging on its rear face.

According to one embodiment, a conductive bushing comprises an orifice passing through the silicon wafer, an electrically insulating layer covering the walls of the orifice, and at least one electrically conductive material covering the insulated walls of the orifice or completely filling the orifice.

According to one embodiment, the wafer comprises on its rear face contacts electrically isolated from the wafer and electrically connected to conductive bushings.

According to one embodiment, the wafer further comprises conductive bushings which are not connected to the integrated circuit region.

According to one embodiment, the plate comprises conductive cross-sections sectioned along their longitudinal axis, along the sides of the plate.

The present invention also provides an assembly of silicon wafers comprising at least one stack of two silicon wafers, each wafer comprising an integrated circuit region on the front face and contacts welded or bonded to contacts of the other wafer, in which at least one plate includes contacts on the rear face and conductive bushings passing through the plate; right through, electrically connecting the contacts on the rear face to the integrated circuit region. According to one embodiment, the contacts on the rear face of a wafer are welded or glued to contacts on the front face of the other silicon wafer.

According to one embodiment, conductive bushings comprise orifices made in the silicon wafer, an electrically insulating layer covering the walls of the orifice, and at least one electrically conductive material covering the walls insulated from the orifice or completely filling the 'orifice.

According to one embodiment, at least one silicon wafer has at least one conductive bushing which is not connected to its integrated circuit region.

According to one embodiment, at least one plate comprises conductive cross-sections sectioned along their longitudinal axis, along the sides of the plate.

These objects, characteristics as well as others of the present invention will be explained in more detail in the following description of a process for manufacturing conductive bushings according to the invention and of various variants of this process, as well as examples of integrated circuit assemblies according to the invention, in relation to the attached figures among which: - Figures 1 to 4 previously described illustrate conventional methods of interconnecting integrated circuits, Figures 5A to 5E are sectional views of a silicon wafer illustrating a method of manufacturing conductive bushings according to the invention, - FIGS. 6A to 6D illustrate an alternative embodiment of certain steps of the method of FIGS. 5A to 5E, FIGS. 7 to 8A, 9 to 13 are sectional views of silicon wafers representing various alternative embodiments of conductive bushings according to the invention,

FIG. 8B represents the rear face of a silicon wafer seen in section in FIG. 8A,

FIGS. 14, 15 are diagrammatic section views of assemblies of integrated circuits according to the invention,

- Figures 16A and 16B show a perspective view and a top view of an integrated circuit board comprising conductive bushings according to the invention arranged on the edges of the board, Figure 17 is the electrical diagram of an electronic circuit comprising integrated circuits to be interconnected, - Figures 18A to 18D illustrate a method of interconnection according to the invention of the integrated circuits of Figure 17, and Figures 19A to 19D illustrate a method of manufacturing cuvettes in a silicon wafer by anisotropic etching.

FIGS. 5A to 5E are views in partial section of a silicon wafer and illustrate a method of manufacturing conductive bushings according to the invention.

In the step shown in FIG. 5A, one begins by making cuvettes 60 of a determined depth in a virgin monocrystalline silicon wafer 50, commonly called a "wafer" and intended to receive integrated circuits. The wafer 50 has a standard thickness of several hundred micrometers, for example 700 micrometers for a wafer with a diameter of 6 inches (15.24 cm). The bowls 60 are made to a depth of the order of 30 to 150 micrometers depending on the final thickness of the wafer 50 aimed at the end of a thinning step described below. The bowls 60 are formed by isotropic or anisotropic etching of the silicon or by any other known method enabling blind holes to be produced on the surface of a silicon wafer, in particular the plasma or laser etching methods. It should be noted that in Figures 5A to 5E and Figures 7 to 13 described below, the cuvettes are shown with inclined walls due to an anisotropic etching of the silicon. However, these bowls could also have straight walls or walls of irregular shape depending on the engraving technique chosen. An anisotropic etching process using a potassium hydroxide solution will be described by way of example in the last pages of this application.

As illustrated in FIG. 5B, various regions of integrated circuits 51 are then produced collectively on the front face of the wafer 50, by implantation / diffusion of dopants, deposition and etching of layers of oxide, of polycπstallin silicon ... (a only region 51 being partially shown in the figure). The regions of integrated circuits 51 include various electronic or electrical components, such as transistors, resistors, capacitors, conductive tracks, etc. The steps for implanting regions 51 are in themselves conventional and will not be described here for the sake of of simplicity. The presence of the bowls 60 does not imply any appreciable modification of the etching and diffusion masks.

During the manufacture of the regions 51, an electrically insulating layer 61 is deposited on the surface of the wafer 50 which extends from the integrated circuits 51 to the interior of the bowls 60 and isolates the walls of the latter. The material 51 is conventionally silicon oxide Sι0 ₂ or any other known oxide or insulator, for example silicon oxynitride SiON. Also, a layer of conductive material is deposited and etched 62 such as aluminum or copper, which extends from the regions of integrated circuits 51 to the cuvettes 60 and covers the insulated walls of the latter. In the parts extending between the integrated circuits 51 and the cuvettes 60, the conductive layer 62 is etched to form conductive tracks or conductive sections electrically connecting the cuvettes 60 to inputs / outputs of the regions of integrated circuits 51. Thus, the wafer 50 shown in FIG. 5B is similar to a conventional wafer, with the difference that the contacts conventionally made on the periphery of the integrated circuit regions 51 here take the form of conductive cuvettes 60.

At the end of the process, the surface of the wafer 50 is covered by a passivation layer 52 like a hardened glass paste or a polyimide, which has openings made by dry or wet etching opposite the bowls 60.

In the step shown in FIG. 5C, the cuvettes 60 are filled with an assembly material 64 forming protuberances ("bumps"), for example a tin-lead alloy SnPb, a conductive adhesive charged with silver, a ACF conductive paste ("Anisotropic Conductive Paste"), an ACF conductive film ("Anisotropic Conductive Film") ... these materials being known to those skilled in the art and used in the "flip chip" technique mentioned in the preamble. The assembly material 64 is deposited directly in the cuvettes 60 or, as shown in FIG. 5C, via a junction material 63 compatible with the conductive layer 62. The junction material 63 is for example nickel , Zincate (Nickel-Zinc), a Tungsten-Titanium alloy ... deposited by projection ("sputtering") or formed by electrochemical growth. In general, material compatibility issues are known to those skilled in the art and have been resolved in the prior art. For example, the joining material 63 is useless if the layer 62 is made of copper (copper can support any type of joining material) and is on the contrary necessary if the layer 62 is made of aluminum and the joining material used is tin-lead.

In the step of FIG. 5D, the wafer 50 is inverted on a flexible strip 59 ("backlap tape"), preferably a strip of the "UV" type whose adhesion on the front face of the wafer 50 can be degraded to appropriate time by exposure to ultraviolet light. The rear face of the wafer 50 is then attacked by chemical and mechanical abrasion ("backlapping") until the silicon at the bottom of the bowls 60 is removed and the junction material 63 or the assembly material 64 is reached. (in the absence of joint material 63). The bowls 60 thus become conductive crossings according to the invention, which will be designated by the same reference 60, opening onto the rear face of the thinned wafer 50. The thickness of the thinned wafer 50 is of the order of 30 to 150 micrometers according to the initial depth of the bowls 60.

At this stage of the process according to the invention, the wafer 50 is an unfinished product from the industrial point of view but nevertheless constitutes a finished object according to one aspect of the invention. Indeed, thanks to the crossings 60, the wafer 50 offers a plurality of contacts on the rear face which allow, if desired, to electrically test the regions of integrated circuits 51 by means of a spike card without it being necessary. to remove the wafer from the support strip 59. Thus, the conductive bushings 60 according to the invention may only be produced for the purpose of the electrical test of the wafer 50 by its rear face. This possibility is advantageous when the wafer 50 is too fragile to be handled and placed on a classic test tray. Another advantage is that the crossings 60 form areas for relaxation of the mechanical stresses exerted on the wafer 50. It is indeed well known that the mechanical stresses appearing after the formation of regions of integrated circuits 51 weaken the wafers and make perilous their thinning beyond a certain thickness. By making the crossings 60, the resistance of the wafer 50 is significantly improved and its thinning is facilitated beyond the limits generally accepted in the state of the art.

The rear face of the wafer 50 can then be entirely covered with an insulating layer in order to bury the contacts on the rear face, if these were only made for the purpose of the electrical test of the regions of integrated circuits 51, such as we proposed it above.

The primary objective of the present invention however being to allow the assembly of integrated circuit wafers, the method of the invention will generally be continued, as illustrated in FIG. 5E, by a deposition step on the rear face of the wafer 50 an insulating layer 53 having openings 54 at the places where the conductive crossings open 60. The insulating layer 53 is for example a non-thermal hard oxide deposited according to LPCVD (Low Pressure Chemical Vapor Deposition) technology at low pressure and at low temperature, such as silicon oxynitride SiON, or a material of the "BCB Photoimaginable" type, or a polyimide deposited in one or more layers. The openings 54 are produced by chemical or mechanical etching (plasma, laser) depending on the material forming the layer 53. An assembly material 65 is then deposited in the openings 54 forming protuberances on the rear face, which may be identical to the material d 'assembly 64 forming the protrusions on the front face. At the end of the process which has just been described, there is a silicon wafer comprising regions of integrated circuits 51 and protrusions 64, 65 ("bumps") on the front face and on the rear face electrically connected to the regions 51. As will be described in more detail below, the protrusions 64, 65 make it possible to produce stacks of integrated circuits 51 in a simpler manner than in the prior art, by assembly steps carried out at the "wafer level"("waferlevel") or at "chip level".

We will first describe various variants of the invention relating to the method of manufacturing the conductive bushings, the structure of the bushings and the structure of the contacts on the front and rear faces.

According to an alternative embodiment of the method of the invention illustrated in FIG. 6A, one begins by manufacturing on the front face of the wafer 50 regions of integrated circuits 51 provided with conventional contacts 55 ("pads"), accessible through openings practiced in the passivation layer 52 (glass or polyimide) and comprising as previously a conductive layer 62 (aluminum or copper) resting on an insulating layer 61 (oxide).

In the step shown in FIG. 6B, cuvettes 70 are produced in the middle of the contacts 55, by plasma etching or laser etching, or even by chemical etching after having deposited an etching mask on the surface of the wafer 50.

In the step shown in FIG. 6C, an insulating layer 71 is deposited on the walls of the cuvettes 70 without covering the entire conductive layer 62, which forms around the cuvettes 70 a conductive ring from initial contacts 55. The insulating layer 71 is for example a thick coarse oxide deposited at low temperature (200-250 ° C.).

The next step, illustrated in FIG. 6D, is identical to the step in FIG. 5C and consists in depositing in the insulated bowls 70 an assembly material 64 forming protuberances, optionally by means of a joining material. 63. The electrical connection between the cuvettes 70 and the inputs / outputs of the integrated circuit regions 51 is ensured here by the fact that the junction material 63 or contact material 64 (in the absence of junction material 64) substantially extends beyond the cuvettes 70 and is in contact with the conductive layer 62.

These steps are followed by steps of thinning the wafer 50 and making contacts 65 on the rear face, which have been described above in relation to FIGS. 5D, 5E.

Figures 7 to 13 are sectional views illustrating other alternative embodiments of conductive bushings according to the invention and of contacts on the rear face. These variants have particularities which can be combined to make still other alternative embodiments of conductive bushings according to the invention.

The wafer 50 of Figure 7 has conductive crossings 60 similar to those of Figure 5E. The contact on the rear face differs from that described above in that a conductive layer 66 is deposited and etched on the insulating layer 53, before the protuberances 65 are deposited. The conductive layer 66, for example copper for an insulating layer : 3 in polyimide, is etched so as to form contact pads covering the openings 54 made in the insulating layer 53.

In FIG. 8A, the conductive layer 66 extends beyond the openings 54 in the form of conductive tracks 67 ending in contact pads 68 on which the protuberances of the assembly material 65 are deposited. In FIG. 8B, it can be seen that the tracks 67 make it possible to offset at any point on the rear face of the silicon wafer 50 the contact pads 68 receiving the protrusions 65. FIG. 8B also shows that conductive bushings 60 according to the invention are not necessarily arranged at the periphery of an integrated circuit region 51. For example, the integrated circuit region 51 located on the front face may have the shape of a frame, as shown by dotted lines, and conductive crossings 66 may be provided inside this frame.

The wafer 50 of FIG. 9 comprises conductive bushings 80 which differ from those of FIG. 5E in that the contacts on the front face are themselves offset with regard to the locations where the bushings 80 open out. Here, the junction material 63 has two layers 63-1, 63-2. The first layer 63-1 is deposited or formed in the bushings 80 and the second layer 63-2 is deposited or formed on a first passivation layer 52-1 provided with openings facing the conductive layer 62. The second layer 63 -2, which is in contact with the conductive layer 62, is covered by a second passivation layer 52-2. The second passivation layer 52-2 has openings facing the second layer 63-2 of the junction material 63 in which the protuberances of the assembly material 64 are deposited. By this method, the protrusions on the front face can be arranged at any point on the surface of the wafer 50, including above the regions of integrated circuits 51 as seen in FIG. 9.

The wafer 50 of FIG. 10 has conductive crossings 81 which differ from those of FIG. 5E in that the conductive layer 62 does not cover the walls of the conductive crossings 81, which are always insulated by the layer 61. As for the embodiment of FIG. 6D, the electrical contact between the conductive layer 62 and the junction material 63 (or the joining material 64 in the absence of junction material 63) is ensured by an overflow of the junction material 63 (or assembly material 64) on the layer 62, outside the bushings 81.

As illustrated in FIG. 11, the wafer 50 may also include conductive bushings 82 which are not electrically connected to the integrated circuit region 51. In this case, the bushings 82 simply comprise an insulating layer 72 covering their walls and are filled by the assembly material 64. As will be seen later, such bushings 82 make it possible to transfer an electrical signal through a silicon wafer in an assembly of several silicon wafers.

In FIG. 12, the wafer 50 comprises conductive crossings 83 devoid of contact on the front face, the upper mouth of the crossings 83 being covered by the passivation layer 52. The walls of the crossings 83 are covered by the insulating layer 61 and the conductive layer 62. Such bushings 83 can be filled with a conductive material. They can also be left empty or, as shown in FIG. 12, be filled with an insulating material 73. In this case, the continuity electrical with the conductive layer 66 on the rear face, which carries the protuberances of the assembly material 65, is ensured by a "T" contact between the layer 62 and the layer 66.

In FIG. 13, the wafer 50 has bushings 84 filled with the assembly material 64 which forms both protrusions 64-1 on the front face and protrusions 64-2 on the rear face. The protrusions 64-2 on the rear face are obtained before the deposition of the insulating layer 53 by an over-etching of the rear face of the wafer 50, for example by continuing abrasion of the rear face chemically without mechanical abrasion in order to remove some additional micrometers of silicon without attacking the assembly material 64. Once the silicon is removed, the assembly material 64 is thus protruding from the rear face and forms the protuberances 64-2. The rear face of the wafer 50 is then covered by the insulating layer 53. The insulating layer 53 covering the protrusions 64-2 is removed by etching or by fine polishing of the rear face.

In practice, the wafer 50 which has just been described, comprising conductive bushings according to the invention, can be assembled with another wafer before being cut. In this case, the assembly of future integrated circuit wafers is carried out collectively at the "wafer level" and the cutting of the assembled wafers makes it possible to directly obtain stacks of integrated circuit wafers. The assembly of integrated circuit wafers can also be carried out at the "chip level", that is to say after the cutting of the wafers into individual integrated circuit wafers. Whatever method is chosen, the present invention makes it possible to produce stacks of integrated circuit wafers, examples of which 90, 95 are shown schematically in Figures 14 and 15.

The stack 90 of FIG. 14 includes three integrated circuit boards 91, 92, 93 comprising contacts on the front face and on the rear face electrically connected by conductive bushings according to the invention. The contacts on the rear face of the wafer 91 are welded or bonded to the contacts on the front face of the wafer 92, and the contacts on the rear face of the wafer 92 are welded or glued to the contacts on the front face of the wafer 93. The contacts in rear face of the plate 93 are welded or bonded to contact pads of an interconnection support 94. The welding or bonding of the contacts located opposite is ensured by melting or polymerization of the assembly material described above (tin - lead, conductive adhesive, ACP, ACF ...).

Of course, when two integrated circuit wafers are assembled, the assembly material may only be deposited on one face of one of the two wafers.

Thus, it is clear that in the description and in the claims, the term "contact" designates the protuberances of the assembly material 64, 65 (FIGS. 5E, 7, 8A, 9, 10, 11, 12, 13) when that this is deposited but also denotes, when the assembly material is not deposited, the conductive pads intended to receive the assembly material, for example the conductive pads on the rear face formed by the conductive material 66 (FIGS. 7, 8A, 12) or the conductive pads on the front face formed by the junction material 63 (Figures 7, 8A, 10).

The stack 95 of FIG. 15 comprises three plates 96, 97, 98. The plate 96, of conventional type, only has contacts opposite

ant. Platelets

97, 98 are provided with contacts on the front and face rear connected by conductive crossings. The contacts on the front face of the wafer 96 are welded or glued to the contacts on the front face of the wafer 97 (the wafer 96 being mounted in "flip chip") and the contacts on the rear face of the wafer 97 are welded or glued to the contacts on the front face of the plate 98. The contacts on the rear face of the plate 98 are welded or glued to contact pads of an interconnection support 99. It can be seen in the figure that the contacts on the front face of the plate 98 are offset relative to the contacts on the rear face, thanks to an offset of the location of the contacts ("re-routing") of the type described above in relation to FIG. 9. A shift of the contacts on the rear face can also be provided, as described above in relation to FIGS. 8A, 8B.

When such stacks are produced collectively at the "wafer stage", it is advantageous to inject between the two silicon wafers assembled a damping material 86, which facilitates the cutting of the wafers and protects the regions of integrated circuits. After cutting the wafers, the material 86 fills the space between the silicon wafers, as shown in FIGS. 14 and 15, and gives the assembly good mechanical cohesion.

Of course, the present invention is susceptible of various other embodiments, variants and applications.

Thus, FIG. 16A represents a silicon wafer 58 cut out from the wafer 50 previously described by following cutting lines passing through the center of the conductive bushings according to the invention. The structure of these conductive crossings can be any of the structures previously described. We get in this case of ccnductive crossings 85 sectioned along their longitudinal axis. These "half-crossings" 85 run along the edges of the wafer 58 and are connected on the front face to the integrated circuit region 51 by the conductive layer 62 already described. On the rear face of the wafer 58, shown in FIG. 16B, the conductive layer 66 already described forms sections of tracks oriented towards the center of the rear face, at the ends of which are the protuberances of the assembly material 65. This embodiment allows in particular to reduce the number of conductive crossings made on a silicon wafer, each crossing splitting into two half-crossings on the edges of two separate silicon wafers.

FIG. 17 schematically represents an example of an electronic circuit which can be produced in the form of a stack of integrated circuit wafers according to the invention. The circuit includes a microprocessor MP, a memory MEM and a power supply circuit PWS. The microprocessor MP comprises a first port of eight inputs / outputs connected to a bus B1 comprising wires βi to es, and a second port of eight inputs / outputs connected to a bus B2 comprising wires in to eiβ. The memory MEM includes a port of eight inputs / outputs connected to the wires in eig of the bus B2. The microprocessor MP, the memory MEM and the circuit PWS each have a terminal connected to the ground GND. The circuit PWS receives an external voltage Vcc and delivers a first voltage VI applied to the memory MEM and to the microprocessor MP and two other voltages V2, V3 applied only to the microprocessor MP.

FIG. 18A represents a printed circuit board 100 intended to connect the elements MP, MEM, PWS to the buses Bl, B2 as well as to the voltage Vcc and to the ground GND.

The wafer 100 thus comprises eight conductive tracks ei a es (bus Bl), eight conductive tracks in ae _l8 (bus B2), a ground track GND and a track carrying the voltage Vcc. These various tracks end in metallized areas arranged in a rectangular pattern.

FIGS. 18B, 18C, 18D respectively represent, by views on the front face, three silicon wafers 101, 102, 103 which are stacked as illustrated in FIG. 14 to make the circuit of FIG. 17. The wafer 101 has a region of integrated circuit MP where the microprocessor MP is installed, the wafer 102 comprises a region of integrated circuit MEM and the wafer 103 comprises a region of integrated circuit PWS.

The plate 101 is arranged on the printed circuit 100 and comprises on the front face 18 contacts ei-eβ, en-eie, GND, Vcc connected to conductive bushings, as well as 3 contacts VI, V2, V3 devoid of conductive bushings. The 18 conductive bushings eι ~ es, en-e ^, GND, Vcc lead to contacts on the rear face (not shown) coinciding with the contact pads of the printed circuit 100. All the contacts except the Vcc contact are connected has integrated MP circuit region.

The plate 102 is arranged on the plate 101 and has for this purpose on the front face 13 contacts e-eis, GND, Vcc, VI, V2, V3 connected to conductive bushings opening on the rear face on contacts coinciding with the corresponding contacts of the wafer 101. The contacts en-e ₁₈ , GND, VI are connected to the integrated circuit region MEM and the contacts Vcc, V2, V3 are isolated from the integrated circuit region MEM.

Finally, the plate 103, which dissipates the most heat, is arranged on the plate 102 and comprises on the front face 5 conductive crossings GND, Vcc, VI, V2, V3 connected to the integrated PWS region, leading to contacts on the rear face coinciding with the corresponding contacts of the plate 102.

As shown in FIGS. 18A to 18D, additional contacts not connected to the integrated circuit regions can be provided on the front (solid lines) and rear (dotted lines) faces of the plates 101 to 103 for regular distribution of the contacts and better fixing of these various elements.

Compared to a conventional flat mounting, the stacking of plates 101, 102, 103 according to the invention makes it possible not only to reduce by three the dimensions of the plates on the surface of the printed circuit 100, but also to eliminate the conductive tracks. that would be necessary for their interconnection. Thus, the connection of the memory MEM to the bus B2 (in at e ₈ ) is provided by conductive crossings, and the voltages V2, V3 supplied by the power supply circuit PWS of the wafer 103 are applied directly to the microprocessor MP of the wafer 101 by means of wafer 102 which for this purpose has crossings V2, V3 which are not connected to the region of integrated circuit MEM.

Of course, the conductive bushings and contacts on the rear face according to the invention are not only applicable to the assembly of several integrated circuit boards. They can also make it possible to connect a simple integrated circuit board on an interconnection support, for example on a printed circuit or a hybrid circuit thick layers or thin layers. This chip transfer technique constitutes an alternative to conventional techniques of the “chip and son” or “flip chip” type described in the preamble in relation to FIGS. 1 and 2. There will now be described in relation to FIGS. 19A to 19E a method making it possible to produce cuvettes in a virgin monocπstallin silicon wafer before the implantation of electronic components, without altering the surface of the wafer.

As illustrated in FIG. 19A, one begins by successively depositing on the two faces of the silicon wafer 50 a layer 110 of silicon oxide Sι02 and a layer 111 of nitride, for example silicon nitride Sι3N4. The oxide layer 110 is deposited in a conventional manner in a "hydrox" oven intended to grow oxide and the nitride layer 111 is deposited in an LPCVD ("Low Pressure Chemical Vapor") oven. The wafer 50 is of a standard thickness of the order of 700 micrometers. The oxide layer 110 is of the order of 90 nanometers thick and the nitride layer 111 is 160 nanometers thick.

During a step illustrated in FIG. 19B, a photosensitive resin mask 112 is provided on the surface of the wafer 50 comprising openings 113 in regions where cuvettes must be produced. The nitride layer 111 located opposite the openings 113 is attacked by means of an "Al" etchant, for example a cold plasma CF4 (mechanical etching) or a solution of orthophosphoric acid H3PO4 (chemical etching). The oxide layer 110 is then attacked using an etchant "B1", for example a cold plasma or a solution of hydrofluoric acid or ammonium fluoride.

As illustrated in Figure 19C, the resin mask 112 is then dissolved or removed with an oxygen plasma.

The plate 50 is provided with an etching mask constituted by the layers of oxide 110 and nitride 111, having openings 114 at the places where the openings 113 of the resin mask were located. The wafer 50 is then immersed in a solution comprising an etching agent "C" attacking the monocrystalline silicon 50 without attacking the nitride 111, causing the cuvettes 60 to appear. This solution is for example a KOH potash solution of concentration 6N brought to a temperature of the order of 80 ° C., capable of containing an accelerating etching agent. Such a solution makes it possible to etch monocrystalline silicon at a speed of the order of 1.6 micrometers per minute and a selectivity greater than 1/23000 relative to the nitride layer 111. Thus, the etching of a bowl 60 of a depth of 100 micrometers is produced in approximately one hour and causes etching of the nitride layer 111 of the order of 4.3 nanometers, negligible with regard to its total thickness.

The bowls 60 being produced, the nitride layer 111 is removed by means of an etching agent "A2" capable of attacking the silicon of the bowls 60 although this is not desired. The agent "A2" is for example a cold plasma or a solution of orthophosphoric acid. As it is technically difficult to stop the process at the precise moment when the last atom of the nitride layer 111 is dissolved, the oxide layer 110 protects the silicon wafer 50. The oxide layer 110 is then removed, preferably by means of a chemical etching agent "B2" which does not attack monocrystalline silicon, for example hydrofluoric acid.

These steps being completed, there is a virgin silicon wafer 50 provided with cuvettes 60 intended to form conductive bushings according to the invention, as has been described above. Potash attacking silicon isotropically, that is to say according to the orientation of the atoms of the crystal lattice (1,0,0), the cuvettes have four walls inclined by about 58 ° relative to the surface of the wafer 50. In general, the shape of a cuvette according to the invention is given by the following relation:

(1) Wb = Wo - 2D cotg (58 °)

either approximately

(2) Wb Wo - 1.25 D

in which D is the depth of the cuvette, Wo is the opening or size of the cuvette (i.e. its width at the surface of the silicon wafer) and Wb is the width at the bottom of the cuvette (i.e. the size of the contact obtained on the back). To fix the ideas, the table below gives various values of the width Wb of the contact on the rear face according to the opening Wo and the depth D of a bowl, for a range of values of the depth D going from 30 to 110 micrometers. The surface of the contact on the rear face can of course be enlarged by the production of conductive pads, as has been described above.

Claims

1. A method of manufacturing conductive bushings (60, 70, 80-85) in a silicon wafer (50), characterized in that it comprises the steps consisting in: - producing cuvettes (60, 70) of a depth determined on the front face of the silicon wafer, deposit on the walls of the cuvettes an electrically insulating material (61, 71, 72),

- depositing at least one electrically conductive material (62, 63, 64) on the insulated walls of the bowls, and

- thin the silicon wafer (50), by chemical and / or mechanical abrasion of its rear face, until reaching the conductive material (62, 63, 64) deposited in the cuvettes.

2. The method of claim 1, wherein the step of depositing on the walls of the cuvettes (60) of a conductive material comprises a step of filling the cuvettes with at least one conductive material (63, 64).

3. Method according to one of claims 1 and 2, wherein the cuvettes (60) are produced before the implantation of an integrated circuit region (51) on the silicon wafer.

4. Method according to one of claims 1 and 2, wherein the cuvettes (70) are produced after the implantation of an integrated circuit region (51) on the silicon wafer.

5. Method according to one of claims 1 to 4, comprising a step consisting in plastering on the rear face of the wafer at least one layer of an electrically insulating material (53), and a step consisting in make contact pads (65, 66) connected to the conductive bushings (60, 70) on the rear face.

6. Method according to one of claims 1 to 5, comprising a step of cutting the silicon wafer (50) through the middle of the conductive bushings (60, 70, 80-84) to obtain at least one wafer silicon (58) comprising conductive bushings (85) sectioned along their longitudinal axis, along the sides of the wafer (58).

7. Method for interconnecting at least two integrated circuit boards, characterized in that it comprises the steps consisting in: - providing an integrated circuit board (91-93, 96-98) comprising contacts (65, 66) in rear face electrically connected to an integrated circuit region (51) on the front face by conductive bushings (60, 70, 80- 85) passing through the board, and - soldering or gluing the contacts (65, 66) in rear face of the wafer with contacts (64) on the front face of another silicon wafer.

8. The method of claim 7, wherein the conductive bushings comprise orifices (60,

70) formed in the silicon wafer, an electrically insulating layer (61, 71, 72) covering the walls of the orifice, and at least one electrically conductive material (62, 63, 64) covering the insulated walls of the orifice or completely filling the orifice.

9. Method according to one of claims 7 and 8, wherein the conductive bushings are sectioned (85) along their longitudinal axis and along the sides of the plates.

10. Silicon wafer (50, 58) comprising an integrated circuit region (51) located on its front face, characterized in that it comprises conductive bushings (60, 70, 80-85) connected to the circuit region integrated, crossing the plate from side to side and opening onto its rear face.

11. The silicon wafer according to claim 10, in which a conductive bushing comprises an orifice (60, 70) passing through the silicon wafer, an electrically insulating layer (61, 71, 72) covering the walls of the orifice, and at at least one electrically conductive material (62, 63, 64) covering the insulated walls of the orifice or completely filling the orifice.

12. Silicon wafer according to one of claims 10 and 11, comprising on its rear face contacts (65, 66) electrically isolated from the wafer (50) and electrically connected to conductive bushings (60, 70, 80-85 ).

13. Silicon wafer according to one of claims 10 to 12, further comprising conductive bushings (82) which are not connected to the integrated circuit region (51).

14. Silicon wafer (58) according to one of claims 10 to 13, comprising conductive bushings (85) sectioned along their longitudinal axis, along the sides of the wafer.

15. Assembly (90, 95) of silicon wafers comprising at least one stack of two silicon wafers (50, 58, 91-93, 96-98), each wafer comprising an integrated circuit region (51) on the front face and contacts (63, 64, 65, 66) welded or glued to contacts of the other plate, characterized in that at least one plate (91-93, 97, 98) comprises contacts on the rear face (65, 66) and conductive bushings (60, 70, 80-85) crossing the wafer right through, electrically connecting the contacts (65, 66) on the rear face to the integrated circuit region (51).

16. An assembly of silicon wafers according to claim 15, in which contacts (65, 66) on the rear face of a wafer are welded or bonded to contacts (63, 64) on the front face of the other silicon wafer .

17. An assembly of silicon wafers according to one of claims 15 and 16, in which conductive bushings comprise orifices (60, 70) practical in the silicon wafer, an electrically insulating layer (61, 71, 72) covering the walls of the orifice, and at least one electrically conductive material (62, 63, 64) covering the insulated walls of the orifice or completely filling the orifice.

18. An assembly of silicon wafers according to one of claims 15 to 17, in which at least one silicon wafer has at least one conductive bushing (82) which is not connected to its integrated circuit region (51).

19. An assembly of silicon wafers according to one of claims 15 to 18, in which at least one wafer (58) comprises conductive cross-sections (85) along their longitudinal axis, along the sides of the wafer.