WO2001045167A2 - Integrated circuit package formed at a wafer level - Google Patents
Integrated circuit package formed at a wafer level Download PDFInfo
- Publication number
- WO2001045167A2 WO2001045167A2 PCT/US2000/042765 US0042765W WO0145167A2 WO 2001045167 A2 WO2001045167 A2 WO 2001045167A2 US 0042765 W US0042765 W US 0042765W WO 0145167 A2 WO0145167 A2 WO 0145167A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bonding pads
- layer
- wafer
- metallized
- openings
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the invention relates generally to integrated circuit packages, and more specifically to a ball-grid array integrated package formed at a wafer level .
- the footprint of an integrated circuit package on a circuit board is the area of the board occupied by the package. It is generally desired to minimize the footprint and to place packages close together.
- the ball-grid array (BGA) package has emerged as one of the more popular package types because it provides high density, minimum footprint, and shorter electrical paths, which means that it has better performance than previous types of semiconductor packages.
- a typical BGA package is shown in Fig. 9.
- an integrated circuit chip 122 is mounted by means of an adhesive on an upper surface of a base 112 made of a substrate material .
- Metal bonding wires or wirebond leads 120 electrically connect a plurality of metal chip pads 126 formed on the upper surface of the chip 122 with wire bonding pads 128 formed on the upper surface of the base 112.
- the base 112 includes plated through-hole vias 118 and metal traces 114 to connect the circuitry from the upper surface to the lower surface of the base 112.
- a plurality of solder balls 116 are placed on the bottom surface of the base 112 and are electrically connected to the metal traces 114 of the base.
- the solder balls 116 can be arranged in a uniform full matrix array over the entire bottom surface, in a staggered full array, or around the perimeter of the bottom surface in multiple rows. The solder balls are then used to secure the chip package onto a printed circuit board in the end-use product. While the BGA packages of the prior art provide a great improvement over earlier types of packages in terms of high density and high I/O capability, it is always desired to make the IC package even smaller to further decrease the amount of space needed on a printed circuit board to accommodate the package. Because the wirebond leads are of a predetermined length and require a minimum spacing between adjacent bonding sites to provide sufficient room for the bonding tool, the substrate base must be larger than the chip and it is not possible to fabricate a more compact package. Ideally, it is desired to make a package in which the substrate base does not have to be any larger than the size of the chip .
- the above objects have been achieved in an integrated circuit package that is formed on the wafer level using a flip chip design with a single wafer.
- the integrated circuit package is formed by first providing a product silicon wafer having a plurality of microelectric circuits fabricated thereon and having a plurality of standard aluminum bonding pads exposed. The aluminum bonding pads are re-metallized to be solderable. Then, a layer of adhesive is deposited onto the wafer surface, the bonding pads remaining exposed. A pre- fabricated interposer substrate, having metallized openings, is aligned to the wafer and then the assembly is cured.
- Solder, or conductive adhesive is then deposited through the openings in the substrate and the assembly is reflowed, or cured, to form the electrical connection between the circuitry on the substrate and the bonding pads on the silicon wafer. Solder balls are then placed on the metal pads or the substrate and are then reflowed forming a BGA structure The wafer is then diced and the individual BGA packages are formed. The BGA package is flipped for mounting on a circuit board.
- the integrated circuit package of the present invention is smaller than BGA packages of the prior art in that the additional space usually required because of the use of wirebonding leads is not necessary.
- the whole wafer can be packaged all at one time which is more efficient than packaging each die individually and allows for parallel testing of the packaged dice while still in wafer form.
- FIG. 1 is a perspective view of a silicon wafer having a plurality of chips formed on a top surface.
- Fig. 2 is a cross-sectional view of a section 2-2 of the silicon wafer shown in Fig. 1.
- Figs. 3-6 are cross-sectional views of the silicon wafer of Fig. 1 showing the various process steps used in forming the IC package of the present invention.
- Fig. 7 is a cross-sectional view of the silicon wafer of Fig. 1, showing the finalized wafer assembly for the IC package of the present invention.
- Fig. 8 is a cross-sectional view of the finalized IC package of the present invention.
- Fig. 9 is a cross-sectional view of a ball-grid array package as known in the prior art .
- a silicon wafer 21 has a plurality of microcircuits fabricated thereon.
- the microcircuits are arranged into a matrix of individual chips or dice 24, 25.
- a plurality of aluminum bonding pads 23 are arranged around the perimeter of each of the chips .
- the wafer 21 is usually diced at this point into individual chips, and each of the individual chip is then packaged.
- the chips are formed on the wafer but are not diced until the packaging operation on the wafer has been completed, thus the packaging of the chip is conducted at the wafer level.
- a section 2-2 of the wafer 21 is shown, with the aluminum bonding pads 23 being disposed on a top surface of the wafer 21.
- the first step in the packaging process is to re-metallize the aluminum bonding pads 23 in order to make the bonding pads solderable.
- Aluminum which is commonly used for the wirebond pads of IC's, is a less than ideal metal for use in solder connections due to the fact that the aluminum tends to oxidize which creates bonding problems.
- the aluminum bonding pads need to be wetable by solder or have a low ohmic contact resistance for application of a conductive adhesive. Therefore, the bonding pads need to be re-metallized.
- One process for re-metallizing the bonding pads is to use electroless nickel- gold plating.
- a layer of zinc is deposited on the aluminum bonding pads 23, then a layer of electroless nickel plating is deposited on the layer of zinc and, then, a layer of electroless gold plating is deposited on top of the electroless nickel plating to form a nickel-gold plating 19 in order to make the bonding pads 23 conducive to soldering.
- a thin film metallization process can be carried out to re-metallize the bonding pads.
- a layer of adhesive 27 is deposited on the top surface of the wafer 21 such that the bonding pads 23 are left uncovered.
- the adhesive can be made of a silicone elastomer.
- the adhesive layer 27 can be applied through a screen printing process in which the silicone elastomer material is pushed through the openings of a stencil or a mesh screen.
- the screen is mounted onto a screen printer and is precisely positioned with respect to the wafer. A certain amount of the silicone elastomer material is dispensed along one edge of the screen and an air- operated squeegee presses down on the screen as it sweeps across it, sheering the material at a constant pressure.
- the material acquires higher flowability above certain shear pressures, which allows it to go through the screen and fill the gaps left by the wire mesh of the screen.
- the area above the bonding pads 23 is blocked so that no material is laid on top of the bonding pads.
- the screen is removed and a uniform layer of the material is formed on top of the wafer.
- an adhesive layer preform can be used to adhere the adhesive layer 27 to the top surface of the wafer 21 or to the backside of an interposer substrate layer.
- the silicone elastomer acts as an encapsulant, providing environmental protection for the wafer.
- the silicone elastomer also acts as a buffer for the wafer 21 from external stresses, such as a thermal coefficient of expansion mismatch between the wafer and the package solder balls used for mounting the IC package, or a mismatch between the wafer and an end- use printed circuit board on which the IC package would be mounted.
- an interposer substrate layer 30 is then secured on top of the elastomer layer 27 to form a wafer assembly 39.
- the interposer substrate 30 is a preformed substrate consisting of metal circuitry 34 and a dielectric base 32.
- the metal circuitry 34 typically consists of copper traces formed throughout the substrate.
- the interposer substrate 30 can also include solder resist coatings to help define solder wetable areas on the copper metal circuitry.
- the metal circuitry 34 can be formed on a single layer or on multiple layers of the interposer substrate 30.
- the copper metal circuitry can be nickel- gold plated or coated by an organic material .
- the dielectric base material 32 is typically made of a polya ide base substrate.
- BT resin and other epoxy-glass substrates can also be used as the dielectric base material 32.
- the metal circuitry 34 generally serves as interconnect circuitry, as the traces can be routed throughout the substrate to interconnect the circuits from the various bonding pads 23 to the Input/Output (I/O) interconnects which will be added to the wafer assembly 39, as described later with reference to Fig. 7.
- a key feature of the interposer substrate 30 is a plurality of openings 36 on the copper circuitry.
- the interposer substrate 30 can be approximately the same size as the wafer 21 and is aligned to the wafer 21 such that the openings 36 line up with the bonding pads 23.
- a sufficient amount of copper must be present in the openings 36 to provide adequate connection for solder or for a conductive adhesive.
- a circular copper ring around the openings 36 or a copper strip across the openings 36 can be used to facilitate this requirement.
- the interposer substrate 30 is then adhered by a bonding adhesive to the elastomer layer 27 and the wafer assembly 39 is then cured. Thus, the interposer is aligned and bonded to the wafer.
- a layer of solder paste 40 is deposited through the openings 36 of the interposer substrate 30. This can be carried out by a screen or stencil printing process in the same manner as described above with reference to the depositing of the elastomer layer 27.
- the interposer substrate base 32 layer is screened o::f and the solder paste 40 is deposited into the openings 36 by an air-operated squeegee so that the solder paste 40 is deposited on the wafer all at one time.
- the wafer 21 is then solder reflowed to form a plurality of electrical connections between the bonding pads 23 on the wafer 21 and the copper metal circuitry 34 in the interposer substrate layer 30.
- solder paste can also be deposited through the openings of the interposer substrate by the use of automatic dispensing equipment or by solder preform placement.
- a conductive adhesive may be used, in lieu of the solder paste, to electrically connect the bonding pads 23 and the metal circuitry 34.
- the adhesive is deposited in the openings 36 and then is cured to form the electrical connections.
- an epoxy material can be used to protect the solder connections. Application of the epoxy material would also be by the screen or stencil printing process described above and the protective coating would then be cured.
- the next step is to place package solder balls on the wafer.
- the package solder balls serve as the I/O interconnects for the package and will be used to secure the completed IC package to an end-use printed circuit board.
- the solder balls 50 are placed on the metallized openings 36 through a mechanical transfer of pre-formed solder balls.
- the solder balls 50 can be formed by screen or stencil printing solder paste.
- the solder is then reflowed to form the package solder balls.
- the solder balls 50 are applied in whatever type of pattern is desired, such as in a uniform full matrix over the entire surface. At this point, electrical testing may be conducted on the wafer assembly 39 since the wafer assembly 39 contains finished dice arranged in a matrix format.
- the wafer assembly 39 is diced, or singulated, to form individual chip-size BGA packages 70, 72.
- a common technique for the singulation is to use a wafer saw with diamond or resinoid saw blades.
- the finished BGA package 70 can then be mounted on the end-use printed circuit board in the same manner as prior art BGA packages.
- the BGA package 70 of the present invention has the same footprint as the individual silicon die, as no extra space is needed to accommodate wirebond leads or larger substrate bases. In this way, the integrated circuit package of the present invention provides the advantages of a smaller package size and the convenience of packaging at the wafer level.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002392837A CA2392837A1 (en) | 1999-12-14 | 2000-12-11 | Integrated circuit package formed at a wafer level |
EP00992704A EP1238427A2 (en) | 1999-12-14 | 2000-12-11 | Integrated circuit package formed at a wafer level |
JP2001545366A JP2004537841A (en) | 1999-12-14 | 2000-12-11 | Integrated circuit package formed at wafer level |
KR1020027007432A KR20020059851A (en) | 1999-12-14 | 2000-12-11 | Integrated circuit package formed at a wafer level |
NO20022792A NO20022792L (en) | 1999-12-14 | 2002-06-12 | Integrated circuit package formed at a silicon wafer level |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/460,902 US6388335B1 (en) | 1999-12-14 | 1999-12-14 | Integrated circuit package formed at a wafer level |
US09/460,902 | 1999-12-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001045167A2 true WO2001045167A2 (en) | 2001-06-21 |
WO2001045167A3 WO2001045167A3 (en) | 2002-05-23 |
Family
ID=23830502
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/042765 WO2001045167A2 (en) | 1999-12-14 | 2000-12-11 | Integrated circuit package formed at a wafer level |
Country Status (10)
Country | Link |
---|---|
US (2) | US6388335B1 (en) |
EP (1) | EP1238427A2 (en) |
JP (1) | JP2004537841A (en) |
KR (1) | KR20020059851A (en) |
CN (1) | CN1217410C (en) |
CA (1) | CA2392837A1 (en) |
MY (1) | MY135942A (en) |
NO (1) | NO20022792L (en) |
TW (1) | TW490822B (en) |
WO (1) | WO2001045167A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001082361A2 (en) * | 2000-04-25 | 2001-11-01 | Atmel Corporation | Method of forming an integrated circuit package at a wafer level |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6078100A (en) * | 1999-01-13 | 2000-06-20 | Micron Technology, Inc. | Utilization of die repattern layers for die internal connections |
US6713854B1 (en) | 2000-10-16 | 2004-03-30 | Legacy Electronics, Inc | Electronic circuit module with a carrier having a mounting pad array |
US6487078B2 (en) * | 2000-03-13 | 2002-11-26 | Legacy Electronics, Inc. | Electronic module having a three dimensional array of carrier-mounted integrated circuit packages |
US7102892B2 (en) * | 2000-03-13 | 2006-09-05 | Legacy Electronics, Inc. | Modular integrated circuit chip carrier |
CN1311547C (en) * | 2000-03-23 | 2007-04-18 | 精工爱普生株式会社 | Semiconductor device, method of manufacture thereof, circuit board and electronic device |
US7337522B2 (en) * | 2000-10-16 | 2008-03-04 | Legacy Electronics, Inc. | Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
US6524885B2 (en) * | 2000-12-15 | 2003-02-25 | Eaglestone Partners I, Llc | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
EP1378152A4 (en) * | 2001-03-14 | 2006-02-01 | Legacy Electronics Inc | A method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
TW523857B (en) * | 2001-12-06 | 2003-03-11 | Siliconware Precision Industries Co Ltd | Chip carrier configurable with passive components |
US6492196B1 (en) * | 2002-01-07 | 2002-12-10 | Picta Technology Inc. | Packaging process for wafer level IC device |
US6800948B1 (en) * | 2002-07-19 | 2004-10-05 | Asat Ltd. | Ball grid array package |
US6987032B1 (en) * | 2002-07-19 | 2006-01-17 | Asat Ltd. | Ball grid array package and process for manufacturing same |
US6979594B1 (en) | 2002-07-19 | 2005-12-27 | Asat Ltd. | Process for manufacturing ball grid array package |
JP2004134648A (en) * | 2002-10-11 | 2004-04-30 | Seiko Epson Corp | Circuit board, mounting structure of ball grid array, electro-optical device, and electronic apparatus |
KR100512971B1 (en) * | 2003-02-24 | 2005-09-07 | 삼성전자주식회사 | Manufacturing method of micro electro mechanical system using solder ball |
JP2004335915A (en) * | 2003-05-12 | 2004-11-25 | Shinko Electric Ind Co Ltd | Method for manufacturing semiconductor device |
JP4130158B2 (en) * | 2003-06-09 | 2008-08-06 | 三洋電機株式会社 | Semiconductor device manufacturing method, semiconductor device |
US6974776B2 (en) * | 2003-07-01 | 2005-12-13 | Freescale Semiconductor, Inc. | Activation plate for electroless and immersion plating of integrated circuits |
KR100541394B1 (en) | 2003-08-23 | 2006-01-10 | 삼성전자주식회사 | NSMD type substrate for ball grid array package and manufacturing method thereof |
US7372151B1 (en) | 2003-09-12 | 2008-05-13 | Asat Ltd. | Ball grid array package and process for manufacturing same |
US7073702B2 (en) * | 2003-10-17 | 2006-07-11 | International Business Machines Corporation | Self-locking wire bond structure and method of making the same |
KR100676493B1 (en) * | 2004-10-08 | 2007-02-01 | 디엔제이 클럽 인코 | method for manufacturing wafer level chip scale package using redistribution substrate |
WO2006076381A2 (en) * | 2005-01-12 | 2006-07-20 | Legacy Electronics, Inc. | Radial circuit board, system, and methods |
US8610262B1 (en) | 2005-02-18 | 2013-12-17 | Utac Hong Kong Limited | Ball grid array package with improved thermal characteristics |
US7245013B2 (en) * | 2005-07-26 | 2007-07-17 | Infineon Technologies Ag | Substrate based IC-package |
AT9551U1 (en) * | 2006-05-16 | 2007-11-15 | Austria Tech & System Tech | METHOD FOR FIXING AN ELECTRONIC COMPONENT ON A PCB AND A SYSTEM CONSISTING OF A PCB AND AT LEAST ONE ELECTRONIC COMPONENT |
US7824965B2 (en) * | 2007-08-07 | 2010-11-02 | Skyworks Solutions, Inc. | Near chip scale package integration process |
JP5510795B2 (en) * | 2008-01-30 | 2014-06-04 | 日本電気株式会社 | Electronic component mounting structure, electronic component mounting method, and electronic component mounting substrate |
CN101572257B (en) * | 2008-04-30 | 2011-02-16 | 南茂科技股份有限公司 | Chip packaging tape and chip packaging structure containing same |
TWI387067B (en) * | 2009-03-17 | 2013-02-21 | Chipmos Technologies Inc | Substrateless chip package and fabricating method |
US8367475B2 (en) * | 2011-03-25 | 2013-02-05 | Broadcom Corporation | Chip scale package assembly in reconstitution panel process format |
TWI487042B (en) * | 2012-10-18 | 2015-06-01 | 旭德科技股份有限公司 | Packaging process |
US20180315682A1 (en) * | 2015-10-21 | 2018-11-01 | GM Global Technolgy Operations LLC | Systems and methods for reinforced adhesive bonding using textured solder elements |
US11064615B2 (en) | 2019-09-30 | 2021-07-13 | Texas Instruments Incorporated | Wafer level bump stack for chip scale package |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5747101A (en) * | 1994-02-02 | 1998-05-05 | International Business Machines Corporation | Direct chip attachment (DCA) with electrically conductive adhesives |
DE19702186A1 (en) * | 1997-01-23 | 1998-07-30 | Fraunhofer Ges Forschung | Process for packaging integrated circuits |
JPH11214421A (en) * | 1997-10-13 | 1999-08-06 | Matsushita Electric Ind Co Ltd | Method for forming electrode of semiconductor element |
JP2000036518A (en) * | 1998-07-16 | 2000-02-02 | Nitto Denko Corp | Wafer scale package structure and circuit board used for the same |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4056681A (en) * | 1975-08-04 | 1977-11-01 | International Telephone And Telegraph Corporation | Self-aligning package for integrated circuits |
US5468681A (en) | 1989-08-28 | 1995-11-21 | Lsi Logic Corporation | Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias |
US5504035A (en) | 1989-08-28 | 1996-04-02 | Lsi Logic Corporation | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate |
KR920022482A (en) * | 1991-05-09 | 1992-12-19 | 가나이 쯔도무 | Electronic component mounting module |
KR950012658B1 (en) * | 1992-07-24 | 1995-10-19 | 삼성전자주식회사 | Semiconductor chip mounting method and substrate structure |
US5734201A (en) * | 1993-11-09 | 1998-03-31 | Motorola, Inc. | Low profile semiconductor device with like-sized chip and mounting substrate |
US5539153A (en) * | 1994-08-08 | 1996-07-23 | Hewlett-Packard Company | Method of bumping substrates by contained paste deposition |
JP2581017B2 (en) * | 1994-09-30 | 1997-02-12 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US5495667A (en) * | 1994-11-07 | 1996-03-05 | Micron Technology, Inc. | Method for forming contact pins for semiconductor dice and interconnects |
US5851845A (en) | 1995-12-18 | 1998-12-22 | Micron Technology, Inc. | Process for packaging a semiconductor die using dicing and testing |
JP3345541B2 (en) * | 1996-01-16 | 2002-11-18 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
JP2842361B2 (en) * | 1996-02-28 | 1999-01-06 | 日本電気株式会社 | Semiconductor device |
JPH1084014A (en) * | 1996-07-19 | 1998-03-31 | Shinko Electric Ind Co Ltd | Manufacture of semiconductor device |
US5604160A (en) | 1996-07-29 | 1997-02-18 | Motorola, Inc. | Method for packaging semiconductor devices |
US5798557A (en) | 1996-08-29 | 1998-08-25 | Harris Corporation | Lid wafer bond packaging and micromachining |
KR100222299B1 (en) | 1996-12-16 | 1999-10-01 | 윤종용 | Wafer level chip scale package and method of manufacturing the same |
US6097098A (en) * | 1997-02-14 | 2000-08-01 | Micron Technology, Inc. | Die interconnections using intermediate connection elements secured to the die face |
JP3176307B2 (en) * | 1997-03-03 | 2001-06-18 | 日本電気株式会社 | Mounting structure of integrated circuit device and method of manufacturing the same |
US5790384A (en) * | 1997-06-26 | 1998-08-04 | International Business Machines Corporation | Bare die multiple dies for direct attach |
US5972734A (en) * | 1997-09-17 | 1999-10-26 | Lsi Logic Corporation | Interposer for ball grid array (BGA) package |
US6081026A (en) * | 1998-11-13 | 2000-06-27 | Fujitsu Limited | High density signal interposer with power and ground wrap |
US6081429A (en) * | 1999-01-20 | 2000-06-27 | Micron Technology, Inc. | Test interposer for use with ball grid array packages assemblies and ball grid array packages including same and methods |
US6281046B1 (en) * | 2000-04-25 | 2001-08-28 | Atmel Corporation | Method of forming an integrated circuit package at a wafer level |
-
1999
- 1999-12-14 US US09/460,902 patent/US6388335B1/en not_active Expired - Fee Related
-
2000
- 2000-07-25 US US09/625,072 patent/US6413799B1/en not_active Expired - Fee Related
- 2000-12-01 MY MYPI20005649A patent/MY135942A/en unknown
- 2000-12-11 JP JP2001545366A patent/JP2004537841A/en not_active Withdrawn
- 2000-12-11 KR KR1020027007432A patent/KR20020059851A/en not_active Application Discontinuation
- 2000-12-11 CA CA002392837A patent/CA2392837A1/en not_active Abandoned
- 2000-12-11 EP EP00992704A patent/EP1238427A2/en not_active Withdrawn
- 2000-12-11 WO PCT/US2000/042765 patent/WO2001045167A2/en active Application Filing
- 2000-12-11 CN CN008172021A patent/CN1217410C/en not_active Expired - Fee Related
- 2000-12-13 TW TW089126574A patent/TW490822B/en not_active IP Right Cessation
-
2002
- 2002-06-12 NO NO20022792A patent/NO20022792L/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5747101A (en) * | 1994-02-02 | 1998-05-05 | International Business Machines Corporation | Direct chip attachment (DCA) with electrically conductive adhesives |
DE19702186A1 (en) * | 1997-01-23 | 1998-07-30 | Fraunhofer Ges Forschung | Process for packaging integrated circuits |
JPH11214421A (en) * | 1997-10-13 | 1999-08-06 | Matsushita Electric Ind Co Ltd | Method for forming electrode of semiconductor element |
JP2000036518A (en) * | 1998-07-16 | 2000-02-02 | Nitto Denko Corp | Wafer scale package structure and circuit board used for the same |
Non-Patent Citations (2)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 13, 30 November 1999 (1999-11-30) -& JP 11 214421 A (MATSUSHITA ELECTRIC IND CO LTD), 6 August 1999 (1999-08-06) * |
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 05, 14 September 2000 (2000-09-14) -& JP 2000 036518 A (NITTO DENKO CORP), 2 February 2000 (2000-02-02) -& EP 0 973 197 A (NITTO DENKO CORP) 19 January 2000 (2000-01-19) * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001082361A2 (en) * | 2000-04-25 | 2001-11-01 | Atmel Corporation | Method of forming an integrated circuit package at a wafer level |
WO2001082361A3 (en) * | 2000-04-25 | 2002-05-16 | Atmel Corp | Method of forming an integrated circuit package at a wafer level |
Also Published As
Publication number | Publication date |
---|---|
EP1238427A2 (en) | 2002-09-11 |
WO2001045167A3 (en) | 2002-05-23 |
JP2004537841A (en) | 2004-12-16 |
CN1217410C (en) | 2005-08-31 |
TW490822B (en) | 2002-06-11 |
US6413799B1 (en) | 2002-07-02 |
MY135942A (en) | 2008-07-31 |
CN1409872A (en) | 2003-04-09 |
NO20022792D0 (en) | 2002-06-12 |
KR20020059851A (en) | 2002-07-13 |
NO20022792L (en) | 2002-06-12 |
US6388335B1 (en) | 2002-05-14 |
CA2392837A1 (en) | 2001-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6413799B1 (en) | Method of forming a ball-grid array package at a wafer level | |
US6281046B1 (en) | Method of forming an integrated circuit package at a wafer level | |
US6344401B1 (en) | Method of forming a stacked-die integrated circuit chip package on a water level | |
US6746898B2 (en) | Integrated chip package structure using silicon substrate and method of manufacturing the same | |
US7205178B2 (en) | Land grid array packaged device and method of forming same | |
US6150193A (en) | RF shielded device | |
US8178964B2 (en) | Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same | |
US6962829B2 (en) | Method of making near chip size integrated circuit package | |
US6051489A (en) | Electronic component package with posts on the active side of the substrate | |
JP3142723B2 (en) | Semiconductor device and manufacturing method thereof | |
US20080237828A1 (en) | Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for wlp and method of the same | |
US20080197469A1 (en) | Multi-chips package with reduced structure and method for forming the same | |
EP2207198A2 (en) | Manufacturing method of a semiconductor device | |
EP0623242A4 (en) | Backplane grounding for flip-chip integrated circuit. | |
US20080157340A1 (en) | RF module package | |
JP2004537841A5 (en) | ||
US6911737B2 (en) | Semiconductor device package and method | |
US6140708A (en) | Chip scale package and method for manufacture thereof | |
US6284566B1 (en) | Chip scale package and method for manufacture thereof | |
US6339253B1 (en) | Semiconductor package | |
WO2002017392A2 (en) | Polymer redistribution of flip chip bond pads |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): CA CN JP KR NO SG |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): CA CN JP KR NO SG |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2392837 Country of ref document: CA |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2000992704 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020027007432 Country of ref document: KR |
|
ENP | Entry into the national phase |
Ref country code: JP Ref document number: 2001 545366 Kind code of ref document: A Format of ref document f/p: F |
|
WWE | Wipo information: entry into national phase |
Ref document number: 008172021 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 1020027007432 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 2000992704 Country of ref document: EP |