WO2001045167A3 - Integrated circuit package formed at a wafer level - Google Patents

Integrated circuit package formed at a wafer level Download PDF

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Publication number
WO2001045167A3
WO2001045167A3 PCT/US2000/042765 US0042765W WO0145167A3 WO 2001045167 A3 WO2001045167 A3 WO 2001045167A3 US 0042765 W US0042765 W US 0042765W WO 0145167 A3 WO0145167 A3 WO 0145167A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
integrated circuit
circuit package
circuitry
metallized
Prior art date
Application number
PCT/US2000/042765
Other languages
French (fr)
Other versions
WO2001045167A2 (en
Inventor
Ken M Lam
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to JP2001545366A priority Critical patent/JP2004537841A/en
Priority to EP00992704A priority patent/EP1238427A2/en
Priority to CA002392837A priority patent/CA2392837A1/en
Priority to KR1020027007432A priority patent/KR20020059851A/en
Publication of WO2001045167A2 publication Critical patent/WO2001045167A2/en
Publication of WO2001045167A3 publication Critical patent/WO2001045167A3/en
Priority to NO20022792A priority patent/NO20022792L/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
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    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/13001Core members of the bump connector
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • H01L2224/73265Layer and wire connectors
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    • H01L2924/10253Silicon [Si]
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    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/181Encapsulation

Abstract

An integrated circuit package (70) that is formed at the wafer level. The integrated circuit package (70) occupies a minimum amount of space on an end-use printed circuit board. A pre-fabricated interposer substrate (30), made of metal circuitry (34) and a dielectric base (32), has a plurality of metallized openings which are aligned with metallized wirebond pads (23) on the top surface of a silicon wafer (21). Solder (40), or conductive adhesive, is deposited through the metallized openings to form the electrical connection between the circuitry on the interposer layer (30) and the circuitry on the wafer (21). Solder balls (50) are then placed on the metal pad openings on the interposer substrate (30) and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.
PCT/US2000/042765 1999-12-14 2000-12-11 Integrated circuit package formed at a wafer level WO2001045167A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2001545366A JP2004537841A (en) 1999-12-14 2000-12-11 Integrated circuit package formed at wafer level
EP00992704A EP1238427A2 (en) 1999-12-14 2000-12-11 Integrated circuit package formed at a wafer level
CA002392837A CA2392837A1 (en) 1999-12-14 2000-12-11 Integrated circuit package formed at a wafer level
KR1020027007432A KR20020059851A (en) 1999-12-14 2000-12-11 Integrated circuit package formed at a wafer level
NO20022792A NO20022792L (en) 1999-12-14 2002-06-12 Integrated circuit package formed at a silicon wafer level

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/460,902 1999-12-14
US09/460,902 US6388335B1 (en) 1999-12-14 1999-12-14 Integrated circuit package formed at a wafer level

Publications (2)

Publication Number Publication Date
WO2001045167A2 WO2001045167A2 (en) 2001-06-21
WO2001045167A3 true WO2001045167A3 (en) 2002-05-23

Family

ID=23830502

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/042765 WO2001045167A2 (en) 1999-12-14 2000-12-11 Integrated circuit package formed at a wafer level

Country Status (10)

Country Link
US (2) US6388335B1 (en)
EP (1) EP1238427A2 (en)
JP (1) JP2004537841A (en)
KR (1) KR20020059851A (en)
CN (1) CN1217410C (en)
CA (1) CA2392837A1 (en)
MY (1) MY135942A (en)
NO (1) NO20022792L (en)
TW (1) TW490822B (en)
WO (1) WO2001045167A2 (en)

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CN1409872A (en) 2003-04-09
KR20020059851A (en) 2002-07-13
CA2392837A1 (en) 2001-06-21
NO20022792D0 (en) 2002-06-12
WO2001045167A2 (en) 2001-06-21
CN1217410C (en) 2005-08-31
NO20022792L (en) 2002-06-12
US6388335B1 (en) 2002-05-14
US6413799B1 (en) 2002-07-02
MY135942A (en) 2008-07-31
TW490822B (en) 2002-06-11
EP1238427A2 (en) 2002-09-11

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