WO2001048921A1 - Reference voltage distribution for multiload i/o systems - Google Patents
Reference voltage distribution for multiload i/o systems Download PDFInfo
- Publication number
- WO2001048921A1 WO2001048921A1 PCT/US2000/030578 US0030578W WO0148921A1 WO 2001048921 A1 WO2001048921 A1 WO 2001048921A1 US 0030578 W US0030578 W US 0030578W WO 0148921 A1 WO0148921 A1 WO 0148921A1
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- WO
- WIPO (PCT)
- Prior art keywords
- reference voltage
- circuit
- driver
- noise
- line
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/4013—Management of data rate on the bus
Definitions
- the present invention pertains to the field of receivers More particularly, the present invention pertains to reference voltage distribution for multiload input/output (i/o) systems.
- Determination of the state or logic level of a signal (high or low) in digital signaling requires the signal to be compared to a reference state
- the signal can be a voltage level, and it can be compared to a reference voltage to determine if the signal is high or low
- Providing a reference voltage line which has a reference voltage that tracks noise in a manner similar to the data lines is helpful for achieving high data rates on today's high performance buses Tracking allows common mode noise refection at the receiver thereby improving the noise margin
- the reference voltage and the data voltages do not track the noise in a similar manner the amount of time needed for the data signal to clearly cross the reference voltage changes The amount of time needed for the data signal to clearly cross the reference voltage can vary from one bit to another However, the worst case time needed for the data signal to clearly cross the reference voltage is used to ensure reliable operation When the worst case time needed for the data signal to cross the reference voltage increases, the frequency of the data signal has to decrease, making the bus operate at a relatively low data rate Consequently, it is beneficial for the noise
- CMOS complementary metal-oxide semiconductor
- CMOS complementary metal-oxide semiconductor
- SBD simultaneous bidirectional signaling technology
- CMOS network 100 includes chip 1 10 and chip 120 Chip 1 10 and chip 120 are coupled by data line 1 15 and reference lines 130 and 140 Chip 1 10 generates a high reference voltage (Vhigh) and a low reference voltage (Vlow) which are driven unto reference lines 130 and 140, respectively Chip 120 also generates a Vhigh and Vlow which are driven unto reference lines 130 and 140 Since both chips 1 10 and 120 continuously and simultaneously generate and distribute the reference voltages the reference voltages are generally well defined at all times
- Chip 1 10 includes driver 1 12, input line 1 1 1 , multiplexer 1 13, receiver 1 14 and high voltage reference d ⁇ ver (high vref d ⁇ ver) 142, and low voltage reference driver (low vref d ⁇ ver) 144
- Chip 120 includes d ⁇ ver 122, input line 121, multiplexer 123, receiver 124 and high voltage reference driver (high vref driver) 146, and low voltage reference driver (low vref driver) 146
- D ⁇ ver 1 12 drives a data signal received on input line 1 1 1 onto line 1 15
- reference voltage generators 142 and 144 are applying Vhigh and Vlow onto lines 1 0 and 140
- reference voltage generators 146 and 148 are also applying Vhigh and Vlow onto lines 130 and 140
- d ⁇ ver 112 also couples noise to line 1 15 By generating Vhigh and Vlow at both chip 1 10 and 120 and applying Vhigh and Vlow to lines 130 and 140, noise in each chip is also coupled
- Receiver 124 receives the signal on line 1 15 and the output of multiplexer 123 Multiplexer 123 either outputs Vhigh or Vlow depending on whether the outbound signal driven is high or low Receiver compares the signal received on line 1 15 with the output multiplexer 123 and outputs a signal indicative of the logic level or state of the signal on line 115 Since noise in line 1 15 substantially tracks the noise in lines 130 and 140, the common mode noise can be rejected at the receiver, improving performance Receiver 1 14 operates in a manner similar to receiver 124 and need not be described in greater detail here While only one data line is shown in network 100, generally multiple data bits share a common Vref pair
- bus technologies besides CMOS SBD technology, each of which has its advantages and which would benefit from pseudo differential voltage reference distribution
- alternative bus technologies include unidirectional, multi-load CMOS, or multi-load open drain (Gunning transistor logic (GTL)) signaling systems Since tracking noise in both the reference voltage and data lines and minimizing drift in the reference voltage l ⁇ ne(s) may have a beneficial effect on performance and noise margin, it is desirable to give the benefits of pseudo differential voltage reference distribution to uni-directional, multi-load CMOS, or Gunning transistor logic (GTL) signaling systems
- a circuit that is to be coupled to a reference voltage line includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a d ⁇ ver is driving a data line
- Figure 1 illustrates a CMOS point-to-point network which has pseudo differential Vref distribution
- FIG. 2 illustrates a multi-load CMOS network for one embodiment in accordance with the present invention
- Figure 3 illustrates a multi-load parallel terminated network for one embodiment in accordance with the present invention
- Figure 4 illustrates a multi-load parallel terminated network for an alternative embodiment in accordance with the present invention.
- Figure 5 illustrates a multi-load parallel terminated network for yet another embodiment in accordance with the present invention.
- Figure 6 illustrates a multi-load parallel terminated network for an alternative embodiment in accordance with the present invention.
- Figure 7 illustrates a multi-load parallel terminated network for yet another embodiment in accordance with the present invention.
- Network 200 includes three separate integrated circuit 250, 260, and 270, each of which has a data driver, a receiver, a reference voltage driver, and a reference keeper
- Integrated circuit 250 includes data driver 205, receiver 235, reference voltage driver 220, and reference keeper 221
- Integrated circuit 260 includes data driver 210, receiver 240, reference voltage driver 225, and reference keeper 226.
- Integrated circuit 270 includes data driver 215, receiver 245, reference voltage driver 230, and reference keeper 231
- Data driver 205 and reference voltage driver 220 are grouped together as a pair
- data driver 210 and reference voltage driver 225 are grouped together as a pair
- data driver 215 and reference voltage driver 230 are grouped together as a pair
- data driver 205 and reference voltage driver 220 drive lines 201 and 202, respectively, at the same time While the data driver of a chip/pair is driving the data line, the data driver allows noise to couple to the data line The noise will affect the logic and voltage levels on the data line.
- the reference voltage driver of the pair also permits noise to be coupled to the reference voltage line Consequently, the noise on reference voltage line 202 substantially tracks the noise on data line 201
- the tracking of the noise on lines 201 and 202 helps maintain the margins between the data line and the reference voltage line, allowing better timing and noise margin for some embodiments in accordance with the present invention
- reference keepers 221, 226, and 231 drive reference line 202 so as to maintain a predetermined reference voltage level
- Reference keepers 221, 226, 231 prevent line 202 from drifting when none of drivers 220-230 are driving reference line 202 or when there is a changeover from one driver to another driver
- Changeover form one driver to another driver is also referred to as master changeover
- the reference keeper is a high impedance leaker which is sufficient to maintain reference voltages during changeover
- the reference voltage line(s) can be left floating for a few bus cycles because there is only a small leakage current during changeover
- network 200 only included one data line and one reference voltage line, it should be appreciated that the scope and spirit of the present invention encompass alternative embodiments having different data line to reference voltage line ratios
- alternative embodiments may have two or more data lines for each reference voltage line
- alternative embodiments may have conventional discrete element circuits instead of integrated circuits coupled to the data line(s) and the reference voltage line(s)
- only one of the integrated circuits or discrete element circuits may have a reference keeper to maintain the reference voltage on the reference voltage line
- Yet other alternative embodiments may have at least one external reference keeper which is separate from the integrated circuits or discrete element circuits
- the external reference keeper is coupled to the reference voltage line and continuously drives the reference voltage line
- Yet other alternative embodiments may have no external reference keeper Rather, a reference keeper in an integrated circuit or a discrete element circuit will drive the reference line within a predetermined period of time after all drivers or bus agents stop driving the data line(s)
- a parallel terminated network has resistors at each end of a reference voltage line and resistors at each end of the data line
- the termination resistors serve the purpose of absorbing a bounce in the reference voltage signal to present reflections when the bounce reaches the end of the reference voltage line
- the data line termination resistors serve the purpose of absorbing a signal that travels down the data line to prevent reflections
- a parallel terminated network is preferable to a series terminated network because the intended logic level of a data signal is communicated to all receivers along the data line during the first pass of the signal down the line.
- a parallel terminated bus driver's pull-up impedance should be substantially equal to the driver's pull-down impedance (Rdn)
- Figure 3 illustrates a parallel terminated network for an embodiment in accordance with the present invention
- Network 300 can be implemented with GTL technology
- other bus technologies suitable for parallel terminated networks may also be used
- Network 300 includes three separate integrated circuits 350, 360, and 370, each of which has a data driver, a receiver
- Integrated circuit 370 includes data driver 315, receiver 345, and reference voltage driver 330
- Data driver 305 and reference voltage driver 320 are grouped together as a pair
- data driver 310 and reference voltage driver 325 are grouped together as a pair
- data driver 315 and reference voltage driver 330 are grouped together as a pair
- Network 300 also includes data line 301.
- reference voltage line 302, reference line termination 307-308, and data line termination resistors 303- 304 When the data driver of a pair drives data line 301 the reference voltage driver of the pair also drives reference voltage line 302 with a reference voltage
- the reference voltage driver of the pair also behaves as a noise coupling circuit by coupling noise in the integrated circuit to the reference voltage line
- network 300 only included one data line and one reference voltage line, it should be appreciated that the scope and spirit of the present invention encompass alternative embodiments having different data line and reference voltage line ratios
- alternative embodiments may have two or more data lines for each reference voltage line
- alternative embodiments may have conventional discrete element circuits instead of integrated circuits coupled to the data l ⁇ ne(s) and the reference voltage l ⁇ ne(s)
- Data driver 305 and reference driver 320 are paired together and drive lines 301 and 302, respectively, at the same time
- the remaining pairs do not drive the lines
- a signal applied by a data d ⁇ ver onto line 301 travels the length of line 301
- resistances 303 and 304 at the ends of the data line serve the purpose of absorbing a signal that travels down the data line to prevent reflections
- resistances 307-308 serve the same purpose of absorbing a noise bounce in the voltage reference signal on line 302, but they also allow the voltage reference line to be matched to the data line Due to these termination resistances, network 300 is preferable to a series terminated network because the intended logic level of a data signal is communicated to all receivers along the data line during the first pass of the signal down the line In a series terminated network, on the other hand, the data signal has to travel to the end of the line and reflect back before a receiver along the
- Receivers 333-345 compare the signal on lines 302 and 301 and generate a signal indicative of the logic level of the signal on line 301
- the ability of receivers to properly decode the signal depends on network 300 providing a predetermined reference voltage (Vref) on line 302 as well as a common mode noise tracking between the reference voltage line and the data line
- Vref reference voltage
- the timing at the receivers 335-345 can affect performance on the bus
- the reference voltage line is substantially similar to the data line so that noise couples substantially equally and in a similar manner to both lines
- the noise that couples to the reference line is substantially in phase with and has substantially equal magnitude to the noise on the data line
- a predetermined margin between the data signal and the reference voltage can be maintained more easily which may lead to better signal recovery and improved performance, such as higher data rates on the data lines
- the reference voltage and data lines to be substantially similar, in one embodiment the
- Vtt is the voltage applied to the reference line termination resistors
- FIG. 4 illustrates a parallel terminated network in accordance with an alternative embodiment of the present invention
- Network 400 includes three separate integrated circuits 450, 460, and 470, each of which has a data driver, a receiver, and a reference voltage driver
- Integrated circuit 450 includes data driver 405, receiver 435, and reference voltage driver 420
- Integrated circuit 460 includes data driver 410, receiver 440, and reference voltage driver 425.
- Integrated circuit 470 includes data driver 415, receiver 445, and reference voltage driver 430
- Data driver 405 and reference voltage driver 420 are grouped together as a pair
- data driver 410 and reference voltage driver 425 are grouped together as a pair
- data driver 415 and reference voltage driver 430 are grouped together as a pair
- Network 400 also includes data line 401 , reference voltage line 402, reference line termination up resistors 407u-408u, reference line termination down resistors 407d-408d, and data line termination up resistors 403-404.
- the reference voltage driver of the pair drives data line 401
- the reference voltage driver of the pair also drives reference voltage line 402 with a reference voltage.
- the reference voltage driver of the pair also behaves as a noise coupling circuit by coupling noise in the integrated circuit to the reference voltage line.
- network 400 only included one data line and one reference voltage line, it should be appreciated that the scope and spirit of the present invention encompass alternative embodiments having different data line and reference voltage line ratios.
- alternative embodiments may have two or more data lines for each reference voltage line.
- alternative embodiments may have conventional discrete element circuits instead of integrated circuits coupled to the data line(s) and the reference voltage line(s).
- the three pairs of a data driver and a reference voltage driver operate in a manner similar to the driver pairs described in connection with network 300. and their operation need not be described further, here.
- a pair of a data driver and a reference voltage driver when a pair of a data driver and a reference voltage driver are driving lines 4 1 and 402. the remaining pairs do not drive the lines.
- the two pairs may drives the lines simultaneously.
- a signal applied by a data driver onto line 401 travels the length of line 401.
- resistors 403 and 404 at the ends of the data line serve the purpose of absorbing a signal that travels down the data line to prevent reflections.
- resistors 407u, 407d, 408u, and 408d serve the purpose of absorbing a noise bounce in the voltage reference signal on line 402 when the bounce reaches the end of a voltage reference line, in order to prevent reflections.
- Network 400 is preferable to a series terminated network because the intended logic level of a data signal is communicated to all receivers along the data line during the first pass of the signal down the data line.
- Receivers 435-445 compare the signal on lines 402 and 401 and generate a signal indicative of the logic level of the signal on line 401 .
- the ability of receivers to properly decode the signal depends on network 400 providing a predetermined reference voltage (Vref) on line 402 as well as common mode noise tracking between the data line and the reference voltage line.
- Vref reference voltage
- the timing at the receivers 435-445 can affect performance on the bus.
- the reference voltage line is substantially similar to the data line so that noise couples substantially equally and in a similar manner to both lines.
- the noise that couples to the reference line has a phase and magnitude that is substantially equal to that of the noise on the data line.
- a predetermined margin between the data signal and the reference voltage can be maintained more easily which may lead to better signal recovery and improved performance, such as higher data rates on the lines.
- the lines have substantially equivalent lengths and impedances, corresponding termination resistors with substantially equivalent values, and corresponding drivers attached to the lines with substantially equivalent impedances. Consequently, the material, length, and cross- sections, among other characteristics of lines 401 and 402 are substantially similar in one embodiment.
- Resistor 403 has substantially the same resistance, Rtt, as resistors 407u and 407d in parallel.
- resistor 404 has substantially the same resistance. Rtt, as resistors 408u and 408d in parallel.
- the relationship between the termination resistors on lines 401 and 402 is described by the following expression: Rttup
- each of reference voltage drivers 420-430 is substantially equal to the impedance of each of data drivers 405-415.
- data drivers 405-415 have a pull-up impedance equal to Rup' when a rising edge signal is being driven onto line 401 and a pull-down impedance equal to Rdn' when a falling edge signal is being driven onto line 401.
- Rup' is equal to Rdn'.
- the parallel combination of Rup" and Rdn" of each of drivers 420-430. in one embodiment should be substantially equal to Rup' or Rdn' of drivers 405-415.
- Rup" 421 in parallel with Rdn" 422 should be substantially equal to Rup' or Rdn'.
- the relationship between Rup" and Rdn", on the one hand, and Rup' and Rdn'. on the other hand, is described by the following expression: Rup"
- the reference voltage at the output of a reference voltage driver is related to the voltage supplied to the reference voltage driver.
- Rup and Rdn" is described by the following equation: Vtt* Rdn"/(Rup” + Rdn” ) * Vref
- the value of the reference voltage on line 402 is related to the voltage (Vtt) applied to resistors 407u and 408u as described by the following expression
- line 402 will remain at Vref because of the voltage generated due to resistor pair 407u and 407d, and resistor pair 408u and 408d While in one embodiment there is current flow through termination resistors in an alternate embodiment of the present invention there is less current flow through the termination resistors In line 402 there is insubstantial DC cu ⁇ ent flow because the on-chip Vref generator and the termination resistor pair are all set to Vref Therefore, if a Vref generator is switched off the Vref remains at the same DC level and does not drift.
- Figure 5 illustrates a parallel terminated network for an alternative embodiment in accordance with the present invention
- Network 500 includes three separate integrated circuits 550, 560, and 570, each of which has a data driver, a receiver, and a reference voltage driver
- Network 500 includes data drivers 505, 510, and 515, reference voltage drivers 520-530, data line 501 , reference voltage line (reference line) 502, data line termination resistors 503 and 504, reference line termination resistors 507 and 508, and receivers 535-545
- Network 500 operates and is made in a manner similar to network 400 and need not be described in greater detail, here
- the reference voltage drivers behave as a noise coupling circuit by coupling noise in an integrated circuit to the reference voltage line
- network 500 only included one data line and one reference voltage line, it should be appreciated that the scope and spirit of the present invention encompass alternative embodiments having different data line to reference voltage line ratios
- alternative embodiments may have two or more data lines for each reference voltage line
- alternative embodiments may have conventional discrete element circuits instead of integrated circuits coupled to the data line(s) and the reference voltage line(s)
- Network 600 includes three separate integrated circuits 650, 660, and 670, each of which has a data driver, a receiver, and a noise coupling circuit.
- Network 600 includes data drivers 605, 610, and 615, noise coupling circuits 620-630, data line 601, reference voltage line (reference line) 602, data line termination resistors 603 and 604, reference line termination resistors 607 and 608, and receivers 635-545
- Network 600 operates and is made in a manner similar to network 500 and need not be described in greater detail, here
- network 600 instead of having reference voltage drivers that generate a reference voltage and couple noise from each integrated circuit to the reference voltage line, network 600 includes noise coupling circuits that couple noise to the reference voltage line from the integrated circuits that are driving the data line
- Noise coupling circuit 620 includes a resistor Rdn" 622 which substantially matches Rup' and Rdn' of driver 605
- Circuit 620 includes a capacitor 621 which couples Rdn" 622 to reference line 602
- the noise in circuit 620 is coupled to reference line 602 when switch 623 is closed and driver 605 is driving data line 601
- the capacitor needs to be sized such that it allows the lowest frequency noise of interest to couple through Noise coupling circuits 625 and 630 operate in a similar manner to circuit 620 and need not be desc ⁇ bed in greater detail
- the reference voltage is supplied to reference line 602 by applying a voltage substantially equal to Vref to the termination resistors Line 602 will substantially remain at Vref due to the voltage applied to the termination resistors but will also reflect the noise in each of the integrated circuits 650, 660, and 670 when the noise circuits 620, 625, and 630, respectively, couple the noise of each integrated circuit to reference line 602
- network 600 only included one data line and one reference voltage line, it should be appreciated that the scope and spirit of the present invention encompass alternative embodiments having different data line and reference voltage line ratios
- alternative embodiments may have two or more data lines for each reference voltage line
- alternative embodiments may have conventional discrete element circuits instead of integrated circuits coupled to the data l ⁇ ne(s) and the reference voltage l ⁇ ne(s)
- Figure 7 illustrates a parallel terminated network for an alternative embodiment in accordance with the present invention
- Network 700 includes three separate integrated circuits 750, 760, and 770 each of which has a data driver a receiver, and a noise coupling circuit
- Network 700 includes data drivers 705, 710 and 715, noise coupling circuits 720-730, data line 701 , reference voltage line (reference line) 702 data line termination resistors 703 and 704, reference line termination resistors 707 and 708, and receivers 735-745
- Network 700 operates and is made in a manner similar to network 600 and need not be described in greater detail here Salient differences between network 700 and network 600 will now be described For example, instead of placing a resistor and switch in the noise coupling circuit which substantially matches Rup' and Rdn' of the data driver the noise coupling circuit includes a driver that is substantially similar to the data driver but which is always driven with a constant (high or low) input such that the driver is consistently pulling one end of the capacitor towards (high or low) rail with an im
- the reference voltage is supplied to reference line 702 by applying a voltage substantially equal to Vref to the termination resistors
- Line 702 will substantially remain at Vref due to the voltage applied to the termination resistors but will also reflect the noise in each of the integrated circuits 750, 760, and 770 when the noise circuits 720, 725, and 730, respectively, couple the noise of each integrated circuit to reference line 702
- network 700 only included one data line and one reference voltage line, it should be appreciated that the scope and spirit of the present invention encompass alternative embodiments having different data line and reference voltage line ratios
- alternative embodiments may have two or more data lines for each reference voltage line
- alternative embodiments may have conventional discrete element circuits instead of integrated circuits coupled to the data hne(s) and the reference voltage l ⁇ ne(s)
- Vref drivers can be replaced by either the noise coupling circuits of network 600 of Figure 6 or the noise coupling circuits of network 700 of Figure 7.
- driver 220 can be replaced by either noise coupling circuit 620 or noise coupling circuit 720.
- the Vref drivers can be replaced by either the noise coupling circuits of network 600 or the noise coupling circuits of network 700.
- driver 420 can be replaced by noise coupling circuit 620 or noise coupling circuit 720.
- Vref drivers can be replaced by either the noise coupling circuits of network 600 or the noise coupling circuits of network 700.
- driver 520 can be replaced by noise coupling circuit 620 or noise coupling circuit 720.
- Noise coupling circuits are defined herein to cover both the Vref drivers of Figures 2, 3, 4, and 5, which couple noise as well as generate reference voltages, and the noise coupling circuits which substantially only couple noise.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0213018A GB2373152B (en) | 1999-12-23 | 2000-11-07 | Reference voltage distribution for multiload I/O systems |
AU14704/01A AU1470401A (en) | 1999-12-23 | 2000-11-07 | Reference voltage distribution for multiload i/o systems |
DE10085350T DE10085350B3 (en) | 1999-12-23 | 2000-11-07 | Reference voltage distribution for multi-load I / O systems |
HK02107147.5A HK1045610B (en) | 1999-12-23 | 2002-09-27 | Reference voltage distribution for multiload i/o systems |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/470,686 US6453422B1 (en) | 1999-12-23 | 1999-12-23 | Reference voltage distribution for multiload i/o systems |
US09/470,686 | 1999-12-23 |
Publications (1)
Publication Number | Publication Date |
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WO2001048921A1 true WO2001048921A1 (en) | 2001-07-05 |
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ID=23868608
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/030578 WO2001048921A1 (en) | 1999-12-23 | 2000-11-07 | Reference voltage distribution for multiload i/o systems |
Country Status (6)
Country | Link |
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US (2) | US6453422B1 (en) |
AU (1) | AU1470401A (en) |
DE (1) | DE10085350B3 (en) |
GB (1) | GB2373152B (en) |
HK (1) | HK1045610B (en) |
WO (1) | WO2001048921A1 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6697896B1 (en) * | 1999-12-31 | 2004-02-24 | Intel Corporation | Method and apparatus for implementing high speed signals using differential reference signals |
US6738415B2 (en) * | 2001-03-22 | 2004-05-18 | Sun Microsystems, Inc. | Bi-directional communication system |
JP2002351588A (en) * | 2001-05-30 | 2002-12-06 | Hitachi Ltd | Signal receiving circuit, semiconductor device and system |
US7177288B2 (en) * | 2001-11-28 | 2007-02-13 | Intel Corporation | Simultaneous transmission and reception of signals in different frequency bands over a bus line |
US6906531B2 (en) * | 2002-10-11 | 2005-06-14 | Dell Products L.P. | Adaptive reference voltage method and system |
JP4593915B2 (en) * | 2002-12-31 | 2010-12-08 | 三星電子株式会社 | Simultaneous bidirectional input / output circuit and method |
US6891406B2 (en) * | 2003-01-09 | 2005-05-10 | International Business Machines Corporation | Method and apparatus for supplying a reference voltage for chip-to-chip communication |
US7155352B2 (en) * | 2003-12-31 | 2006-12-26 | Intel Corporation | Using feedback to select transmitting voltage |
KR100687923B1 (en) * | 2005-04-29 | 2007-02-27 | 삼성전자주식회사 | Master device, control method thereof and electronic apparatus having master device |
US7710188B1 (en) | 2006-01-13 | 2010-05-04 | Marvell International Ltd. | Low-noise, temperature-insensitive, voltage or current input, analog front end architecture |
JP2008042376A (en) * | 2006-08-03 | 2008-02-21 | Fujitsu Ltd | Bi-directional transmission circuit and transceiver element |
US8179161B1 (en) | 2009-05-05 | 2012-05-15 | Cypress Semiconductor Corporation | Programmable input/output circuit |
US8487655B1 (en) | 2009-05-05 | 2013-07-16 | Cypress Semiconductor Corporation | Combined analog architecture and functionality in a mixed-signal array |
US9612987B2 (en) | 2009-05-09 | 2017-04-04 | Cypress Semiconductor Corporation | Dynamically reconfigurable analog routing circuits and methods for system on a chip |
EP3217291B1 (en) * | 2016-03-11 | 2020-06-17 | Socionext Inc. | Integrated circuitry systems |
US10599590B2 (en) | 2016-11-30 | 2020-03-24 | International Business Machines Corporation | Uniform memory access architecture |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5247209A (en) * | 1992-05-12 | 1993-09-21 | Acer Incorporated | Supply independent constant output circuit having fast stabilization |
US5483110A (en) * | 1993-03-19 | 1996-01-09 | Hitachi, Ltd. | Signal transmission method, signal transmission circuit and information processing system using same |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5023488A (en) * | 1990-03-30 | 1991-06-11 | Xerox Corporation | Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines |
GB9007793D0 (en) * | 1990-04-06 | 1990-06-06 | Foss Richard C | Dram cell plate and precharge voltage generator |
US5355391A (en) * | 1992-03-06 | 1994-10-11 | Rambus, Inc. | High speed bus system |
US5371424A (en) * | 1992-11-25 | 1994-12-06 | Motorola, Inc. | Transmitter/receiver circuit and method therefor |
US5550496A (en) * | 1995-07-31 | 1996-08-27 | Hewlett-Packard Company | High speed I/O circuit having a small voltage swing and low power dissipation for high I/O count applications |
US6011419A (en) * | 1997-08-05 | 2000-01-04 | International Business Machines Corporation | Decoupling scheme for mixed voltage integrated circuits |
US6201572B1 (en) * | 1998-02-02 | 2001-03-13 | Agilent Technologies, Inc. | Analog current mode assisted differential to single-ended read-out channel operable with an active pixel sensor |
US6195395B1 (en) * | 1998-03-18 | 2001-02-27 | Intel Corporation | Multi-agent pseudo-differential signaling scheme |
US6184717B1 (en) * | 1998-12-09 | 2001-02-06 | Nortel Networks Limited | Digital signal transmitter and receiver using source based reference logic levels |
US6226205B1 (en) * | 1999-02-22 | 2001-05-01 | Stmicroelectronics, Inc. | Reference voltage generator for an integrated circuit such as a dynamic random access memory (DRAM) |
US6133799A (en) * | 1999-02-25 | 2000-10-17 | International Business Machines Corporation | Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS |
US6320438B1 (en) * | 2000-08-17 | 2001-11-20 | Pericom Semiconductor Corp. | Duty-cycle correction driver with dual-filter feedback loop |
-
1999
- 1999-12-23 US US09/470,686 patent/US6453422B1/en not_active Expired - Lifetime
-
2000
- 2000-11-07 DE DE10085350T patent/DE10085350B3/en not_active Expired - Fee Related
- 2000-11-07 WO PCT/US2000/030578 patent/WO2001048921A1/en active Application Filing
- 2000-11-07 GB GB0213018A patent/GB2373152B/en not_active Expired - Fee Related
- 2000-11-07 AU AU14704/01A patent/AU1470401A/en not_active Abandoned
-
2002
- 2002-04-29 US US10/136,011 patent/US6594769B2/en not_active Expired - Lifetime
- 2002-09-27 HK HK02107147.5A patent/HK1045610B/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5247209A (en) * | 1992-05-12 | 1993-09-21 | Acer Incorporated | Supply independent constant output circuit having fast stabilization |
US5483110A (en) * | 1993-03-19 | 1996-01-09 | Hitachi, Ltd. | Signal transmission method, signal transmission circuit and information processing system using same |
Also Published As
Publication number | Publication date |
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GB0213018D0 (en) | 2002-07-17 |
US6594769B2 (en) | 2003-07-15 |
US6453422B1 (en) | 2002-09-17 |
GB2373152A (en) | 2002-09-11 |
AU1470401A (en) | 2001-07-09 |
DE10085350B3 (en) | 2013-09-12 |
US20020151288A1 (en) | 2002-10-17 |
HK1045610B (en) | 2005-05-06 |
HK1045610A1 (en) | 2002-11-29 |
GB2373152B (en) | 2004-09-08 |
DE10085350T1 (en) | 2002-12-05 |
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