WO2001050504A2 - An improved method for buried anti-reflective coating removal - Google Patents

An improved method for buried anti-reflective coating removal Download PDF

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Publication number
WO2001050504A2
WO2001050504A2 PCT/US2000/035130 US0035130W WO0150504A2 WO 2001050504 A2 WO2001050504 A2 WO 2001050504A2 US 0035130 W US0035130 W US 0035130W WO 0150504 A2 WO0150504 A2 WO 0150504A2
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WO
WIPO (PCT)
Prior art keywords
gate region
reflective coating
spacers
layer
gate
Prior art date
Application number
PCT/US2000/035130
Other languages
French (fr)
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WO2001050504A3 (en
Inventor
Mark W. Haley
Delbert Parks
Original Assignee
Koninklijke Philips Electronics N.V.
Philips Semiconductors, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V., Philips Semiconductors, Inc. filed Critical Koninklijke Philips Electronics N.V.
Priority to JP2001550784A priority Critical patent/JP2003519910A/en
Priority to EP00986719A priority patent/EP1188179A2/en
Publication of WO2001050504A2 publication Critical patent/WO2001050504A2/en
Publication of WO2001050504A3 publication Critical patent/WO2001050504A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • the present invention is generally directed to semiconductor structures using anti-reflective coatings to aid in the photolithography process as well as semiconductor structures utilizing spacers adjacent the gate regions for forming source and drain regions.
  • NVM nonvolatile memory
  • DRAM dynamic random access memory
  • peripheral circuits on these devices are typically composed of logic circuits for addressing the memory cells, while other peripheral circuits function as read/write buffers and sense amplifiers.
  • Amorphous silicon deposition eliminates the replication of underlying isolation topography in the polysilicon surface.
  • amorphous silicon deposition has problems with deposition defects and is also more difficult to fully dope.
  • Another technique for improving linewidth control involves the use of anti- reflective layers as part of the photolithographic process.
  • the use of anti-reflective layers reduces the effects of both the surface roughness caused by the grain structure of polysilicon and the resist thickness variation due to the underlying effects caused by the rough surface and the topographical features of the polysilicon layer.
  • the addition of an anti-reflective layer also helps to planarize the isolation topography and reduce the variation of the photoresist thickness over the substrate.
  • the benefits of using anti- reflective coatings (ARC) can be lost if the coatings can not be totally and easily removed prior to suicide formation (contact formation), since the use of ARCs already require special processing equipment and can add additional steps a manufacturing process.
  • BARC buried anti-reflective coating
  • Oxide spacers may also be included as part of the device's structure, the formation of which tend to complicate the BARC removal process. Removal of the BARC film during spacer etching has led to narrow spacer profiles and excessive isolation oxide loss. Overetching of the oxide spacer layer has been attempted to solve the problem of incomplete BARC removal, but this has led to degradation of the device's structure and performance.
  • a two step etching process is used to remove substantially all of an anti-reflective coating from a gate region while minimizing the dielectric spacer loss along side the gate. Minimizing spacer oxide loss along side the gate, in turn, provides protection to the gate edge during the silicidation which prevents notching at the top of the gate.
  • An example embodiment of the present invention is directed to a method for manufacturing a semiconductor structure, having a substrate and a gate region thereon, which includes removing an anti-reflective coating (ARC) layer over the gate region to improve silicidation of the gate.
  • An anti-reflective coating is first formed over the gate region.
  • a dielectric layer is formed over the anti-reflective coating layer, the gate region and the substrate.
  • Dielectric spacers are then formed on the substrate, adjacent the gate region and the anti-reflective coating layer, by etching the dielectric layer using a first process that includes selectively removing portions of the dielectric layer on the anti- reflective coating. Utilizing a second, different etching process, the anti-reflective coating over the gate region is selectively removed while preserving the spacers adjacent the gate region.
  • Another example embodiment of the present invention is directed to a method for manufacturing a semiconductor structure, having a substrate and a gate region thereon, which includes the removal of an anti-reflective coating (ARC) layer over the gate region to improve silicidation of the gate.
  • the method includes providing an buried anti-reflective coating over the gate region and providing an oxide layer over the buried anti-reflective coating layer, the gate region and the substrate.
  • Oxide spacers are formed on the substrate, adjacent the gate region and the anti-reflective coating layer, by using a first process to substantially simultaneously etch the oxide layer to form the spacers and to remove the oxide on the anti-reflective coating.
  • an endpoint is utilized to terminate the first process once the oxide over the anti-reflective coating is removed.
  • a second, different etching process is then used that selectively removes the anti- reflective coating over the gate region while preserving the oxide spacers adjacent the gate region; the spacers and gate region therein forming an aperture for receiving a suicide.
  • Another example embodiment of the present invention is directed to a method for manufacturing a semiconductor structure, having a substrate and a gate region thereon, that includes removing an anti-reflective coating (ARC) layer over the gate region to improve silicidation of the gate.
  • the method includes providing a silicon oxynitride coating over an amorphous silicon gate region and providing a silicon dioxide layer over the silicon oxynitride coating layer, the gate region and the substrate.
  • Oxide spacers are then formed on the substrate, adjacent the gate region and the silicon oxynitride coating layer, by using a first process to substantially simultaneously etch the silicon dioxide layer and to remove the silicon dioxide that is disposed on the silicon oxynitride coating.
  • An endpoint is utilized to terminate the first process once the silicon dioxide is removed and a second, different etching process, is utilized thereafter that selectively removes the silicon oxynitride coating over the gate region while preserving the silicon dioxide spacers adjacent the gate region.
  • FIGS. 1A illustrates the first step of an example embodiment for making a semiconductor structure wherein the oxide layer is etched to form oxide spacers.
  • FIGS. IB illustrates the example embodiment semiconductor structure after the first etching step according to the teachings of the present invention.
  • FIGS. 1C illustrates another step of an example embodiment for making a semiconductor structure wherein the ARC is etched from the gate region.
  • FIGS. ID illustrates the example embodiment for making a semiconductor structure after another etching step according to the teachings of the present invention.
  • the present invention is believed to be applicable to a variety of MOS devices and semiconductor structures that utilize spacers as part of their structure or in their manufacturing process.
  • the teachings of the present invention are believed to be applicable in the area of anti-reflective coating removal procedures prior to salicidation of a semiconductor device.
  • a two step etching process is used to substantially remove all of an anti-reflective coating from a gate region while minimizing the dielectric spacer loss along side the gate. Minimizing spacer oxide loss along side the gate, in turn, provides protection to the gate edge during the silicidation which prevents notching at the top of the gate. While the present invention is not necessarily so limited, an appreciation of various aspects of the invention is best gained through a discussion of various example semiconductor structures described below.
  • a method for manufacturing a semiconductor structure having a substrate and a gate region thereon involves the removal of an anti-reflective coating (ARC) layer over the gate region to improve silicidation of the gate.
  • the method includes providing an anti-reflective coating over the gate region and providing a dielectric layer over the anti-reflective coating layer, the gate region and the substrate.
  • Dielectric spacers are then formed on the substrate, adjacent the gate region and the anti-reflective coating layer, by etching the dielectric layer using a first process that includes selectively removing portions of the dielectric layer on the anti-reflective coating. Utilizing a second, different etching process, the anti-reflective coating over the gate region is selectively removed while preserving the spacers adjacent the gate region.
  • Figure 1A shows a semiconductor structure having a substrate 10 with a gate region 12 disposed thereon.
  • the gate region is made of amorphous silicon (ASi), but could be made of other compatible semiconductor materials used in the formation of gate regions.
  • BARC buried anti-reflective coating
  • a dielectric layer 16 is then disposed on the entire structure, which can be an oxide type material such as silicon dioxide (SiO 2 ).
  • the semiconductor structure is then subjected to a first etching process step, as shown by arrows 18, wherein portions of dielectric layer 16 are primarily etched off.
  • the first process step of a dielectric (oxide) spacer etch process will remove the BARC over the amorphous silicon and should utilize a common oxide etch chemistry such as CF4 or a mix of CHF 3 /CF 4 and possibly an inert gas such as argon or helium. This step should remove all of the oxide being selective to silicon and may involve using an endpoint to terminate the etch process step once the oxide is removed.
  • Figure IB illustrates the semiconductor structure after the first etching process; this figure also illustrates formation of oxide spacers 16A and 16B adjacent gate region 12 and that bound BARC layer 14.
  • the semiconductor structure is then subjected to the second etching process, as illustrated by arrows 20, that utilizes either a CF 4 or CHF 3 with an oxygen additive to provide selectivity to the oxide material relative to the SiON (BARC) layer 14.
  • the etching process can be performed in either a 4520 or 4520XL using similar chamber configurations and chemistry. This method will maintain the dielectric spacer profile (16A, 16B) and minimize isolation oxide loss while ensuring complete BARC removal.
  • Figure ID illustrates the semiconductor structure resulting from the second etching process and illustrates that oxide spacers 16A and 16B have remained substantially intact adjacent gate region 12.
  • Spacers 16A and 16B, along with gate region 12 now form an aperture 22 for receiving suicide during the silicidation (contact formation) process.
  • oxide loss is minimized in the two-step spacer etch process where the first step is a traditional oxide etch and the second step is highly selective to oxide while etching the BARC over the ASi gates. Complete BARC removal is imperative for good suicide formation on the amorphous silicon gate region. Without selectivity to the oxide material in the BARC removal process (second etch process) spacers 16A andl ⁇ B widths become too small and the result is gate to source/drain leakage. In addition, notching may occur along side the amorphous silicon gate where spacer etching is excessive and has exposed this edge.
  • Leaving oxide on the gate top edge assures uniform suicide formation on top of the gate.
  • the present invention is applicable to a number of different semiconductor structures and processes. Accordingly, the present invention should not be considered limited to the particular examples described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent structures, as well as numerous structures to which the present invention may be applicable will be readily apparent to those of skill in the art upon review of the present specification. The claims are intended to cover such modifications and devices.

Abstract

A method for manufacturing a semiconductor structure, having a substrate and a gate region thereon, is described that includes removing an anti-reflective coating (ARC) layer over the gate region to improve salicidation of the gate. An anti-reflective coating is formed over the gate region and then a dielectric layer is formed over the anti-reflective coating layer and the substrate. Dielectric spacers are then formed on the substrate, adjacent the gate region and the anti-reflective coating layer, by etching the dielectric layer using a first process that includes selectively removing portions of the dielectric layer on the anti-reflective coating. Utilizing a second, different etching process, the anti-reflective coating over the gate region is selectively removed while preserving the spacers adjacent the gate region. Use of the present invention helps to minimize the dielectric spacer loss along side the gate region during removal of the buried anti-reflective coating, thereby providing a protection to the gate edge during the salicidation.

Description

AN IMPROVED METHOD FOR BURIED ANTI-REFLECTIVE COATING
REMOVAL
Field of the Invention
The present invention is generally directed to semiconductor structures using anti-reflective coatings to aid in the photolithography process as well as semiconductor structures utilizing spacers adjacent the gate regions for forming source and drain regions.
Background of the Invention
Tremendous advances in semiconductor technology have permitted dramatic increases in circuit density and complexity with equally dramatic decreases in power consumption and package sizes. Single-chip microprocessors with millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second), are packaged in relatively small, air-cooled semiconductor device packages. Many of the integrated circuits formed on semiconductor substrates are comprised of several circuit functions now all integrated on the single chip. For example, nonvolatile memory (NVM) devices, such as DRAMs (dynamic random access memory), are composed of an array of memory cells for storing digital information. The peripheral circuits on these devices are typically composed of logic circuits for addressing the memory cells, while other peripheral circuits function as read/write buffers and sense amplifiers. Commercially, the drive for increased portability and continuous use, while reducing size and weight, of electronic hand held devices has put more pressure on chip manufacturers to find ways to handle these requirements while reducing the chip size.
The combination of decreasing geometries in chips and the increase in the use of highly reflective materials, such as polysilicon, aluminum and metal silicides has lead to increased photolithographic patterning problems. Unwanted reflections from these underlying reflective materials during the photoresist patterning process often cause the resulting photoresist patterns to be distorted. Further, in order to fabricate high performance MOS transistors it is necessary to control gate electrode linewidths. Improved control of the gate electrode linewidth allows the formation of smaller channel lengths and increases the performance of MOS transistors. Poor photoresist patterning can lead to varying linewidths and to varying gate-lengths, which ultimately lead to variations in the channel length. Consequently, variation of the channel length will alter the electrical characteristics of the MOS device which are supposed to be carefully controlled.
One current technique for improving gate electrode linewidth control in manufacture of MOS transistors involves the use of amorphous silicon deposition. Amorphous silicon deposition eliminates the replication of underlying isolation topography in the polysilicon surface. However, amorphous silicon deposition has problems with deposition defects and is also more difficult to fully dope.
Another technique for improving linewidth control involves the use of anti- reflective layers as part of the photolithographic process. The use of anti-reflective layers reduces the effects of both the surface roughness caused by the grain structure of polysilicon and the resist thickness variation due to the underlying effects caused by the rough surface and the topographical features of the polysilicon layer. The addition of an anti-reflective layer also helps to planarize the isolation topography and reduce the variation of the photoresist thickness over the substrate. The benefits of using anti- reflective coatings (ARC) can be lost if the coatings can not be totally and easily removed prior to suicide formation (contact formation), since the use of ARCs already require special processing equipment and can add additional steps a manufacturing process.
Where a buried anti-reflective coating (BARC) on a gate region is used in manufacturing a semiconductor device, it is necessary to remove all of the BARC prior to proper salicidation of the gate. Incomplete BARC removal causes poor silicide formation on the top of the gate. Oxide spacers may also be included as part of the device's structure, the formation of which tend to complicate the BARC removal process. Removal of the BARC film during spacer etching has led to narrow spacer profiles and excessive isolation oxide loss. Overetching of the oxide spacer layer has been attempted to solve the problem of incomplete BARC removal, but this has led to degradation of the device's structure and performance.
Therefore, there is a need to provide a method for effectively and selectively removing the entire anti-reflective coating on a device prior to suicide formation without substantially disrupting the adjacent insulative structures or the underlying amorphous silicon layer. Further, there is a need for a method of removing the ARC layer that can be easily integrated into the process flow of conventional manufacturing techniques for semiconductor devices.
Summary of the Invention
In the present invention a two step etching process is used to remove substantially all of an anti-reflective coating from a gate region while minimizing the dielectric spacer loss along side the gate. Minimizing spacer oxide loss along side the gate, in turn, provides protection to the gate edge during the silicidation which prevents notching at the top of the gate.
An example embodiment of the present invention is directed to a method for manufacturing a semiconductor structure, having a substrate and a gate region thereon, which includes removing an anti-reflective coating (ARC) layer over the gate region to improve silicidation of the gate. An anti-reflective coating is first formed over the gate region. A dielectric layer is formed over the anti-reflective coating layer, the gate region and the substrate. Dielectric spacers are then formed on the substrate, adjacent the gate region and the anti-reflective coating layer, by etching the dielectric layer using a first process that includes selectively removing portions of the dielectric layer on the anti- reflective coating. Utilizing a second, different etching process, the anti-reflective coating over the gate region is selectively removed while preserving the spacers adjacent the gate region.
Another example embodiment of the present invention is directed to a method for manufacturing a semiconductor structure, having a substrate and a gate region thereon, which includes the removal of an anti-reflective coating (ARC) layer over the gate region to improve silicidation of the gate. The method includes providing an buried anti-reflective coating over the gate region and providing an oxide layer over the buried anti-reflective coating layer, the gate region and the substrate. Oxide spacers are formed on the substrate, adjacent the gate region and the anti-reflective coating layer, by using a first process to substantially simultaneously etch the oxide layer to form the spacers and to remove the oxide on the anti-reflective coating. Next, an endpoint is utilized to terminate the first process once the oxide over the anti-reflective coating is removed. A second, different etching process, is then used that selectively removes the anti- reflective coating over the gate region while preserving the oxide spacers adjacent the gate region; the spacers and gate region therein forming an aperture for receiving a suicide.
Another example embodiment of the present invention is directed to a method for manufacturing a semiconductor structure, having a substrate and a gate region thereon, that includes removing an anti-reflective coating (ARC) layer over the gate region to improve silicidation of the gate. The method includes providing a silicon oxynitride coating over an amorphous silicon gate region and providing a silicon dioxide layer over the silicon oxynitride coating layer, the gate region and the substrate. Oxide spacers are then formed on the substrate, adjacent the gate region and the silicon oxynitride coating layer, by using a first process to substantially simultaneously etch the silicon dioxide layer and to remove the silicon dioxide that is disposed on the silicon oxynitride coating. An endpoint is utilized to terminate the first process once the silicon dioxide is removed and a second, different etching process, is utilized thereafter that selectively removes the silicon oxynitride coating over the gate region while preserving the silicon dioxide spacers adjacent the gate region.
The above summary of the present invention is not intended to describe each possible embodiment or every implementation of the present invention. The figures, and the detailed description that follows, more particularly exemplify these embodiments. Brief Description of the Drawings
The invention may be more completely understood upon consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:
FIGS. 1A illustrates the first step of an example embodiment for making a semiconductor structure wherein the oxide layer is etched to form oxide spacers.
FIGS. IB illustrates the example embodiment semiconductor structure after the first etching step according to the teachings of the present invention. FIGS. 1C illustrates another step of an example embodiment for making a semiconductor structure wherein the ARC is etched from the gate region.
FIGS. ID illustrates the example embodiment for making a semiconductor structure after another etching step according to the teachings of the present invention.
While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Detailed Description
The present invention is believed to be applicable to a variety of MOS devices and semiconductor structures that utilize spacers as part of their structure or in their manufacturing process. The teachings of the present invention are believed to be applicable in the area of anti-reflective coating removal procedures prior to salicidation of a semiconductor device. A two step etching process is used to substantially remove all of an anti-reflective coating from a gate region while minimizing the dielectric spacer loss along side the gate. Minimizing spacer oxide loss along side the gate, in turn, provides protection to the gate edge during the silicidation which prevents notching at the top of the gate. While the present invention is not necessarily so limited, an appreciation of various aspects of the invention is best gained through a discussion of various example semiconductor structures described below. In an example embodiment, a method for manufacturing a semiconductor structure having a substrate and a gate region thereon is disclosed that involves the removal of an anti-reflective coating (ARC) layer over the gate region to improve silicidation of the gate. The method includes providing an anti-reflective coating over the gate region and providing a dielectric layer over the anti-reflective coating layer, the gate region and the substrate. Dielectric spacers are then formed on the substrate, adjacent the gate region and the anti-reflective coating layer, by etching the dielectric layer using a first process that includes selectively removing portions of the dielectric layer on the anti-reflective coating. Utilizing a second, different etching process, the anti-reflective coating over the gate region is selectively removed while preserving the spacers adjacent the gate region.
Referring now to Figures 1A-1D, Figure 1A shows a semiconductor structure having a substrate 10 with a gate region 12 disposed thereon. The gate region is made of amorphous silicon (ASi), but could be made of other compatible semiconductor materials used in the formation of gate regions. On the upper surface of gate region 12 is disposed a layer of buried anti-reflective coating (BARC) 14, which in this example embodiment is silicon oxynitride (SiON). A dielectric layer 16 is then disposed on the entire structure, which can be an oxide type material such as silicon dioxide (SiO2). The semiconductor structure is then subjected to a first etching process step, as shown by arrows 18, wherein portions of dielectric layer 16 are primarily etched off. The first process step of a dielectric (oxide) spacer etch process will remove the BARC over the amorphous silicon and should utilize a common oxide etch chemistry such as CF4 or a mix of CHF3/CF4 and possibly an inert gas such as argon or helium. This step should remove all of the oxide being selective to silicon and may involve using an endpoint to terminate the etch process step once the oxide is removed. Figure IB illustrates the semiconductor structure after the first etching process; this figure also illustrates formation of oxide spacers 16A and 16B adjacent gate region 12 and that bound BARC layer 14.
Referring now to Figure 1C, the semiconductor structure is then subjected to the second etching process, as illustrated by arrows 20, that utilizes either a CF4 or CHF3 with an oxygen additive to provide selectivity to the oxide material relative to the SiON (BARC) layer 14. The etching process can be performed in either a 4520 or 4520XL using similar chamber configurations and chemistry. This method will maintain the dielectric spacer profile (16A, 16B) and minimize isolation oxide loss while ensuring complete BARC removal. Figure ID illustrates the semiconductor structure resulting from the second etching process and illustrates that oxide spacers 16A and 16B have remained substantially intact adjacent gate region 12. Spacers 16A and 16B, along with gate region 12 now form an aperture 22 for receiving suicide during the silicidation (contact formation) process. In this example embodiment, oxide loss is minimized in the two-step spacer etch process where the first step is a traditional oxide etch and the second step is highly selective to oxide while etching the BARC over the ASi gates. Complete BARC removal is imperative for good suicide formation on the amorphous silicon gate region. Without selectivity to the oxide material in the BARC removal process (second etch process) spacers 16A andlόB widths become too small and the result is gate to source/drain leakage. In addition, notching may occur along side the amorphous silicon gate where spacer etching is excessive and has exposed this edge. Leaving oxide on the gate top edge (provided by spacers 16A and 16B - see Figure ID) assures uniform suicide formation on top of the gate. As noted above, the present invention is applicable to a number of different semiconductor structures and processes. Accordingly, the present invention should not be considered limited to the particular examples described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent structures, as well as numerous structures to which the present invention may be applicable will be readily apparent to those of skill in the art upon review of the present specification. The claims are intended to cover such modifications and devices.

Claims

What is claimed is: 1. A method for manufacturing a semiconductor structure having a substrate and a gate region thereon, comprising: providing an anti-reflective coating over the gate region; providing a dielectric layer over the anti-reflective coating layer and the substrate; forming dielectric spacers on the substrate, adjacent the gate region and the anti- reflective coating layer, by etching the dielectric layer using a first process that includes selectively removing portions of the dielectric layer on the anti-reflective coating ; and utilizing a second, different etching process, that selectively removes the anti- reflective coating over the gate region while preserving the spacers adjacent the gate region.
2. The method according to claim 1 , wherein the gate region is made of amorphous silicon (ASi); and wherein the dielectric layer is formed from silicon dioxide (SiO2).
3. The method according to claim 1, further providing an etch chemistry for the first process of CF4 and an inert gas selected from at least one of argon and helium.
4. The method according to claim 1, further providing an etch chemistry for the first process of CHF3/CF4 and an inert gas selected from at least one of argon and helium.
5. The method according to claim 1, further providing an etch chemistry for the second process of an oxygen additive and at least one of CF4 and CHF3.
6. The method according to claim 1, wherein the dielectric spacers are oxide spacers on the substrate, adjacent the gate region and the anti-reflective coating layer, and the first process is used to substantially concurrently etch the dielectric layer to form the spacers and to remove the dielectric on the anti-reflective coating layer; and further including utilizing an endpoint to terminate the first process once the oxide over the anti-reflective coating is removed.
7. The method according to claim 6, wherein the gate region is made of amorphous silicon (ASi), and the second, different etching process, that selectively removes the anti-reflective coating over the gate region while preserving the oxide spacers adjacent the gate region, the spacers and gate region forming an aperture therein for receiving a silicide.
8. The method according to claim 6, wherein the oxide layer is made of silicon dioxide (SiO2) and the second, different etching process, that selectively removes the anti-reflective coating over the gate region while preserving the oxide spacers adjacent the gate region, the spacers and gate region forming an aperture therein for receiving a silicide.
9. The method according to claim 6, wherein the anti-reflective coating is made of silicon oxynitride (SiON) and the second, different etching process, that selectively removes the anti-reflective coating over the gate region while preserving the oxide spacers adjacent the gate region, the spacers and gate region forming an aperture therein for receiving a silicide.
10. The method according to claim 6, further providing an etch chemistry for the first process selected from one of CF4 and CHF3/CF4, and further including an inert gas selected from one of argon and helium.
11. The method according to claim 10, further providing an etch chemistry for the second process selected from one of CHF3 and CF4, and further including an oxygen additive.
PCT/US2000/035130 1999-12-30 2000-12-22 An improved method for buried anti-reflective coating removal WO2001050504A2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003081660A1 (en) * 2002-03-19 2003-10-02 Freescale Semiconductor, Inc. Integrated circuit device and method therefor

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997048127A1 (en) * 1996-06-13 1997-12-18 France Telecom METHOD FOR ENGRAVING THE GATE IN MOS TECHNOLOGY USING A SiON BASED HARD MASK
US5731239A (en) * 1997-01-22 1998-03-24 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance
US5880006A (en) * 1998-05-22 1999-03-09 Vlsi Technology, Inc. Method for fabrication of a semiconductor device
US5902125A (en) * 1997-12-29 1999-05-11 Texas Instruments--Acer Incorporated Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction
US6013569A (en) * 1997-07-07 2000-01-11 United Microelectronics Corp. One step salicide process without bridging
US6069044A (en) * 1998-03-30 2000-05-30 Texas Instruments-Acer Incorporated Process to fabricate ultra-short channel nMOSFETS with self-aligned silicide contact
US6194297B1 (en) * 1999-01-19 2001-02-27 United Microeletronics Corp. Method for forming salicide layers
US6211048B1 (en) * 1998-12-21 2001-04-03 United Microelectronics Corp. Method of reducing salicide lateral growth

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997048127A1 (en) * 1996-06-13 1997-12-18 France Telecom METHOD FOR ENGRAVING THE GATE IN MOS TECHNOLOGY USING A SiON BASED HARD MASK
US5731239A (en) * 1997-01-22 1998-03-24 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance
US6013569A (en) * 1997-07-07 2000-01-11 United Microelectronics Corp. One step salicide process without bridging
US5902125A (en) * 1997-12-29 1999-05-11 Texas Instruments--Acer Incorporated Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction
US6069044A (en) * 1998-03-30 2000-05-30 Texas Instruments-Acer Incorporated Process to fabricate ultra-short channel nMOSFETS with self-aligned silicide contact
US5880006A (en) * 1998-05-22 1999-03-09 Vlsi Technology, Inc. Method for fabrication of a semiconductor device
US6211048B1 (en) * 1998-12-21 2001-04-03 United Microelectronics Corp. Method of reducing salicide lateral growth
US6194297B1 (en) * 1999-01-19 2001-02-27 United Microeletronics Corp. Method for forming salicide layers

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003081660A1 (en) * 2002-03-19 2003-10-02 Freescale Semiconductor, Inc. Integrated circuit device and method therefor
US6753242B2 (en) 2002-03-19 2004-06-22 Motorola, Inc. Integrated circuit device and method therefor
US6846716B2 (en) 2002-03-19 2005-01-25 Freescale Semiconductor, Inc. Integrated circuit device and method therefor

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