WO2001050504A3 - An improved method for buried anti-reflective coating removal - Google Patents

An improved method for buried anti-reflective coating removal Download PDF

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Publication number
WO2001050504A3
WO2001050504A3 PCT/US2000/035130 US0035130W WO0150504A3 WO 2001050504 A3 WO2001050504 A3 WO 2001050504A3 US 0035130 W US0035130 W US 0035130W WO 0150504 A3 WO0150504 A3 WO 0150504A3
Authority
WO
WIPO (PCT)
Prior art keywords
reflective coating
gate region
layer
gate
substrate
Prior art date
Application number
PCT/US2000/035130
Other languages
French (fr)
Other versions
WO2001050504A2 (en
Inventor
Mark W Haley
Delbert Parks
Original Assignee
Koninkl Philips Electronics Nv
Philips Semiconductors Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Semiconductors Inc filed Critical Koninkl Philips Electronics Nv
Priority to JP2001550784A priority Critical patent/JP2003519910A/en
Priority to EP00986719A priority patent/EP1188179A2/en
Publication of WO2001050504A2 publication Critical patent/WO2001050504A2/en
Publication of WO2001050504A3 publication Critical patent/WO2001050504A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method for manufacturing a semiconductor structure, having a substrate and a gate region thereon, is described that includes removing an anti-reflective coating (ARC) layer over the gate region to improve salicidation of the gate. An anti-reflective coating is formed over the gate region and then a dielectric layer is formed over the anti-reflective coating layer and the substrate. Dielectric spacers are then formed on the substrate, adjacent the gate region and the anti-reflective coating layer, by etching the dielectric layer using a first process that includes selectively removing portions of the dielectric layer on the anti-reflective coating. Utilizing a second, different etching process, the anti-reflective coating over the gate region is selectively removed while preserving the spacers adjacent the gate region. Use of the present invention helps to minimize the dielectric spacer loss along side the gate region during removal of the buried anti-reflective coating, thereby providing a protection to the gate edge during the salicidation.
PCT/US2000/035130 1999-12-30 2000-12-22 An improved method for buried anti-reflective coating removal WO2001050504A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001550784A JP2003519910A (en) 1999-12-30 2000-12-22 An improved method for removing buried anti-reflective coatings
EP00986719A EP1188179A2 (en) 1999-12-30 2000-12-22 An improved method for buried anti-reflective coating removal

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47533399A 1999-12-30 1999-12-30
US09/475,333 1999-12-30

Publications (2)

Publication Number Publication Date
WO2001050504A2 WO2001050504A2 (en) 2001-07-12
WO2001050504A3 true WO2001050504A3 (en) 2002-01-03

Family

ID=23887116

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/035130 WO2001050504A2 (en) 1999-12-30 2000-12-22 An improved method for buried anti-reflective coating removal

Country Status (3)

Country Link
EP (1) EP1188179A2 (en)
JP (1) JP2003519910A (en)
WO (1) WO2001050504A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6753242B2 (en) 2002-03-19 2004-06-22 Motorola, Inc. Integrated circuit device and method therefor

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997048127A1 (en) * 1996-06-13 1997-12-18 France Telecom METHOD FOR ENGRAVING THE GATE IN MOS TECHNOLOGY USING A SiON BASED HARD MASK
US5731239A (en) * 1997-01-22 1998-03-24 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance
US5880006A (en) * 1998-05-22 1999-03-09 Vlsi Technology, Inc. Method for fabrication of a semiconductor device
US5902125A (en) * 1997-12-29 1999-05-11 Texas Instruments--Acer Incorporated Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction
US6013569A (en) * 1997-07-07 2000-01-11 United Microelectronics Corp. One step salicide process without bridging
US6069044A (en) * 1998-03-30 2000-05-30 Texas Instruments-Acer Incorporated Process to fabricate ultra-short channel nMOSFETS with self-aligned silicide contact
US6194297B1 (en) * 1999-01-19 2001-02-27 United Microeletronics Corp. Method for forming salicide layers
US6211048B1 (en) * 1998-12-21 2001-04-03 United Microelectronics Corp. Method of reducing salicide lateral growth

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997048127A1 (en) * 1996-06-13 1997-12-18 France Telecom METHOD FOR ENGRAVING THE GATE IN MOS TECHNOLOGY USING A SiON BASED HARD MASK
US5731239A (en) * 1997-01-22 1998-03-24 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance
US6013569A (en) * 1997-07-07 2000-01-11 United Microelectronics Corp. One step salicide process without bridging
US5902125A (en) * 1997-12-29 1999-05-11 Texas Instruments--Acer Incorporated Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction
US6069044A (en) * 1998-03-30 2000-05-30 Texas Instruments-Acer Incorporated Process to fabricate ultra-short channel nMOSFETS with self-aligned silicide contact
US5880006A (en) * 1998-05-22 1999-03-09 Vlsi Technology, Inc. Method for fabrication of a semiconductor device
US6211048B1 (en) * 1998-12-21 2001-04-03 United Microelectronics Corp. Method of reducing salicide lateral growth
US6194297B1 (en) * 1999-01-19 2001-02-27 United Microeletronics Corp. Method for forming salicide layers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DATABASE EPODOC EUROPEAN PATENT OFFICE, THE HAGUE, NL; 1 September 2000 (2000-09-01), XP002179134 *

Also Published As

Publication number Publication date
WO2001050504A2 (en) 2001-07-12
JP2003519910A (en) 2003-06-24
EP1188179A2 (en) 2002-03-20

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