WO2001054176A1 - Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors - Google Patents

Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors Download PDF

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Publication number
WO2001054176A1
WO2001054176A1 PCT/US2001/001758 US0101758W WO0154176A1 WO 2001054176 A1 WO2001054176 A1 WO 2001054176A1 US 0101758 W US0101758 W US 0101758W WO 0154176 A1 WO0154176 A1 WO 0154176A1
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Prior art keywords
wafer
silicon
silicon wafer
handle
micro
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Application number
PCT/US2001/001758
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French (fr)
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WO2001054176A9 (en
Inventor
Timothy G. Slater
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Xros, Inc., Nortel Networks
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xros, Inc., Nortel Networks filed Critical Xros, Inc., Nortel Networks
Priority to EP01903124A priority Critical patent/EP1254479A1/en
Priority to CA002397760A priority patent/CA2397760A1/en
Priority to AU2001230982A priority patent/AU2001230982A1/en
Publication of WO2001054176A1 publication Critical patent/WO2001054176A1/en
Publication of WO2001054176A9 publication Critical patent/WO2001054176A9/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Definitions

  • the invention relates to the fabrication of Silicon- On-Insulator (SOI) structures.
  • SOI wafer is a bonded SOI wafer.
  • a bonded SOI wafer is manufactured as two wafers, a device wafer and a handle wafer.
  • the handle wafer is thermally oxidized to form on its surface an oxide layer.
  • Both wafers are chemically treated to become hydrophilic, are aligned and their polished surfaces allowed to come into contact.
  • the wafers adhere to each other and, after a high temperature annealing process, are strongly bonded together.
  • the bonded wafer is ground and polished to form a finished wafer consisting of a handle wafer, an intermediate buried oxide and a device silicon wafer.
  • the device wafer can typically range from less than one micron to several tens of microns in thickness.
  • Prior scanners use a single crystal SOI fabricated mirror.
  • the silicon of the handle wafer is etched away from beneath the device layer and the buried oxide layer serves as a convenient hard etch stop layer during this process.
  • the remaining thin device layer of silicon is etched to form a one- or two-dimensional moveable mirror, as described in U.S. Patent 5,629,790, to Neukermans et al.
  • a method of fabricating a Silicon-On-Insulator (SOI) bonded wafer structure includes oxidizing a device silicon wafer and bonding the oxidized device silicon wafer to a handle silicon wafer.
  • SOI Silicon-On-Insulator
  • Embodiments of the invention may include one or more of the following features.
  • Fabricating the SOI bonded wafer structure can further include lapping the device silicon wafer down to a desired thickness and etching the device silicon wafer to define a mirror. Fabricating the SOI bonded wafer structure can further include oxidizing the handle silicon wafer prior to bonding the oxidized device silicon wafer to the handle silicon wafer.
  • the oxidizing of the handler silicon wafer and the oxidizing of the device silicon wafer can each result in oxide films approximately equal to one-half of a desired thickness.
  • the device silicon wafer, the handle silicon wafer, or both of the silicon wafers can be made of polysilicon.
  • the advantages of the present invention are the following. If the buried oxide layer is grown on the device wafer instead of the handle wafer, the flatness of a silicon mirror fabricated with an SOI manufacturing process so modified may be substantially improved. Similar results may be obtained if an oxide film half the desired thickness is grown on both the handle and device wafers, or the oxide film is split between the two wafers in some other manner.
  • FIG. 1 is a side view of a prior art silicon bonded wafer structure.
  • FIG. 2 is a side view of micro-mirror structure fabricated from a silicon bonded wafer structure.
  • FIG. 3 is a side view of a silicon bonded wafer structure fabricated using a thermally oxidized device wafer.
  • FIG. 4 is a side view of a silicon bonded wafer structure fabricated using thermally oxidized handle and device wafers .
  • FIG. 5 is a side view of a bonded wafer structure fabricated using polysilicon instead of single crystal silicon as the device wafer.
  • FIG. 6 is a schematic depiction of polysilicon resistive sensors arranged in a Wheatstone bridge arrangement for measuring torque.
  • a prior art silicon bonded wafer structure 10 including a set of bonded wafers, more particularly, a handle wafer 12 and a device wafer 14, separated by an oxide layer 16, is shown.
  • the wafers are bonded as follows.
  • the handle wafer 12 is thermally oxidized to form the oxide layer 16, which typically has a thickness of a few thousand Angstrom.
  • the device wafer 14 is bonded to the oxidized handle wafer 12. Once bonded, the device wafer 14 is lapped down or otherwise thinned to a required thickness.
  • a micro-mirror structure 20 produced from the silicon bonded wafer structure 10 (of FIG. 1) is shown.
  • etching is performed and a moveable mirror 32 is defined in the device wafer 14.
  • This process is described in U.S. Patent Application Serial Nos . 5,629,790 and 6,044,705, both to Neukermans et al., both incorporated herein by reference. It is found that for very large thin mirrors (e.g., several mm in size and 2-10 micron thick) produced by this process, there are some residual stresses that make such mirrors marginal for use in very demanding optical applications.
  • an enhanced silicon bonded wafer structure 30 includes the handle wafer 12, the device wafer 14 and the oxide layer 16 disposed therebetween.
  • the device wafer 14 is thermally oxidized to form the oxide layer 16.
  • the oxidized device wafer 14 and handle wafer 12 are bonded, and the device wafer 14 is thinned.
  • a micro-mirror structure is provided from the silicon bonded wafer structure 30 using techniques as shown and described in FIG. 2.
  • the mirrors manufactured on the silicon bonded wafer structure 30 are much flatter than those manufactured using conventionally provided a set of bonded wafers.
  • both the handle wafer 12 and the device wafer 14 can be oxidized to form the oxide layer 16 prior to bonding.
  • the wafers 12, 14 may be oxidized with the same or different thickness.
  • the thickness of the oxide grown on the handle wafer 12 is equal to or less than the thickness of the oxide grown on the device wafer 14.
  • a single crystal silicon device layer also allows for the incorporation of high sensitivity shear sensors, which allow the positioning of mirrors in micro- mirror structures like the one shown in FIG. 2 with great accuracy.
  • an SOI structure that includes polysilicon is used to produce a more ductile material.
  • a silicon bonded wafer structure 50 includes the handle wafer 12 and the oxide wafer 16, but the single crystal device wafer 14 (of FIGS. 1-4) is replaced by a polysilicon device wafer 52, of the same size.
  • the polysilicon wafer 52 is lapped down to the desired thickness and, after etching, gives rise to the structure 50.
  • the top layer 52 is polysilicon, and, as before, the intermediate layer 16 is oxide and the bottom layer 12 is a single crystal silicon layer.
  • the polysilicon wafer yields a thick (5-100 micron), stress free layer of polysilicon that is suitable as a mirror plate.
  • the resultant layer of polysilicon is then treated as the single crystal layer for purposes of mirror construction.
  • the polysilicon layer can be used to define polysilicon hinge sensors as well, and in the same manner as single crystal silicon.
  • the handle wafer 12 can also be made of polysilicon.
  • one or both of the wafers 12, 14 can be made of polysilicon and an oxide formed on the device wafer 14 (whether it be made of polysilicon or single crystal silicon) as described above.
  • a partial view of a hinge 60 shows four polysilicon resistive sensors 62 placed in a Wheatstone bridge type arrangement 64 so that the output corresponds to a shear measurement, that is, the diagonal axis of the Wheatstone bridge 64 is along the direction of hinge 62. Applying voltage to a-a produces an output b-b if shear is present.
  • This arrangement is similar to that of measuring torque with classical strain gauges. It may be noted that the polysilicon hinge sensors are not as sensitive as those made from the single crystal silicon.

Abstract

A bonded wafer fabrication mechanism for a micro-mirror structure provides for oxidizing a device wafer instead of a handle wafer or splitting thermal oxidation processing between the device wafer and the handle wafer prior to etching. The flatness of mirrors in micro-mirror structures fabricated according to such a mechanism is substantially improved.

Description

WAFER BONDING TECHNIQUES TO MINIMIZE BUILT-IN STRESS OF SILICON MICROSTRUCTURES AND MICRO-MIRRORS
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from the following U.S. Provisional Patent Application, the disclosure of which is incorporated by reference in its entirety for all purposes:
U.S. Provisional Patent Application Serial No. 60/176,325, entitled "New Wafer Bonding Techniques to Minimize Built-in Stress of Silicon Microstructures and Micro Mirrors," filed January 18, 2000.
BACKGROUND OF THE INVENTION
The invention relates to the fabrication of Silicon- On-Insulator (SOI) structures.
There is great interest in making small optomechanical structures out of SOI material using micromachining techniques. One type of SOI wafer is a bonded SOI wafer. Often a bonded SOI wafer is manufactured as two wafers, a device wafer and a handle wafer. The handle wafer is thermally oxidized to form on its surface an oxide layer. Both wafers are chemically treated to become hydrophilic, are aligned and their polished surfaces allowed to come into contact. The wafers adhere to each other and, after a high temperature annealing process, are strongly bonded together. The bonded wafer is ground and polished to form a finished wafer consisting of a handle wafer, an intermediate buried oxide and a device silicon wafer. The device wafer can typically range from less than one micron to several tens of microns in thickness. Prior scanners use a single crystal SOI fabricated mirror. Generally, to produce a moveable mirror in SOI material, the silicon of the handle wafer is etched away from beneath the device layer and the buried oxide layer serves as a convenient hard etch stop layer during this process. The remaining thin device layer of silicon is etched to form a one- or two-dimensional moveable mirror, as described in U.S. Patent 5,629,790, to Neukermans et al.
Although a silicon mirror should have nearly zero stress and therefore present an optically flat surface, conventional SOI wafer manufacturing processes can affect the flatness of the silicon device layer. Detailed interferometric measurements of the flatness of silicon mirrors approximately 1.5 by 2.1 mm made of bonded SOI material 10 urn thick show a non-flatness of up to 0.3 waves (lambda=633um) when fabricated using the standard technology. For very large flat mirrors that are extremely thin as required in many applications, this flatness is not adequate.
SUMMARY OF THE INVENTION
In one aspect of the invention, a method of fabricating a Silicon-On-Insulator (SOI) bonded wafer structure includes oxidizing a device silicon wafer and bonding the oxidized device silicon wafer to a handle silicon wafer.
Embodiments of the invention may include one or more of the following features.
Fabricating the SOI bonded wafer structure can further include lapping the device silicon wafer down to a desired thickness and etching the device silicon wafer to define a mirror. Fabricating the SOI bonded wafer structure can further include oxidizing the handle silicon wafer prior to bonding the oxidized device silicon wafer to the handle silicon wafer.
The oxidizing of the handler silicon wafer and the oxidizing of the device silicon wafer can each result in oxide films approximately equal to one-half of a desired thickness.
The device silicon wafer, the handle silicon wafer, or both of the silicon wafers can be made of polysilicon.
Among the advantages of the present invention are the following. If the buried oxide layer is grown on the device wafer instead of the handle wafer, the flatness of a silicon mirror fabricated with an SOI manufacturing process so modified may be substantially improved. Similar results may be obtained if an oxide film half the desired thickness is grown on both the handle and device wafers, or the oxide film is split between the two wafers in some other manner.
Other features and advantages of the invention will be apparent from the following detailed description and from the claims .
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a side view of a prior art silicon bonded wafer structure. FIG. 2 is a side view of micro-mirror structure fabricated from a silicon bonded wafer structure.
FIG. 3 is a side view of a silicon bonded wafer structure fabricated using a thermally oxidized device wafer. FIG. 4 is a side view of a silicon bonded wafer structure fabricated using thermally oxidized handle and device wafers . FIG. 5 is a side view of a bonded wafer structure fabricated using polysilicon instead of single crystal silicon as the device wafer.
FIG. 6 is a schematic depiction of polysilicon resistive sensors arranged in a Wheatstone bridge arrangement for measuring torque.
DETAILED DESCRIPTION
Referring to FIG. 1, a prior art silicon bonded wafer structure 10 including a set of bonded wafers, more particularly, a handle wafer 12 and a device wafer 14, separated by an oxide layer 16, is shown. Using conventional fabrication techniques, the wafers are bonded as follows. The handle wafer 12 is thermally oxidized to form the oxide layer 16, which typically has a thickness of a few thousand Angstrom. The device wafer 14 is bonded to the oxidized handle wafer 12. Once bonded, the device wafer 14 is lapped down or otherwise thinned to a required thickness. Referring to FIG. 2, a micro-mirror structure 20 produced from the silicon bonded wafer structure 10 (of FIG. 1) is shown. To transform the silicon bonded wafer structure 10 to the micro-mirror structure 20, etching is performed and a moveable mirror 32 is defined in the device wafer 14. This process is described in U.S. Patent Application Serial Nos . 5,629,790 and 6,044,705, both to Neukermans et al., both incorporated herein by reference. It is found that for very large thin mirrors (e.g., several mm in size and 2-10 micron thick) produced by this process, there are some residual stresses that make such mirrors marginal for use in very demanding optical applications.
Referring to FIG. 3, an enhanced silicon bonded wafer structure 30 includes the handle wafer 12, the device wafer 14 and the oxide layer 16 disposed therebetween. In order to fabricate the enhanced silicon bonded wafer structure 30, the device wafer 14 is thermally oxidized to form the oxide layer 16. The oxidized device wafer 14 and handle wafer 12 are bonded, and the device wafer 14 is thinned. A micro-mirror structure is provided from the silicon bonded wafer structure 30 using techniques as shown and described in FIG. 2. The mirrors manufactured on the silicon bonded wafer structure 30 are much flatter than those manufactured using conventionally provided a set of bonded wafers.
Other embodiments are contemplated. For example, and with reference to FIG. 4, both the handle wafer 12 and the device wafer 14 can be oxidized to form the oxide layer 16 prior to bonding. The wafers 12, 14 may be oxidized with the same or different thickness. Preferably, the thickness of the oxide grown on the handle wafer 12 is equal to or less than the thickness of the oxide grown on the device wafer 14.
Specifically, using a buried oxide layer of 4000A and a device wafer or device silicon layer of 10 microns, a mirror 1.5 by 2.1 mm shows an average non-flatness (lambda=633nm) of: 0.22 waves when the handle wafer is oxidized 4000A; 0.11 waves when the device wafer is oxidized 4000A; and 0.12 waves when the handle and device wafers are both oxidized 2000A.
Removal of an interfacial silicon layer on the device wafer 16 by a very short chemical etch after removing the buried oxide layer further relieves built-in stresses. Although not shown, a single crystal silicon device layer also allows for the incorporation of high sensitivity shear sensors, which allow the positioning of mirrors in micro- mirror structures like the one shown in FIG. 2 with great accuracy.
In yet another embodiment, an SOI structure that includes polysilicon is used to produce a more ductile material.
Referring to FIG. 5, a silicon bonded wafer structure 50 includes the handle wafer 12 and the oxide wafer 16, but the single crystal device wafer 14 (of FIGS. 1-4) is replaced by a polysilicon device wafer 52, of the same size. The polysilicon wafer 52 is lapped down to the desired thickness and, after etching, gives rise to the structure 50. The top layer 52 is polysilicon, and, as before, the intermediate layer 16 is oxide and the bottom layer 12 is a single crystal silicon layer. The polysilicon wafer yields a thick (5-100 micron), stress free layer of polysilicon that is suitable as a mirror plate. The resultant layer of polysilicon is then treated as the single crystal layer for purposes of mirror construction. The polysilicon layer can be used to define polysilicon hinge sensors as well, and in the same manner as single crystal silicon.
The handle wafer 12 can also be made of polysilicon. Thus, one or both of the wafers 12, 14 can be made of polysilicon and an oxide formed on the device wafer 14 (whether it be made of polysilicon or single crystal silicon) as described above.
Referring to FIG. 6, a partial view of a hinge 60 shows four polysilicon resistive sensors 62 placed in a Wheatstone bridge type arrangement 64 so that the output corresponds to a shear measurement, that is, the diagonal axis of the Wheatstone bridge 64 is along the direction of hinge 62. Applying voltage to a-a produces an output b-b if shear is present. This arrangement is similar to that of measuring torque with classical strain gauges. It may be noted that the polysilicon hinge sensors are not as sensitive as those made from the single crystal silicon.
Other embodiments are within the scope of the following claims.
What is claimed is:

Claims

1. A method of fabricating a Silicon-On-Insulator (SOI) bonded wafer structure comprising: oxidizing a surface portion of a device silicon wafer; and bonding the oxidized surface portion of the device silicon wafer to a handle silicon wafer.
2. The method of claim 1, further comprising: lapping the device silicon wafer down to a desired thickness; and etching the device silicon wafer to define a mirror.
3. The method of claim 2, further comprising: oxidizing the handle silicon wafer prior to bonding the oxidized device silicon wafer to the handle silicon wafer.
4. The method of claim 3, wherein the oxidizing of the handler silicon wafer and the oxidizing of the device silicon wafer each result in oxide films approximately equal to one-half of a desired thickness.
5. The method of claim 1, wherein the device silicon wafer is made of single crystal silicon.
6. The method of claim 1, wherein the handle silicon wafer is made of single crystal silicon.
PCT/US2001/001758 2000-01-18 2001-01-18 Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors WO2001054176A1 (en)

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EP01903124A EP1254479A1 (en) 2000-01-18 2001-01-18 Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors
CA002397760A CA2397760A1 (en) 2000-01-18 2001-01-18 Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors
AU2001230982A AU2001230982A1 (en) 2000-01-18 2001-01-18 Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors

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US17632500P 2000-01-18 2000-01-18
US60/176,325 2000-01-18
US71591600A 2000-11-16 2000-11-16
US09/715,916 2000-11-16

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CA2397760A1 (en) 2001-07-26
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