WO2001057931A1

WO2001057931A1 - Field effect transistor and method for the production of a charge carrier injected field effect transistor

Info

Publication number: WO2001057931A1
Application number: PCT/DE2001/000338
Authority: WO
Inventors: Harald Bachhofer; Thomas Peter Haneder; Hans Reisinger; Gernot Steinlesberger
Original assignee: Infineon Technologies Ag
Priority date: 2000-02-02
Filing date: 2001-01-29
Publication date: 2001-08-09
Also published as: DE10004392A1

Abstract

A source/drain voltage is applied to the field effect transistor during injection of the charge carriers in the channel area of the field effect transistor with the purpose of achieving inhomogeneous distribution of the charge carrier in the channel area.

Description

description

Field effect transistor and method for producing a field effect transistor injected with charge carriers

The invention relates to a field effect transistor and a method for producing a field effect transistor injected with charge carriers.

Such a method and a field effect transistor produced by means of such a method are known from [1].

It is known from [1] to inject charge carriers homogeneously into a channel region of the field effect transistor along the entire gate of the field effect transistor. The field effect transistor has a gate region, a source region, a drain region and a channel region between the source region and the drain region. When the field effect transistor is in the conductive state, a space charge zone is built up through which the current flows through the field effect transistor.

The following parameters of a field effect transistor are of particular importance for use in an analog circuit: the threshold voltage of the field effect transistor,

The steepness of the field effect transistor,

The source-drain breakdown voltage, and

• the output resistance of the field effect transistor.

In a circuit with paired MOS field-effect transistors (Metal Oxide Semiconductor Field-Effect Transistor, MOSFET) it may be necessary that the threshold voltage and the slope of the MOS field-effect transistor match.

Through a homogeneous injection of the charge carriers, ie through a homogeneous occupation of the so-called traps in the channel loading The threshold voltage of the MOS field-effect transistor is shifted richly between source and drain. All other transistor parameters, in particular the further transistor parameters described above, which are of particular importance for an analog circuit with a field effect transistor, remain unchanged. It is often desirable that the slope of the MOS field effect transistor and the output resistance of the MOS field effect transistor are as high as possible.

However, this is not achieved by the known method, since according to this method only the threshold voltage of the MOS field effect transistor is shifted.

Furthermore, a method for producing a MOS field-effect transistor is known from [2].

The problem underlying the invention is therefore to provide a field effect transistor and a method for producing a field effect transistor injected with charge carriers, in which the field effect transistor has an increased output resistance compared to the field effect transistor known from [1].

The problem is solved by the field effect transistor and by the method for producing a field effect transistor injected with charge carriers with the features according to the independent claims.

A field effect transistor has a gate region, a source region and a drain region. A channel region is provided between the source region and the drain region, along which a current flows between the source region and the drain region when the field effect transistor is in a conductive state. The channel region between the source region and the drain region has inhomogeneously injected charge carriers. In a method for producing a field effect transistor injected with charge carriers, the charge carriers are inhomogeneously injected into the channel region between the source region and the drain region of the field effect transistor along the channel region.

In the context of the description, inhomogeneous injection of the charge carriers into the channel area in this context is not to be understood as the unevenness in the distribution of the charge carriers within a narrow tolerance range, which can hardly be avoided with the homogeneous injection of the charge carriers. Rather, it is to be understood as an inhomogeneous injection which takes place, for example, by applying a source-drain voltage during the injection of the charge carriers and which leads to a clearly uneven, i.e. inhomogeneous

Distribution of charge carriers along the channel area leads, which is quantitatively significantly above the irregularity in a homogeneous charge carrier injection.

A permanent change in the properties of the field effect transistor is achieved by the invention. In particular, it is possible to increase the output resistance of the field effect transistor and the source / drain breakdown voltage of the field effect transistor.

Furthermore, the invention makes it possible to improve the adaptation of the field effect transistor threshold voltage.

Preferred developments of the invention result from the dependent claims.

A MOS field-effect transistor can be used as the field-effect transistor.

The charge carriers are preferably injected into the channel region through the gate of the field effect transistor. According to a development of the invention, the injection is carried out in such a way that the threshold voltage is increased more in the vicinity of the source region of the field effect transistor than in the vicinity of the drain region of the field effect transistor.

In this way, a further increase in the output resistance of the field effect transistor is achieved. During the injection of the charge carriers, a source-drain voltage can be applied to the field effect transistor, as a result of which, if the source-drain voltage is sufficiently high, high-energy charge carriers, which are also referred to as ^ hotϊ ^ charge carriers, are driven into the channel region, since their energy level is sufficiently high is to overcome the energy threshold formed by the gate.

To inject the charge carriers, they can also be driven into the channel area using the principle of tunneling charge carriers. According to this configuration, the principle of Fowler-Nordheim tunneling is preferably used.

The field effect transistor according to the invention is particularly suitable for use in an analog circuit, i.e. for use in an electrical circuit with at least one analog component.

Embodiments of the invention are shown in the figures and are explained in more detail below.

Show it

FIG. 1 shows a flow diagram in which the individual method steps of the manufacturing method are shown in accordance with a first exemplary embodiment;

Figure 2 is a sketch of a field effect transistor according to the first embodiment; FIG. 3 shows an output characteristic field of a 0.4 μm n-channel

Short channel transistor according to a further embodiment.

2 shows a MOS field-effect transistor 200.

The MOS field-effect transistor 200 is produced in the following manner in a first method step (step 100, see FIG. 1):

The MOS field-effect transistor 200 is produced in accordance with the method described in [2].

In order to make it easier to understand, some process steps for the production of the MOS field-effect transistor are described below

200 outlined.

On a p-doped silicon wafer, which serves as the substrate

201 is used, a layer of silicon oxide is deposited by means of a chemical vapor deposition method (CVD).

Another layer of polycrystalline silicon is deposited on the silicon oxide layer, likewise by means of the CVD process.

A photoresist layer is deposited on the layer of polycrystalline silicon and light is radiated onto the photoresist layer by means of a light mask. After the developed areas of the photoresist layer and the areas of the polycrystalline silicon that are not covered with the photoresist have been etched back, the exposed areas of the silicon oxide layer are n-doped by means of phosphorus atoms, so that a first, n -doped area 202, hereinafter referred to as Source is referred to, and a second n-doped region 203, which is hereinafter referred to as drain, are formed. After the remaining photoresist layer has been removed, a further silicon oxide layer is deposited by means of the CVD process. In this way, a third region, which is referred to as gate 205 of the MOS field-effect transistor 200, is formed. A silicon oxide layer is located between the gate 205, source 202 and drain 203 and the substrate 201 as an insulation layer 204.

Electrical connections are in each case attached to the individual components of the MOS field-effect transistor 200.

The following are therefore provided in the MOS field-effect transistor 200:

a substrate connection 206 on the substrate 201, a source connection 207 on the source 202,

a drain connection 208 on the drain 203,

a gate connection 209 on the gate 205.

Furthermore, the MOS field effect transistor 200 also has field oxide layers 210, 211 for isolating the MOS field effect transistor 200 from other electrical components that are formed on the substrate 201.

The MOS field-effect transistor 200 produced in the manner described above is subjected to an injection of charge carriers (step 102).

Since this is an n-channel MOS field effect transistor in the present exemplary embodiment, electrons are injected through the gate 205 and the insulation layer 204 into a channel region 212. The channel region 212 has a width 215 with which the distance between the two n p junctions, which are formed between the source 202 and the substrate 201 and between the drain 203 and the substrate 201, is designated. Simultaneously with the start of charge carrier injection, which takes place by driving high-energy electrons into channel region 212 (driving "hot" electrons), an electrical voltage is applied between source 202 and drain 203, ie the drain connection 208 has an electrical charge during the charge carrier injection Potential V _D of V _D =

10V on, as well as the gate connection 209 (potential of the gate connection V _G = 10V). An electrical potential of 0 V is present at the source connection 207 and at the substrate connection 206 of the MOS field-effect transistor 200 (V _s =

V _BS = 0V).

By applying the source / drain voltage to the MOS field-effect transistor 200 during the injection of the charge carriers into the channel region 212, an inhomogeneous electric field is generated, which leads to an inhomogeneous distribution 213 of the charge carriers 214 supplied.

The inhomogeneous injection of the charge carriers is carried out in such a way that the threshold voltage of the MOS field-effect transistor 200 is increased more in the vicinity of the source 202 than in the vicinity of the drain 203.

The type of distribution 214 of the injected charge carriers 214 into the channel region 212 depends on the dose and the profile of the charge carrier injection and is permanent if the thickness of the silicon oxide on the substrate is sufficiently large. According to the exemplary embodiment, the silicon oxide layer has a thickness of approximately 4 n. In general, the thickness of the silicon oxide layer should be sufficiently large so that a large tunnel time constant is ensured (in the exemplary embodiment, the tunnel layer constant of more than 100 years is achieved by the thickness of the silicon layer of 4 nm). The load carrier injection can heuristically be adapted to the desired requirements depending on the application. According to the further silicon oxide layer this embodiment has a thickness of approximately 3 nm to 4 nm.

After the desired number of charge carriers has been injected into the channel region 212 in the desired manner, the injection of the charge carriers is ended (step 103).

3 shows the output characteristic field 300 for a MOS field-effect transistor according to a further exemplary embodiment, namely according to a 0.4 μm n-channel short-channel transistor with an ONO gate (oxide / nitride / oxide), which has the properties of a silicon oxide layer corresponds to the thickness lOnm as gate.

With the reference numeral 301 is a characteristic of the

Drain current I _{D of} the MOS field effect transistor depending on the

Designated drain voltage V _D before the charge carrier injection.

Reference character 302 is in each case a characteristic of the drain current I _{D of} the MOS field-effect transistor depending on the

Drain voltage V _D after the inhomogeneous charge carrier injection.

As can be seen from the output characteristic field 300, the drain current In through the MOS field-effect transistor has been reduced by means of the charge carrier injection, i.e. the output resistance of the MOS field effect transistor has been increased.

It can further be seen from FIG. 3 that the source / drain breakdown voltage has been increased by the inhomogeneous charge carrier injection into the channel region.

As an alternative to the exemplary embodiments described above, the injection of the charge carriers can be carried out using the principle of tunneling the charge carriers into the channel area 212 take place, for example according to the Fowler-Nordheim tunnel.

Even if the exemplary embodiments described above relate to an n-channel MOS field-effect transistor, the inhomogeneous charge carrier injection can of course also be applied to a p-channel MOS field-effect transistor, in which case the polarity of the potentials are inverted, etc. ,

The inhomogeneous injection of the charge carriers into the channel area can also be used with a field effect transistor of another type, for example with an MIS field effect transistor.

It should be noted that the MOS field-effect transistor can in principle be produced in a separate process in any manner without injected charge carriers.

The following publications are cited in this document:

[1] F. R. Libsch and M.H. White, Charge transport and storage of low programming voltage SONOS / MONOS memory devices, Solid State electronics (UK), Vol. 33, No. 1, pp. 105 - 126

[2] D. Widmann et al, technology of highly integrated circuits, Springer Verlag, 2nd edition, ISBN 3-540-59357-8, pages 3 - 12, 1996.

Claims

claims

1. Field effect transistor with

• a gate area, • a source area,

A drain area,

A channel area between the source area and the drain area,

• The channel region between the source region and the drain region has inhomogeneously injected charge carriers.

2. Field effect transistor according to claim 1, wherein the field effect transistor is a MOS field effect transistor.

3. Method for producing a field-effect transistor injected with charge carriers, in which the charge carriers are injected inhomogeneously into the channel region between the source region and the drain region of the field-effect transistor along the channel region.

4. The method according to claim 3, in which a MOS field-effect transistor is used as the field-effect transistor.

5. The method according to claim 3 or 4, wherein the injection of the charge carriers into the channel region takes place through the gate of the field effect transistor.

6. The method according to any one of claims 3 to 5, wherein the injection is carried out in such a way that the threshold voltage in the vicinity of the source region of the field effect transistor is increased more than in the vicinity of the drain region of the field effect transistor.

7. The method according to any one of claims 3 to 6, in which a source-drain voltage is applied to the field-effect transistor during the injection of the charge carriers.

8. The method according to any one of claims 1 to 7, in which high-energy electrons are generated to inject the charge carriers, the energy of which is sufficiently large to reach the channel region.

9. The method according to any one of claims 1 to 7, in which for the injection of the charge carriers, the charge carriers are driven into the channel area by means of tunnels.

10. Electronic circuit with at least one analog electronic component and with at least one field effect transistor according to claim 1 or 2.