WO2001059573A1

WO2001059573A1 - Information processor and semiconductor integrated circuit

Info

Publication number: WO2001059573A1
Application number: PCT/JP2000/000648
Authority: WO
Inventors: Seiji Miura; Kazushige Ayukawa; Takao Watanabe; Hiromi Watanabe
Original assignee: Hitachi, Ltd.
Priority date: 2000-02-07
Filing date: 2000-02-07
Publication date: 2001-08-16
Also published as: AU2000223268A1; JP4549001B2

Abstract

A semiconductor integrated circuit for shortening totally access time in controlling accesses (read/write) from a plurality of access request sources (masters) to a memory block including a plurality of memory banks. By exploiting the properties of the masters, a memory control circuit for changing the contents of the memory access control is employed for each master. Specifically, when a first master having a property of accessing repeatedly the same page (word line) in the same memory bank makes an access request, this memory control circuit ends the access, with the page opened by the access open (bank active). On the contrary, when a second master having a low probability of repeated access to the same page makes an access request, the circuit closes the page opened by the access and ends the (pre-charge) access. This access control is useful especially for saving time to bring a DRAM word line (one word page) into a selected or nonselected state.

Description

Description Information processing device and semiconductor integrated circuit

The present invention relates to an information processing apparatus including a memory block having a plurality of memory banks shared by a plurality of masters, and to a semiconductor integrated circuit including a memory control circuit which receives access from the plurality of masters and controls the memory block. Background art

The documents referred to in this specification are as follows, and the documents are hereinafter referred to by their document numbers. [Reference 1]: Japanese Patent Application Laid-Open No. 05-181743.

[Literature 2]: Japanese Patent Application Laid-Open No. H10-2288413.

A typical information processing device includes a 3 'CPU (Central Processing Unit) and a DRAM (Dynamic Random Access Memory) connected to the CPU via a DRAM control circuit to store desired data. ing. When reading data from the DRAM, the CPU sends a read command to the DRAM control circuit, and the DRAM control circuit decodes the command and controls reading of desired data from the DRAM. The operation will be described below in accordance with a well-known sink DRAM (SDRAM) command system. In the DRAM read control from the DRAM control circuit, first, a non-active command and a row address are sent to the DRAM (ACTV). According to this instruction and the row address, a read line in the DRAM is selected, and data of one row on this word line is transferred to a sense amplifier, amplified, and held. Next, a read instruction and a column address are sent (READ). The column switch is selected by this instruction and the column address, and the data held by the sense amplifier is read. In DRAM, the operation of selecting a word line requires a relatively long time, but once data on the read line is held in the sense amplifier, access to the same read line, that is, within the same page When data is accessed, data can be read in a short time. Also, when reading data from a different word line from the currently selected word line, that is, when an access to a different page occurs, the currently selected word line is once deselected and a new word line is deselected. Since it is necessary to select a word line, it takes a long time to read data.

Now, in the information processing apparatus, a subject accessing the DRAM is not limited to the CPU described above, and may include a hard disk controller, an MPEG decoder, a graphics processing circuit, and the like. The hard disk controller, including the CPU, can be the main unit for accessing the DRAM, and each is called a master. [Reference 1] and [Reference 2] are known as references indicating an information processing apparatus including a plurality of masters.

[Reference 1] describes a technique for allocating a specific memory bank to a specific master in order to increase the efficiency when multiple masters (CPU and I / O controller IOC) access multiple memory banks. [Reference 2] is to hold data for read / write between each master and each memory bank in order to arbitrate access competition between multiple masters and multiple memory banks. A technique of providing a buffer is described. In order to improve access efficiency in a system having a plurality of masters and a plurality of memory banks, the inventors of the present application focused on not only arbitration of access competition but also the importance of control according to the characteristics of the master. In other words, even if the access from the CPU to the DRAM is random, is there. In other words, the CPu access has the property that the currently accessed address and the addresses near it are likely to be accessed again frequently in the near future. Therefore, access from the CPU to the DRAM frequently occurs within the same page.

On the other hand, the access address of the hard disk controller has less locality. When saving the data in the DRAM to the hard disk, an interrupt from the keyboard or mouse causes access to the DRAM from the hard disk controller, reads the data in the DRAM, and stores it in the hard disk. Once the data in the DRAM is saved, there is no need to read the data from the DRAM again unless an interrupt from the keyboard or mouse occurs. Therefore, it is extremely unlikely that the hard disk controller will frequently access the same address again and read data in the near future.

The MPEG decoder sequentially expands the data compressed on a CD-ROM or the like within a certain time and writes the data to the DRAM. Once the compressed data has been decompressed, there is no need to decompress the same data again, so it is extremely unlikely that the MPEG decoder itself will frequently access the same address again in the near future.

As described above, accesses from multiple masters sharing a DRAM have their own characteristics, and simple DRAM access control cannot cope with these accesses. When a master other than the CPU accesses a word line different from the word line already selected by the CPU, the access from the CPU, which was originally within the same page, will access a different page. It has been found that there is a problem that it takes a long time to read data from the DRAM and write data to the DRAM. Therefore, one of the objects of the present invention is to It is to speed up the reading and writing of DRAM for the access of. Disclosure of the invention

The typical means of the present invention are as follows. By identifying the master accessing the memory, the control mode is switched to control the memory corresponding to the master, and the memory is controlled. More specifically, based on the identification signal of each master, the power of closing the memory page at the beginning of access and the switching operation of whether or not to close it are performed, and according to this, the page opening / closing operation is performed at the end of access. Control the memory. When the memory is a DRAM, a page means one of a plurality of word lines in a specific memory bank, and a page open means one page while a word line in a specific memory bank is selected. This corresponds to the fact that the data of (1) is held in the sense amplifier (bank active state). On the other hand, page closing means that the word lines in a memory bank are not selected and any word line can be selected immediately when a word line selection request is issued to the memory bank. Yes (bank precharge state).

When an access request from a master with locality of access is received, if the access is terminated with the page open, the probability of accessing the same page in the next access is high, and the cache hit effect on the page will be reduced. It is easy to appear and access is speeded up. On the other hand, in the case of a master having a low locality of access, the access is terminated by closing the page. In the case of such a master, there is a high probability that the next access is not the same page but a different page, so if a page is opened, it takes time to close the page and reopen another page. It is. Therefore, for a master for which the cache hit effect cannot be expected, the overall access is made more efficient by terminating the access at the close of the page. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 shows a memory control circuit MCTL according to one embodiment of the present invention. FIG. 2 is an overall configuration diagram of an information processing apparatus to which the present invention is applied. Figure 3 shows an example of the instruction set of each master. FIG. 4 is an example of a block diagram of the memory block MEM of FIG. FIG. 5 is an example of a configuration diagram in a bank constituting the block diagram of FIG. FIG. 6 is a diagram illustrating an example of control of the memory block MEM in FIG. FIG. 7 is a diagram illustrating an example of control for setting data in the shift register of FIG. FIG. 8 is a flowchart showing the operation of the control mode switching circuit of FIG. FIG. 9 is an example of a diagram showing an address selection signal and an address corresponding to each memory bank set by the intra-page access determination circuit of FIG. FIG. 10 is a flowchart showing operations of the instruction generation circuit and the address generation circuit of FIG. 1 at the time of read and store instructions. FIG. 11 is a flowchart showing the operation of the instruction generation circuit and the address generation circuit of FIG. 1 at the time of a refresh instruction. FIG. 12 is a diagram showing the latency of DRAM for each access. FIG. 13 is a diagram showing an example of a temporal transition of a master accessing the DRAM. FIG. 14 is a waveform chart showing an example of an operation for access from the CPU. FIG. 15 is a waveform chart showing an example of an operation for an access from the CPU. FIG. 16 is a waveform diagram showing an example of an operation for access from the hard disk controller HDC. FIG. 17 is a waveform chart showing an example of an operation for access from the refresh control circuit. FIG. 18 is a diagram showing another embodiment of the memory control circuit of the present invention. FIG. 19 is a diagram showing another embodiment of the information processing apparatus of the present invention. FIG. 20 is a diagram showing another embodiment of the information processing apparatus of the present invention. FIG. 21 shows another embodiment of the information processing apparatus of the present invention. FIG. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Although the circuit elements constituting each functional block of the embodiment are not particularly limited, they are formed on one semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (Complementary MOS Transistor). You.

FIG. 2 is a basic configuration diagram of an information processing apparatus using the present application. This consists of a first master CPU4, a second master hard disk controller (HDC) 5, an access arbitration circuit (ARB) 2 for arbitrating access from the CPU and HDC, and a plurality of Controls the refresh operation of the memory block (MEM) 3 composed of banks, the memory control circuit (MCTL) 1 that controls MEM by signals from the ARB, the hard disk (HD) 50, and the memory block 3. It consists of a refresh control circuit (RFC) 6. RFC is the third master.

The hard disk controller HDC controls data transfer between the hard disk 50 and the memory block MEM. The MEM is composed of four memory macros, the 0th memory macro 3M0 and the third memory macro 3M3. Each memory macro is composed of four memory banks, and each memory bank has a sense amplifier. This information processing device operates in synchronization with the clock CLK.

Although the CPU is not particularly limited, the address space can be managed by a 32-bit address signal, and the memory block MEM is mapped to a lower 18-bit address space of the CPU address signal. Before explaining the operation of the information processing device, The instruction set will be described. Fig. 3 (a) shows the instruction set of the CPU. The instructions from the CPU to the access arbitration circuit ARB are the CPU instruction signals RW 0 [0] to RWO [3] (corresponding to RWO (4 bits) in Fig. 2). ). The load instruction LD is an instruction for reading data from the DRAM. The store instruction ST is an instruction for writing data to the DRAM. The set register SR is an instruction for setting data in shift registers 1a, lb, and 1c in the DRAM control circuit 1 in FIG. 1 described later. Reserve RV is a reserve instruction to add a new instruction. No operation NO P is an instruction that does nothing.

FIG. 3B shows the instruction set of the hard disk controller HDC, which is represented by the HDC instruction signals RW 1 [0] to RWO [2] (corresponding to RW 1 (2 bits) in FIG. 2). LD, ST, and NOP are instructions having the same role as that described in FIG.

Fig. 3 (c) shows the instruction set of the access arbitration circuit ARB. The instructions from the ARB to the memory control circuit MCTL are ARB instruction signals I COM [0] to I COM [3] (IC OM in Fig. 2). (Corresponding to (4 bit)). R and W are a read instruction and a write instruction, respectively, and are issued corresponding to the LD and ST of the CPU and HDC. The access end instruction EOA is an instruction indicating the end of access. The refresh instruction RF is an instruction for performing a MEM refresh operation. RF is issued in response to a refresh request from the refresh control circuit RFC, which is the third master. S R and NO P are instructions having the same role as the instruction already described with reference to FIG. FIG. 3 (d) shows the instruction set of the memory control circuit MCTL. The instruction from MCTL to MEM is MC TL instruction signals MC OM [0] to MC OM [2] (M COM (3 bit ) Corresponding to). Λ

^ BA is a memory block of MEM's special memory bank 命令 This is an instruction to select a line. The column read instruction RD is an instruction to read data on a selected memory cell of a specific memory bank of MEM. The _c column write instruction WT is an instruction to write data on a selected memory cell of MEM. The precharge command PRE deselects the selected word line and closes the page. NOP is an instruction that means do nothing as in Fig. 3 (a).

Next, the operation of the information processing apparatus of FIG. 2 will be described. When loading data to the CPU, the access request signal REQ0 is set to Low. At the same time as the access request, a load instruction from RW0, a CPU identification signal from MAD0, and an address from ADD0 are output to the access arbitration circuit ARB.

The hard disk controller HDC has a 512-byte buffer inside, and when loading data of the memory block MEM into this buffer, the access request signal REQ 1 is set to Low. At the same time as this access request, a load instruction is output from RW1, an identification signal of HDC is output from MAD1, and an address is output from AADD to ARB.

The data stored in the memory block MEM is likely to be lost unless a refresh operation is performed when DRAM is used.Therefore, the refresh request is periodically sent from the refresh control circuit RFC. There is a need to do. When a refresh request is issued from RFC, REG 2 is set to Low, and at the same time, a refresh command, MAD 2 power, etc. are output from RW 2 to the RFC identification signal, and ADD 2 is output to address ARB.

Access arbitration circuit The ARB monitors whether an access request from the CPU, an access request from the HDC, and an access request from the RFC have been received, and prioritizes the access requests from each master. And allow access from one master. The priority can be changed according to the type and number of masters constituting the information processing device. This In the case of, the access from the RFC is the first priority because it is the control of the refresh. Access from the HDC is interrupt processing, so it has the second priority, and access from the CPU has the last third priority.

Access arbitration circuit When the ARB sets ACK 0 to Low and permits an access request for a load instruction from the CPU, the CPU identifies the CPU identification signal from I MAD, the read instruction from I COM, and the address from I ADD. Output to The MCTL receives the signal from the ARB and controls the MEM.

FIG. 4 is a configuration example of a memory block MEM used in the present invention. 3MO, 3M1, 3M2, and 3M3 indicate memory macros, respectively.Each memory macro consists of four memory marks 3B0, 3B1, 3B2, and 3B3. It is configured. In this example, it is assumed that the data input buffer circuit IBUF and the output buffer circuit OBUF are shared between the four macros, and that the macros are integrated on one chip, although not particularly limited. However, MEMs can also be configured with memory modules that use a well-known SDRAM or similar command at each of the memory mask ports and operate using multiple memory modules. Fig. 5 shows an example of the configuration of DRAM in one memory bank, and Fig. 6 shows the operation of MEM.

Hereinafter, an example of an access operation to the memory block MEM will be described with reference to FIGS. Bank instructions BA and MAD from MC OM, row address RW 0 (10 bits of MADD [13: 4]), macro address MC 0 (2 bits of ADD [1: 0]), bank address When dress BK 0 (two bits of MADD [3: 2]) is input, one of 16 banks is selected by macro address MC 0 and bank address BK 0, and low address RW 0 The selected memory van One of the row and line WLs in the row decoder of the row decoder is selected, and the data of the memory cell for one page of 4096 bits is read out. The data is transferred to the sense amplifier 303 via the two bit line pairs (BL0-0 and BLB0-0 and BL256-15 and BLB256-15), and is held. The sense amplifier is a latch-type sense amplifier in which two CMOS inverters are cross-coupled, and has an amplification and a latch function. In this sense, the sense amplifier can be regarded as a data latch circuit. The sense amplifier is not limited to the above-mentioned latch type sense amplifier, and may be a circuit for separating the amplification section and the latch section of the sense amplifier. In order to read the data held in this sense amplifier, the read command RD from MCOM and the column address CAO (4 bits of MAD D [7: 4]) from MADD and the macro address MCO for the bankactive instruction are used. Enter the same macro address MC 0 and bank address BK 0 as the bank address BKO. One of the sixteen banks is selected by the macro address MC 0 and the bank address BK 0, and the column decoder 300 selects one column address by the column address CA 0. Depending on the selected column address, 256 out of 4096 column switches in the column switch group 304 are selected, and 256 out of the sense amplifiers 303 are selected. The bit data is output to the global bit line GBL, and is output to the outside of the MEM through the output buffer 306. Then, the page is closed by the precharge signal PRE and the bank address BK0. In such a normal operation, the latency from when the memory control circuit 1 receives an instruction from the CPU to when the data is output from the MEM is five.

FIG. 1 shows a memory control circuit MCTL of the present invention. This circuit identifies the master that accesses the memory block MEM, and switches the control mode for controlling the MEM corresponding to the master to the master or the MEM. The control mode switching circuit (C REG) 101 that dynamically performs when these accesses occur. Also, for each memory bank, an in-page access judgment circuit (PH) 102 for judging whether the already selected row address matches the address of the currently generated access, and a control instruction to the MEM are generated. This includes an instruction generation circuit (or command generation circuit) (CGEN) 103 that generates an address and an address generation circuit (AGEN) 104 that generates an address. Further, an input / output data control circuit (DQB) 105 for controlling input / output data is included.

The control mode switching circuit CREG outputs the output signal Id from the shift register la, the output signal 1e from the register 1b, and the output signal 1e from the register lc according to the shift registers la, lb, and lc, and the master identification signal I MAD. It comprises a selection circuit 1 g for selecting the output signal 1 f and a latch circuit 1 i for latching the output signal 1 h of the selection circuit 1 g. Each of the shift registers 1a to 1d is a shift register for setting a necessary flag signal to select a control mode for each master. 1 a can set the flag signal of the CPU, 1 b can set the flag signal of the hard disk controller HDC, 1 c can set the flag signal of the refresh control circuit RFC, and 1 d can set the flag signal of other masters.

Figure 7 shows the operation of setting the CREG shift registers 1a to 1d and the flag. As specific examples, the CPU flag signal High to the shift register la, the HDC flag signal Low to the shift register 1b, the RFC flag signal Low to the shift register 1c, and other masters This shows the operation when the flag signal ow is set to the shift register 1d. When the CPU issues a set register instruction SR and the ARB permits access, the set register instruction SR is input to the memory control circuit 1 through ICOM. In the set register instruction, as shown in Figure 3, the ICOM The 0th bit signal is the flag data FLAG-D set in the shift register.

Four consecutive set register instructions are issued from the ICOM.The first set register instruction sets the flag data to high, the second set register instruction sets low, and the third set register instruction sets low. In the fourth set register instruction, it is set to Low and input to the memory control circuit. At the rising edge of the first set register instruction, High is set to 1 d. At the next rising edge of the clock, the data of I d is transferred to lc, 1 c is set to High, and I d is set to Low. 1 c is set at the next rising edge of the clock. Data is transferred to 1b, 1b is set to High, 1d data is transferred to 1c, 1. Is set to ow and la is set to Low. By shifting the flag data in this way, 1 _& 111111, lb is Low, and 1 finally. Is set to 1 ^ 0, and 1 d is set to Low.

FIG. 8 is a flowchart showing the operation of the control mode switching circuit CREG. In this figure, I NPUT M-ID enclosed by a square indicates an operation for inputting a master identification number, and WAITM-ID indicates an operation for waiting for input of a master identification number. . ? The explanation is given with 11 as the identification number, 0 for the hard disk controller HDC, 1 for the refresh control circuit RFC, and 3 for the other masters. When access from the CPU is permitted to the access arbitration circuit and the CPU identification signal 0 is input to the memory control circuit MCTL through IMAD, the flag signal High of the shift register 1a passes through the output signal 1e, and the selection circuit 1 i is selected, output to the output signal 1 j of the selection circuit 1 i, is latched by the latch circuit 1 k, and the output LMS becomes H igh.

Access from HD C is permitted to ARB, and HD C identification signal 1 is When input to the MCTL through AD, the flag signal Low of the shift register 1b passes through the output signal 1f, is selected by the selection circuit 1i, is output to the output signal 1j of the selection circuit 1i, and is output to the latch circuit 1k. Low is latched at this time, and its output LMS becomes Low. When access from the RFC is permitted to the access arbitration circuit and the identification signal 2 of the RFC is input to the MCTL through the I MAD, the lag signal Low of the shift register 1c passes through the output signal 1g, and the selection circuit 1i Is output to the output signal 1 j of the selection circuit 1 i, and Low is latched by the latch circuit 1 k, and the output LMS becomes Low. The values of shift register 1a, lb, lc, and Id can also be set by providing dedicated setting terminals externally. Also, the values of the shift registers la, 1b, 1c, and 1d can be set by connecting to the power supply or ground with a metal layer or diffusion layer when integrated on a silicon. This is a so-called metal option.

Next, the operation of the intra-page access determination circuit PH will be described. Figure 9 shows the row address selection PS signal (PS) and row address (ROW-ADD) corresponding to each memory bank bank number (BANK NO.) Of each memory macro number (MACRO NO.) Set in PH. ). When the row address selection signal PS is Low, it indicates that the address of the bank has not been selected, and when High, it indicates that the address of the bank has been selected. HT is an intra-page access determination signal indicating whether or not the current access has occurred with respect to the selected row address, that is, whether or not the access is to the same page. When the access judgment signal in the HT page is High, it indicates an access within the same page as the selected address, and when Low, the access or the row of a page different from the selected row address is performed. Indicates that the access has not been selected. When HT is Low, selected by current access 1 The already set row address of one bank is always replaced with the row address of the current access. When HT is High, the lower address does not change.

I ADD is composed of an 18-bit address, and is not particularly limited. In the embodiment shown in FIG. 2, the 17th to 8th bits of the highest order are the MEM low address and the 7th bit. The 6th to 6th bits are the MEM memory non-address, the 5th to 4th bits are the MEM memory macro address, and the 3rd to 0th bits are the MEM column address.

The memory macro address, memory bank address and row address in the I ADD address are input to the in-page access determination circuit PH. In the PH, first, a PS signal corresponding to one memory bank selected by the memory macro address and the memory bank address is output to the instruction generation circuit CGEN and the address generation circuit AGEN. When the PS signal is Low, it is set to 1 at the next rising edge of the clock. When the access end command is input from ICOM and LMS is 0, the selected PS signal is set to 0.

Next, the operation of the intra-page access determination signal HT signal will be described. When the PS signal of one memory bank selected by the IADD address is Low, HT is set to Low. If the PS signal is high, HT is set to high if the row address of one bank selected by the memory macro address and memory bank address matches the current access address, and HT is set to low if they do not match. ow. The HT signal is output to the instruction generation circuit CGEN and the address generation circuit AGEN.

Figure 10 shows an example of the operation of the instruction generator CGEN and the address generator AGEN when a read instruction is input. 〇. For £ 1 ^ and 0 £ ^^, read command from 1 COM, address from IADD, access judgment The intra-page access determination signal HT and the row address selection signal PS, and the LMS from the control mode switching circuit 101 are input from the path 102.

When the row address selection signal PS is Low, in a normal access, CGEN and AGEN first perform a row operation. Specifically, CGEN first outputs a bank active instruction B A, and AGEN outputs a row address, a memory macro address, and a memory bank address to MEM. After two cycles, perform column operation. Specifically, CGEN outputs the read instruction RD, and AGEN outputs the column address, memory macro address, and memory bank address to MEM, and reads the data.

When the row address selection signal PS is High and the intra-page access determination circuit signal HT is Low, the current access is to access a row address different from the already selected row address, that is, to a different page. Indicates access. To access a different page, first perform a precharge operation, deselect the previously selected row address, then perform a row operation and select a new row address. After two cycles, perform column operation and read data.

When the address selection signal PS is High and the intra-page access determination circuit signal HT is High, the current access indicates an access within the already selected low address, that is, an access within the same page. In this case, no row operation is required, and a column operation is performed to read data.

For page access different from normal access, after column operation is completed, when EOA indicating the end of access is input from ICOM, and when LMS is low, precharge operation is performed and MEM memory bank Close the page. When LMS is high, precharge operation is not performed, and the next access is performed with the page opened. If the access is within the same page, wait for the next access with the page open. Figure 11 shows an example of the operation of the instruction generation circuit CGEN and the address generation circuit AGEN when a refresh instruction is input. For CGEN and AGEN, refresh command from ICOM, address from IADD, in-page access determination circuit 102 From in-page access determination signal HT, row address selection signal PS, and control mode switching circuit 101 LMS is entered.

When the row address selection signal PS is Low, CGEN and AGEN perform a row operation first in normal access. Specifically, CGEN first outputs a bank active instruction BA to AMEM, and AGEN outputs a row address, a memory macro address, and a memory bank address to MEM.

When the row address selection signal PS is High and the intra-page access judgment circuit signal HT is Low, the current access is to access a row address different from the already selected row address, that is, an address to a different page. Indicates access. To access a different page, first perform a precharge operation, deselect the previously selected row address, then perform a row operation and select a new row address.

When the row address selection signal PS is High and the intra-page access determination circuit signal HT is High, the current access indicates an access within the already selected row address, that is, an access within the same page. At this time, do nothing.

For access to a page different from the normal access, after the row operation is completed, when EOA indicating the end of the access is input from ICOM, if the LMS power is ow, the precharge operation is performed and the MEM memory bank Close the page. If the LMS is high, the pre-charge operation is not performed and the next access is performed with the page opened.

Figure 12 shows the latencies for the same page access, normal access, and different page access described above. When accessing the same page, 3 for write latency, 1 for write latency, 5 for normal access, 3 for write latency, 7 for different page access, 7 for read latency, 5 for write latency .

Figure 13 shows that after power-on (Tl (INIT)), access from the CPU (T2 (CPU)), access from the hard disk controller HDC (T3 (HDC)), and access from the CPU (T3 (HDC)) The following shows the specific operation when T4 (CPU)) occurs. PW in the Tl (INIT) period indicates power-on and initial operation after power-on. Each of C O to C m in the T 2 (CPU) period indicates one access from the CPU, and H 0 in the T 3 (HDC) period indicates one access from the HDC.

As described above, according to the present invention, the access from the CPU keeps the MEM read line selected at the end of the access, that is, keeps the page open, and the access from the HDC and the refresh control circuit MCTL The flag data was set in the shift registers la, lb, 1c, and 1d so that the page was closed at the end of the access. FIGS. 14 to 17 show specific examples of the operation. In FIGS. 14 to 17, I MAD is the identification number of the master, and I COM corresponds to the instruction in FIG. 3 (c). Here, the NO P instruction is abbreviated as N. I ADD represents an access address, and AD 0 represents a state where a predetermined address signal is input, while DC (Don't Care) represents a state where an address is undefined. MCOM Figure 3

Corresponds to the instruction in (d). MADD also indicates the access address to MEM.

By the initial operation (Tl (INIT)) after the power is turned on, the row address selection signal PS signal of each bank becomes low. Therefore, the first access (CO) from the CPU to each memory bank in the T 2 (CPU) period is a normal access, and the data read latency is 5. This operation is shown in Figure 14. You.

On the other hand, FIG. 15 shows the operation of the page hit state (HT = 1) in the second and subsequent accesses (〇1 to 〇! 1) of the T2 (CPU) period. ing. According to the present invention, the CPU access is not performed by closing the page at the end of the access, and the page is kept open. When most of the second and subsequent accesses to each bank are performed on the same page, the read latency is 3, and the MEM can operate faster than normal operation.

Figure 16 shows the H0 access during the T3 (HDC) period when the access is changed from the CPU to the hard disk controller HDC. In this access, it is assumed that a 512-byte read instruction is issued to the MEM from the HDC. First, the first half of FIG. 16 shows the operation when a page error occurs in the first access of H0. Since each memory bank of the memory block MEM has a page opened for access by the CPU, access from the HDC will almost always be to a different page. The read latency of the first access in Figure 16 is 7. Thereafter, the access by the hard disk controller HDC occurs within the same page, and a total of 16 accesses are performed to read 512 bytes, and the latency becomes 22. When EO indicating the end of access is input, the precharge operation is performed and the page is closed. Compared to the case of normal access, the initial data read latency is two latencies, that is, 20 ns' slower, but when the HDC writes 512 bytes of data to the hard disk, it takes several ms. The delay of 20 ns is not a problem in operation.

During T4 (CPU) period in Fig. 13, access is changed from HDC to CPU. The access of C n + 1 is as follows. According to the present invention, the page of one memory bank accessed by the HDC is closed, and the pages of the remaining memory banks remain open due to the access of the CPU. When the CPU accesses a bank whose page is closed, the access becomes normal and the latency becomes 5.

If the control mode switching circuit according to the present invention is not used, the page is kept open by the access from the hard disk controller HDC, and if the access to the bank holding this state occurs by the CPU, Mostly access to different pages. As a result, the read latency of the access from the CPU becomes 7, which is two latencies slower than the normal access, and this latency directly affects the operation of the CPU. Therefore, according to the present invention, for an access from the HDC, by closing the page at the end of the access, an access from the CPU after this access occurs in a memory bank previously accessed by the HDC. Also, latency does not increase.

Figure 17 shows an operation timing diagram when a refresh request is issued from the refresh control circuit RF. In this case, it is assumed that the page was closed by the last access. Access from RFC is generated to MEM in an interrupt about once every 4 μs, and the page is closed at the end of the refresh operation. In other words, in FIG. 17, MCOM terminates with PRE. That is, the same address is not accessed in the next access of RFC after 4 μs, so it is preferable to close the page. After this access, if the access from the CPU occurs in the memory bank accessed by the refresh control circuit, the latency does not increase.

The specific form of the information processing apparatus of the present invention applied to a semiconductor chip is as follows. First, CPU, HDC, RFC, etc. There is a form in which each of the master and the ARB, MCTL, and MEM are formed on individual semiconductor chips. Here, there are two types of MEM: a case in which all DRAMs are formed on one chip, and a case in which MEMs are formed by a plurality of DRAM chips. A well-known SDRAM or the like can be used for the DRAM chip. Next, as a second mode, there is a mode in which three functional blocks of RFC, ARB, and MCCTL are integrated on one chip as a memory control chip. Other CPUs are formed on individual semiconductor chips as in the first embodiment. As a third form, there is a form in which MCTL and MEM are formed on one chip. Others are the same as in the first embodiment. Furthermore, as a fourth mode, integrating the CPU, RFC, ARB, MCCTL, and MEM on a single semiconductor chip is also effective for small-scale systems. Even in this case, there is no particular limitation, but the master to be an external option such as HDC is a separate chip. If HDC is the most essential system, it can be integrated as needed.

FIG. 18 shows an embodiment of the memory control circuit 100 of the present invention, which is obtained by adding a refresh counter 106 for generating a refresh address to the embodiment shown in FIG. When a refresh command is input from ICOM, the address selection circuit 107 selects an address from the refresh counter and outputs the address to the in-page access determination circuit 102 and the address generation circuit. The refresh counter performs a refresh address renewal every time a refresh instruction is input.

FIG. 19 shows an information processing device using the memory control circuit 100. It arbitrates access from CPU, HDC, CPU and HDC

Arbitration circuit 2, MEM consisting of multiple banks, and access The arbitration circuit 2 includes a memory control circuit 1 for controlling the MEM in accordance with a signal from the arbitration circuit 2, a hard disk 50, and a refresh control circuit 6 for controlling a refresh operation of the MEM. The CPU, HDC, and refresh control circuit 6 do not have the MAD identification signal shown in FIG. 2, and the ports REQ0, REQ1, and REQ2 are connected to the access arbitration circuit. The access arbitration circuit identifies the master at the REQ O, REQ 1, and REQ 2 ports, receives requests from each master, and when access is granted, converts the port information to the master identification signal I MAD I do.

Since a refresh counter 106 is provided inside the memory control circuit 100, there is no need to input a refresh address from the refresh control circuit 6, and the refresh request signal REQ 2 and the refresh enable signal AC K 0 Only need to be connected.

Therefore, even in the configuration example of the information processing device in FIG. 19, the present invention can be realized and the number of terminals can be reduced, which can contribute to cost reduction.

FIG. 20 shows an embodiment in which the CPU 4, the MPEG decoder (MPEG DEC) 5001, the video interface circuit (VIF) 600, and the RFC become masters and access the memory block MEM. At this time, the MEM is shared by the CPU, the MPEGDEC and the VIF.

As in the first embodiment, the access of the CPU opens the page even after the access is completed, and the access of the MPEG decoder, the video interface, and the refresh control circuit 6 ends at the end of the access. Let's consider switching control so that is closed.

The MPEG decoder decompresses the compressed data stored in a CD-ROM or the like and temporarily stores it in the MEM. Video to view The data in the MEM is read from the interface. At this time, the data transfer rate required for the MEM in order for the MPEG decoder to expand the data is about 160 MByte / sec.

When calculating the memory capacity of one frame required for display, one frame is composed of 720 x 480 pixels for NTS C. Since one pixel is composed, the luminance signal Y is 8 bits and the color difference signal Cr is If Cb is 8 bits each, the total number of bits in one frame is about 4 Mbit. Assuming that 60 frames are read out per second, a display requires a data transfer rate of about 30 MB yte / sec. Therefore, a transfer rate of 190 MB yte / sec is required.

The MPEG decoder 501 and the display interface circuit 600 communicate with the memory block (MEM) 50 through the access arbitration circuit 201 and the memory control circuit 101 to form a 512-bit memory block. Connected by data bus. At this time, the access to the memory block 351 at which the data transfer rate of the MPEG decoder 501 becomes the lowest is access to a different page and is performed only once. In this access, 7 latencies, ie, 70 ns power, power, and data transfer rate are (5 1 2,8) Byte X (1 X 100 00) to output 512 bits of data. / 70) MH z = 9 1 1 MB yt eZ sec. Considering that the MPE G decoder requires a transfer rate of up to about 190 MB yte Z sec, the transfer rate of 9 1 MB yte / sec has enough margin, and the remaining transfer rate is sufficient for the CPU. Even if used, the operation of the MPEG decoder does not cause any problem. Therefore, in the second embodiment, the access from the MPEG decoder, the display interface circuit 701, and the refresh control circuit 600 according to the present invention can be achieved by closing the page at the end of these accesses. The access from the CPU after this access is as follows. Even if it occurs in the memory bank accessed by either the MPEG decoder or the video interface before, the latency of DRAM does not increase and the speed can be increased.

Example 4>

Figure 21 shows an embodiment in which the CPU 4, the graphics processing circuit (GC) 502, and the display interface circuit (VIF) 702 access the DRAM by the master and the refresh control circuit (RFC) 602. is there. At this time, the memory block (MEM) 352 is shared by the GC, VIF, and CPU.

As in the first embodiment, CPU access is controlled by opening a page even after the access is terminated, and by GC, VIF, and RFC access, switching control to close the page at the end of the access. Do.

The data transfer speed required for graphics processing by the graphics processing circuit 502 and the data transfer speed required by the display interface circuit 702 for display are obtained as follows.

The number of bits per pixel is 24 bits for R, G, and B representing color, 16 bits for Z value for depth, and 8 bits for α value for transparency, for a total of 48 bits. Assuming that the frame rate is 60 mm and the frame size is 640 x 480, the transfer rate required for drawing is about 884 MB yte / sec, and the transfer rate required for display is about 11 OMB yte / sec. Requires a total transfer rate of 1 GB yte / sec.

The graphics processing circuit GC and the display interface circuit 702 are connected to the access arbitration circuit 2 and the memory block 352 through the memory control circuit 102 via a 204-bit data bus. I have. At this time, the access to the memory block 352 at which the data transfer rate of the GC is the lowest is access to a different page, and is performed only once. this For access, to output 204 8-bit data, 7 latencies, that is, 70 ns power, and the data transfer rate is (204 8/8) Byte X (1 X 100 0/70) MHz = 3.6 GB yte / sec. Considering that a transfer rate of about l GB yt eZ sec is required for the combination of the graphtas processing circuit 502 and the display interface circuit 60 2, the transfer rate of 3.6 GB yte / sec is + min. Even if the remaining transfer rate is used for the CPU, there is no problem in the operation of the graphics processing circuit. Therefore, also in the third embodiment, the operation of the DRAM can be sped up by the present invention.

The DRAM used in the above-described embodiment shows an example in which a plurality of memory ports are integrated on one chip, but this is not a limitation. The present invention can be realized by treating the DRAM of each chip as a memory map.

As described above, access from a plurality of masters sharing a DRAM has its own characteristics. According to the present invention, the control mode can be switched to control the DRAM corresponding to the plurality of masters. , DRAM can be operated at high speed. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention can be applied to an information processing device, particularly a computer device represented by a personal computer device. This information processing device may be versatile or may be incorporated as a part of the control device.

Claims

Range of request

1. a memory block including a plurality of memory banks;

A first master capable of accessing the memory block, a second master capable of accessing the memory block, and receiving access requests from the first and second masters to the memory block. A memory control circuit that outputs an access instruction,

The memory control circuit accesses one of the plurality of memory banks in a first procedure when there is an access request from the first master, and when there is an access request from the second master, Accessing one of the plurality of memory banks in a second step.

2. In Claim 1,

Each of the plurality of memory banks includes a plurality of memory cells and a plurality of data latch circuits provided at intersections of a plurality of read lines and a plurality of data lines,

When the access request is a request to read data from one of the plurality of memory banks, the first procedure includes a step of storing predetermined data read from a selected memory cell into the plurality of data latch circuits. And holding the data to the plurality of data latch circuits after outputting the data to the first master, and the second step includes the step of storing the predetermined data read from the selected memory cell into the plurality of data latch circuits. A semiconductor integrated circuit comprising an operation of clearing the data held in the plurality of data latch circuits after holding the data in the data latch circuit and outputting the data to the second master.

3. In Claim 2,

The information processing apparatus further includes an access arbitration circuit inserted between the first and second masters and the memory control circuit, When the access request of the first master and the access request of the second master conflict, the access arbitration circuit transmits the access request of the second master to the memory control circuit with priority, and thereafter, An information processing device for transmitting an access request of a first master to the memory control circuit.

4. In Claim 3,

The information processing apparatus according to claim 1, wherein the first master is a CPU.

5. In Claim 1,

Each of the plurality of memory banks includes a plurality of memory cells provided at intersections of a plurality of read lines and a plurality of data lines, each of the plurality of memory banks including one MOS transistor and one capacitor.

When the access request is a request to read data from one of the plurality of memory banks, the first procedure includes an instruction to activate a selected memory bank to end a read operation; A semiconductor integrated circuit characterized in that the procedure includes an instruction to place a selected memory bank in a precharged state and finish a read operation.

6. In Claim 5,

Each of the first and second master access requests includes a bank address for designating one of the plurality of memory banks and one of the plurality of code springs in one of the plurality of memory banks. Mouth dress and to choose include

The memory control circuit includes: a first determination circuit configured to determine whether a memory bank corresponding to the bank address is in the active state or the precharge state when the access request is issued; When the memory bank corresponding to the address is in an active state, one of the plurality of read lines selected in the active memory bank is connected to the access bank. An information processing apparatus including a second determination circuit that determines whether or not the address matches the address included in the request.

7. In claim 6,

8. In Claim 1,

Each of the plurality of memory banks of the memory block is provided at an intersection of a plurality of data lines and a plurality of data lines, and includes a plurality of memory cells each including a serially connected MOS transistor and a capacitor. When the request is a data read request from a memory bank, the first procedure reads out predetermined data by selecting one of the plurality of word lines of a corresponding memory bank, and sends the read data to the first master. The second step includes an operation of keeping the selected word line in a selected state after outputting the data, and reading out predetermined data by selecting one of the plurality of read lines of a corresponding memory bank. An information processing apparatus characterized by including an operation of outputting to the second master and an operation of setting the selected word line to a non-selected state.

9. In Claim 1,

Each of the plurality of memory banks of the memory block is provided at an intersection of a plurality of word lines and a plurality of data lines, and includes a plurality of memory cells each including a MOS transistor and a capacitor connected in series, and When the request is a request to read data from a memory bank, the first step is to activate a corresponding memory bank and output predetermined data to the first master, and then activate the corresponding memory bank. The second procedure includes outputting predetermined data from a corresponding memory bank to the second master and then precharging the corresponding memory bank. .

10. In claim 1,

Each of the plurality of memory banks includes a plurality of memory cells provided at intersections of a plurality of code lines and a plurality of data lines,

Each of the first and second master access requests includes a bank address for designating one of the plurality of memory banks and one of the plurality of read lines in one of the plurality of memory banks. The mouth dress for choosing and includes

The information, wherein the memory control circuit includes a first determination circuit that determines whether a memory bank corresponding to the bank address is in an active state or a precharge state when the access request is made. Processing unit c

1 1. In claim 10,

The memory control circuit, when the access request is made, when a memory bank corresponding to the bank address is in an active state, the plurality of memory banks in a selected state among the memory banks in the active state. An information processing apparatus including a second determination circuit that determines whether one of the lead lines matches the row address included in the access request.

1 2. In claim 1,

The information processing device further includes a hard disk device,

The information processing apparatus according to claim 1, wherein the first master is a CPU, and the second master is a hard disk controller coupled to a hard disk device.

1 3. In claim 1,

Each of the plurality of memory banks of the memory block includes a plurality of memory cells provided at intersections of a plurality of read lines and a plurality of data lines, each including a serially connected MOS transistor and a capacitor. , The information processing apparatus according to claim 1, wherein the first master is a CPU, and the second master is a refresh controller of the memory block.

14. A plurality of first nodes for outputting an access command and an access address for a memory block including a plurality of memory punctures, and the first and second masters capable of accessing the memory block. A semiconductor device including a memory control circuit having a plurality of second nodes.

The memory control circuit, when an access request signal from the first master is input to the plurality of second nodes, transmits a signal for accessing one of the plurality of memory banks in a first procedure to the plurality of second nodes. To output one of the plurality of memory banks in the second procedure when an access request signal from the second master is input to the plurality of second nodes. A semiconductor device having an access control switching circuit for outputting the signal from the plurality of first nodes.

15. In claim 14,

The memory control circuit controls each of the plurality of memory banks including a plurality of memory cells and a plurality of data latch circuits provided at intersections of a plurality of read lines and a plurality of data lines. The memory control circuit reads the data from the selected memory cell in the first procedure when the access request signal is a data read request signal from one of the plurality of memory banks. After the predetermined data is held in the plurality of data latch circuits and output to the first master, an instruction signal for holding the data in the plurality of data latch circuits is output. After holding the predetermined data read from the cell in the plurality of data latch circuits and outputting the data to the second master, the plurality of data latch circuits are output. Command to clear the data held in the switch circuit. A semiconductor integrated circuit including a command generation circuit for outputting.

1 6. A plurality of masters, an access arbitration circuit that arbitrates access from the plurality of masters, a DRAM, and a memory system that controls reading and writing Z from the DRAM by access from the access arbitration circuit. With a control circuit,

The memory control circuit includes: a control signal switching circuit that switches a control signal provided for each of the plurality of masters that accesses the DRAM according to the identification signals of the plurality of masters; and a signal from the control signal switching circuit. And a circuit for switching the control operation of the DRAM according to the above.

1 7. In claim 16,

Information characterized in that the control signal can be set freely from an external terminal

1 8. In claim 16,

The plurality of masters are individually formed for each of a plurality of first semiconductor chips, the access arbitration circuit is formed on a second semiconductor chip, the memory control circuit is formed on a third semiconductor chip, and the DR AM is an information processing device including a DRAM memory chip formed on a fourth semiconductor chip.

1 9. In claim 16,

The plurality of masters are individually formed for each of a plurality of first semiconductor chips, the access arbitration circuit and the memory control circuit are formed on a second semiconductor chip, and the DRAM is formed on a third semiconductor chip. An information processing device comprising a DRAM memory chip.

20. In claim 16,

The plurality of masters are individually formed for each of the plurality of first semiconductor chips. The information arbitration circuit is formed on a second semiconductor chip, and the memory control circuit and the DRAM are formed on a third semiconductor chip.