WO2001067500A2 - Methods for making nearly planar dielectric films in integrated circuits - Google Patents

Methods for making nearly planar dielectric films in integrated circuits Download PDF

Info

Publication number
WO2001067500A2
WO2001067500A2 PCT/US2001/007336 US0107336W WO0167500A2 WO 2001067500 A2 WO2001067500 A2 WO 2001067500A2 US 0107336 W US0107336 W US 0107336W WO 0167500 A2 WO0167500 A2 WO 0167500A2
Authority
WO
WIPO (PCT)
Prior art keywords
metal
forming
layer
pattern
deposition rate
Prior art date
Application number
PCT/US2001/007336
Other languages
French (fr)
Other versions
WO2001067500A3 (en
Inventor
Werner Juengling
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to JP2001566176A priority Critical patent/JP2004501503A/en
Priority to AU2001249109A priority patent/AU2001249109A1/en
Publication of WO2001067500A2 publication Critical patent/WO2001067500A2/en
Publication of WO2001067500A3 publication Critical patent/WO2001067500A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31695—Deposition of porous oxides or porous glassy oxides or oxide based porous glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body

Definitions

  • the present invention concerns methods of making integrated circuits, particularly methods of making metal masks and dielectric, or insulative, films.
  • Integrated circuits the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically build the circuits layer by layer, using techniques, such as doping, masking, and etching, to form thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then wired, or interconnected, together to define a specific electric circuit, such as a computer memory.
  • planarity significantly affects the accuracy of a photo-imaging process, known as photomasking or photolithography, which entails focusing light on light-sensitive materials to define specific patterns or structures in a layer of an integrated circuit.
  • photomasking or photolithography which entails focusing light on light-sensitive materials to define specific patterns or structures in a layer of an integrated circuit.
  • the presence of hills and valleys in a layer forces various regions of the layer out of focus, causing photo-imaged features to be smaller or larger than intended.
  • hills and valleys can reflect light undesirably onto other regions of a layer and add undesirable features, such as notches, to desired features.
  • Chemical-mechanical planarization typically entails applying a fluid containing abrasive particles to a surface of an integrated circuit, and polishing the surface with a rotating polishing head. The process is used frequently to planarize the insulative, or dielectric, layers that lie between layers of metal wiring in integrated circuits. These insulative layers, which typically consist of silicon dioxide, are sometimes called intermetal dielectric layers. In conventional integrated-circuit fabrication, planarization of these layers is necessary because each insulative layer tends to follow the hills and valleys of the underlying metal wiring, similar to the way a bed sheet follows the contours of whatever it covers. Thus, fabricators generally deposit an insulative layer much thicker than necessary to cover the metal wiring and then planarize the insulative layer to remove the hills and valleys.
  • a first exemplary method of the invention forms a metal layer with a predetermined maximum feature spacing and then uses a TEOS-based (tetraethyl-orthosilicate-based) oxide deposition procedure to form an oxide film having nearly planar or quasi-planar characteristics.
  • the exemplary method executes a CVD (chemical vapor deposition) TEOS oxide procedure to form an oxide layer on a metal layer having a maximum feature spacing of 0.2-0.5 microns.
  • a second exemplary method includes voids within the oxide, or more generally insulative, film to improve its effective dielectric constant and thus improve its ability to prevent shorting and crosstalk between metal wiring.
  • the exemplary method uses a TEOS process at a non-conformal rate sufficient to encourage the formation of voids, and then uses the TEOS process at a conformal rate of deposition to seal the voids. More generally, however, the invention uses a non-conformal deposition procedure to encourage formation of voids and then a more conformal deposition to seal the voids.
  • a third exemplary method increases the metal-fill density of metal patterns to facilitate formation of intermetal dielectric layers having more uniform thicknesses.
  • the third exemplary method adds floating metal to open areas in a metal layout and then extends non-floating metal dimensions according to an iterative procedure that entails filling in notches, and corners and moving selected edges of the layout.
  • Figure 1 is a cross-sectional view of a partial integrated-circuit assembly 10 including a substrate 12 and metal wires 14a, 14b, and 14c;
  • Figure 2 is a cross-sectional view of the Figure 1 integrated-circuit assembly after formation of a substantially planar insulative layer 16, including a portion 16a with voids and a portion 16b without voids;
  • Figure 3 is a cross-sectional view of the Figure 2 assembly after a facet etch to improve the planarity of layer 16;
  • Figure 4 is a cross-sectional view of the Figure 3 assembly after formation of metal wires 18a and 18b, and substantially planar insulative layer 20, including a portion 20a with voids and a portion 20b without voids;
  • Figure 5 is a cross-sectional view of a partial integrated-circuit assembly 21 including a substrate 22 and metal wires 24a, 24b, and 24c;
  • Figure 6 is a cross-sectional view of the Figure 5 assembly after formation of an oxide spacer 26 and a substantially planar insulative layer 28, including a portion 28a with voids and a portion 28b without voids;
  • Figure 7 is a cross-sectional view of the Figure 6 assembly after a facet etch to improve the planarity of layer 28
  • Figure 8 is a cross-sectional view of the Figure 7 assembly after formation of metal wires 30a and 30b, and substantially planar insulative layer 34, including a portion 34a with voids and a portion 34b without voids;
  • Figure 9 is a cross-sectional view of a partial integrated-circuit assembly 35 including a substrate 36 and metal wires 36a, 36b, and 36c;
  • Figure 10 is a cross-sectional view of the Figure 9 assembly after formation of an oxide spacer 40 and a substantially planar insulative layer 42;
  • Figure 11 is a flow chart illustrating an exemplary method of modifying a metal layout to facilitate fabrication of intermetal dielectric layers with more uniform thickness
  • Figure 12 is a partial top view of a metal layout showing how the exemplary method of Figure 11 adds metal to open areas in a metal layout;
  • Figure 13 is a partial top view of a metal layout showing how the exemplary method of Figure 11 fills notches in a metal layout
  • Figure 14 is a partial top view of a metal layout showing how the exemplary method of Figure 11 fills corners in a metal layout
  • Figure 15 is a partial view of a metal layout showing how the exemplary method of Figure 11 fills in between opposing edges of live metal regions in a metal layout
  • Figure 16 is a partial view of a metal layout showing how the exemplary method of Figure 11 moves edges
  • Figure 17 is a block diagram of an exemplary computer system 42 for hosting and executing a software implementation of the exemplary pattern- filling method of Figure 11; and Figure 18 is a simplified schematic diagram of an exemplary integrated memory circuit 50 that incorporates one or more nearly planar intermetal dielectric layers and/ or metal layers made in accord with exemplary methods of the invention.
  • Figures 1-4 show a number of exemplary integrated-circuit assemblies, which taken collectively and sequentially, illustrate an exemplary method of making nearly planar or quasi planar dielectric films, or layers, within the scope of the present invention.
  • a quasi planar film is globally planar with local nonplanarities having slopes less than or equal to 45 degrees and depths less than the thickness of the next metal layer to be deposited. The local nonplanarities typically occur over the gaps between underlying metal features.
  • the method begins with formation of an integrated-circuit assembly or structure 10, which can exist within any integrated circuit, for example, an integrated memory circuit.
  • Assembly 10 includes a substrate 12.
  • substrate encompasses a semiconductor wafer as well as structures having one or more insulative, semi-insulative, conductive, or semiconductive layers and materials. Thus, for example, the term embraces silicon-on-insulator, silicon-on-sapphire, and other advanced structures.
  • Substrate 12 includes three representative wires or conductive structures
  • wires 14a-14c are approximately 3000-6000 angstroms thick and comprise metals, such as aluminum, gold, or silver, and nonmetals, such as heavily doped polysilicon. Spacing 14s, in the exemplary embodiment, is 0.3 microns.
  • Wires 14a- 14c can be formed using any number of methods, for example, photolithography and dry etching.
  • the exemplary embodiment forms a lateral-etch-resistant layer, that is, a layer resistant to lateral etching, on a metal layer before etching.
  • suitable layers include a TEOS, oxide-nitride layer.
  • Figure 2 shows that the exemplary method next entails forming an insulative layer 16 over substrate 12 and wires 14a- 14b.
  • Layer 16 has a thickness 16t of, for example, 6000 angstroms, and includes two layers or sublayers 16a and 16b.
  • Sublayer 16a includes a number of voids, particularly voids 17 between wires 14a and 14b, and between wires 14b and 14c, to increase its dielectric constant.
  • Sublayer 16b is either substantially voidless or includes a substantially fewer number of voids than sublayer 16a. The presence of voids in sublayer 16a reduces lateral electrical coupling between adjacent metal features, for example, between wires 14a and 14b and between wires 14a- 14c and any overlying conductive structures.
  • the exemplary method forms layer 16 using a combination of a non- conformal and conformal oxide depositions.
  • a CND TEOS chemical vapor deposition tetraethyl-orthosilicate
  • PECND TEOS plasma- enhanced CVD TEOS oxide deposition process
  • a non-conformal deposition rate to form void- filled sublayer 16a voids
  • a conformal rate to form substantially voidless sublayer 16b.
  • Figure 3 shows that after forming sublayer 16b, which includes some level of nonplanarity, the exemplary method facet etches the sublayer at an angle of about 45 degrees to improve its global planarity. (That layer 16b has undergone further processing is highlighted by its new reference numeral 16b'.)
  • the facet etch reduces or smooths any sharp trenches in regions overlying gaps between metal features, such as wires 14a-14c.
  • face etch refers to any etch process that etches substantially faster in the horizontal direction than in the vertical direction.
  • the term includes an angled sputter etch or reactive- ion etch.
  • Figure 4 shows the results of forming a second metallization level according to the procedure outlined in Figures 1-3. In brief, this entails forming conductive structures 18a and 18b on insulative sublayer 16b' and forming an insulative layer 20 on sublayer 16b' and conductive structures 18a and 18b. Insulative layer 20, like insulative layer 16, includes void-filled sublayer 20a and substantially void- free sublayer 20b'. Sublayer 20a includes one or more voids 19 between conductive structures 18a and 18b. Sublayer 20b' was facet etch to improve its planarity. Layer 20 has a thickness 20t, of for example 3000-6000 angstroms.
  • Figures 5-8 show a number of exemplary integrated-circuit assemblies, which taken collectively and sequentially, illustrate a second exemplary method of making nearly planar or quasi planar dielectric layers within the scope of the present invention.
  • the second method is particularly applicable to maximum metal feature spacing greater than about 0.3 microns or oxide thickness less than 6000 angstroms to allow for shallow via formation, that is, via depths less than about 4000 angstroms.
  • Figure 5 shows that the method begins with formation of an integrated-circuit assembly or structure 21, which, like assembly 10 in Figure 1, can exist within any integrated circuit.
  • Assembly 10 includes a substrate 22 which supports three representative wires or conductive structures 24a, 24b, and 24c, with a desired feature spacing 24s.
  • spacing 24s is greater than 0.3 microns.
  • Some embodiments set a minimum spacing of 0.17 microns.
  • the present invention is not limited to any particular spacing.
  • Figure 6 shows that the exemplary method next entails forming an insulative spacer 26 and an insulative layer 28.
  • Insulative spacers 26 which consists of silicon dioxide for example, lies over portions of substrate 22 adjacent wires 24a-24c to reduce the effective separation of wires 24a-24c.
  • the exemplary method uses a TEOS oxide deposition and subsequent etching to form spacers 26.
  • Insulative layer 28 has a thickness 28t of, for example, 4000 angstroms, and includes two sublayers 28a and 28b, analogous to sublayers 16a and 16b in the first embodiment.
  • sublayer 28a includes a number of voids 27 between the wires to increase its dielectric constant
  • sublayer 28b is either substantially voidless or includes a substantially fewer number of voids than sublayer 28a.
  • a two-stage TEOS oxide deposition process similar to that used in the first embodiment, is used to form layer 28.
  • Figure 7 shows that after forming sublayer 28b, which includes some level of nonplanarity, the exemplary method facet etches the sublayer at an angle of about 45 degrees to improve its global planarity.
  • Figure 8 shows the results of forming a second metallization level according to the procedure outlined in Figures 5-7.
  • This entails forming conductive structures 30a and 30b on insulative sublayer 28b' and forming an insulative spacer 32 and an insulative layer 34, which, like insulative layer 28, includes void-filled sublayer 34a and substantially void- free sublayer 34b'.
  • Sublayer 34a includes voids 31 between conductive structures 30a and 30b, and sublayer 34b' is facet etched to improve its planarity.
  • Figures 9 and 10 show a number of exemplary integrated-circuit assemblies, which taken collectively and sequentially, illustrate a third exemplary method of making nearly planar or quasi planar dielectric layers within the scope of the present invention.
  • the third exemplary embodiment is intended for forming insulative films on metal layers with maximum feature spacing up to about 0.5 microns.
  • Figure 9 shows that the method begins with formation of an integrated- circuit assembly or structure 35, which like assembly 10 in Figure 1 and assembly 21 in Figure 5, can exist within any integrated circuit.
  • Assembly 35 includes a substrate 36 which supports three representative wires or conductive structures 38a, 38b, and 38c, with a desired feature spacing 38s of about 0.5 microns.
  • Figure 10 shows the results of forming an oxide spacers 40 and an insulative layer 42.
  • the exemplary embodiment forms one or more oxide spacers 40 which is about 1000 angstroms wide, and thus reduces the effective spacing between conductors 38a-38c by 2000 angstroms.
  • Forming insulative layer 42 entails executing a flow-fill procedure, such as TRIKON-200 by Trikon Technologies, Inc. To obtain global and local planarity, one can reduce the maximum feature space by using oxide/TEOS spacer as taught in the second exemplary method, or by enlarging the metal feature, or by adding floating metal between the metal features. Exemplary Method of Promoting Uniform Thickness of Intermetal Dielectric Layers
  • the inventor developed specific methods of (and related computer software) for increasing the pattern density of metal layouts.
  • the methods and associated software take a given metal layout and modify, or fill, open areas of the layout to increase pattern density and thus promote uniform thickness or reduce thickness variation across dielectric layers formed on metal layers based on the layouts. These methods and software can thus be used, for example, to facilitate formation of the conductive structures shown in Figures 1, 5, and 9.
  • the exemplary method generally entails iteratively measuring a given layout, adding floating metal to fill large open areas in the layout, and extending or filling out existing metal areas to meet maximum feature spacing, or gap, criteria.
  • Figure 11 shows a flow chart of the exemplary method, which is suitable for implementation as a computer-executable program.
  • the flow chart includes a number of process or decision blocks 110, 120, 130, and 140.
  • the exemplary method begins at process block 110 which entails measuring a given layout. This entails determining open (unmetallized or nonconductive) areas large enough to be filled with floating metal and identifying live metal areas that require additional metal to obtain desired spacing. Floating metal is metal that is not coupled to a signal path or component, whereas live metal is metal that is coupled to a signal path or component.
  • the exemplary method proceeds to block 120 which entails adding floating metal to any large areas identified in block 110.
  • Figure 12 shows a hypothetical layout having a live metal region 200 with open area 210.
  • the exemplary method adds floating metal, such as floating metal region 220.
  • the exemplary method After adding floating metal, the exemplary method adds live metal as indicated in block 120 of Figure 11. Figure 12 is again instructive of the exemplary method. If dimension B is less than the sum of dimension SI, dimension S2, and L, the exemplary method adds metal as indicated by added active metal region 230. process block 104 which entails filling in notches in the layout. More particularly, the exemplary method follows an iterative process for adding live (or non-floating) metal, as indicated by blocks 130a-130g.
  • Block 130a entails filling notches in the current live metal.
  • Figure 13 shows a live metal region 300 of a hypothetical metal layout having a notch 310. Included within notch 310 are a series of iteratively added live metal regions 320-325. The amount of metal added at each iteration can be selected using a minimum surface area criteria or computed dynamically each iteration. The exemplary embodiment repeatedly adds metal to the notch until it is filled, before advancing to block 310b. However, other embodiments can advance to block 310b before the notch is filled, relying on subsequent trips or iterations through the first loop in the flowchart to complete filling of the notch.
  • Block 130b entails filling in corners in the current live metal, meaning the live metal after filling notches.
  • Figure 14 illustrates a live metal region 400 having a corner 410 and added L-shaped live metal regions 420-423 and a rectangular live metal region 424. (Other embodiments add other shapes of live metal regions.)
  • the amount of metal added at each iteration can be selected using a minimum surface area or single-dimensional criteria or computed dynamically each iteration.
  • the exemplary embodiment repeatedly adds metal to the corner until it is filled, before advancing to block 130c. However, other embodiments can advance to block 310b before the notch is filled, relying on subsequent trips through the inner loop to complete filling of the notch.
  • Block 130c entails filling in between opposing edges of adjacent live metal regions to achieve a desired spacing, such as a maximum desired spacing L.
  • Figure 15 shows live metal regions 510 and 520, which have respective opposing edges 510a and 520a.
  • the exemplary method entails adding live metal regions, such as live metal regions 521-523, one edge such as edge 520a to achieved the maximum desired spacing L.
  • other embodiments add live metal to both of the opposing edges to achieve the desired spacing.
  • Still other embodiments look at the lengths of the opposing edges and use one or both of the lengths to determine one or more dimensions of the added live metal regions.
  • decision block 130d in Figure 11 This block entails determining whether more live metal can be added. More precisely, this entails measuring the layout as modified by the live metal already added and determining whether there are any adjacent regions that violate the desired maximum spacing criteria. (Note that some exemplary embodiments include more than one maximum spacing criteria to account for areas where capacitive effects or crosstalk issues are of greater importance than others.) If the determination indicates that more metal can be added execution proceeds back to block 130a to fill in remaining notches, and so forth. If the determination indicates that no more live metal can be added to satisfy the maximum spacing criteria, execution to proceeds to block 130e in Figure 11.
  • Block 130e entails moving (or redefining) one or more edges (or portions of edges) of live metal regions in the modified layout specification.
  • Figure 16 shows live metal regions 610 and 620, which have respective edges 610a and 620a. It also shows the addition of live metal region 630 to edge 620a, which effectively extends the edge. Similarly, edge 620a has been extended with the iterative addition of live metal regions 631 and 632. The additions can be made iteratively using a dynamic or static step size, or all it once by computing the size of an optimal addition to each edge. Exemplary execution then proceeds to decision block 130f.
  • decision block 130f the exemplary method decides again whether more metal can be added to the layout. If more metal can be added, the exemplary method repeats execution of process blocks 104-122. However, if no metal can be added, the method proceeds to process block 140 to output the modified layout for use in a fabrication process.
  • the exemplary method performs data compaction to minimize or reduce the amount of layout data carried forward from iteration to iteration.
  • Data compaction reduces the number of cells which define the circuit associated with the metal layout and the computing power necessary to create the metal layout.
  • the exemplary compaction scheme flattens all array placement into single instance placements. For example, a single array placement of a cell incorporating a 3x4 matrix flattens to 12 instances of a single cell. It also flattens specific cells, such as array core cells, vias, or contacts, based on layout or user settings. Additionally, it flattens cells which contain less than a predetermined number of shapes regardless of any other effects. For example, one can flatten cells having less than 10, 20, or 40 shapes.
  • the exemplary compaction scheme attempts to merge shapes to minimize overlapping shapes and redundant data.
  • the appropriate or optimum degree of flattening depends largely on the processing power and memory capabilities of the computer executing the exemplary method. Faster computers with more core memory and swap space can handle larger number of shapes per cell and thus have less need for flattening than slower computers with less core memory and swap space. In the extreme, a complete circuit layout can be flattened into one cell.
  • a given layout design is not a single flat list of shapes but includes two or more cells placed into each other as instances, additional precaution should be taken to reduce the risk of introducing unintended shorts into the layout during the pattern- fill process.
  • this entails managing the hierarchy of cells.
  • the exemplary embodiment implements a hierarchy management process which recognizes that each cell has an associated fill area that will not change throughout the metal-fill process.
  • the exemplary management process entails executing the following steps from the bottom up until all cell dependencies are resolved. For each instance in each cell, the process creates a temporary unique copy of the cell associated with a given instance. After this, the process copies metal from other cells into the cell being examined if it falls into the fill area. The process then copies metal from other cell into the cell if the metal falls into a ring around the fill area. Next, the process identifies, extracts, and marks conflict areas.
  • This exemplary pattern-filling method and other simpler or more complex methods embodying one or more filling techniques of the exemplary embodiment can be used in combination with the methods of making nearly planar intermetal dielectric layers described using Figures 1-10. More precisely, one can use a pattern-filling method according to the invention to define a layout for a particular metal layer, form a metal layer based on the layout, and then form a nearly planar intermetal dielectric layer according to the invention on the metal layer. The combination of these methods promises to yield not only a nearly planar dielectric layer that reduces or avoids the need for chemical- mechanical planarization, but also a dielectric layer with less thickness deviation because of the adjusted pattern fill density of the underlying metal layer.
  • Exemplary Computer System Incorporating Pattern-Filling Method Figure 17 shows an exemplary computer system or workstation 42 for hosting and executing a software implementation of the exemplary pattern-filling method.
  • the most pertinent features of system 42 include a processor 44, a local memory 45 and a data-storage device 46. Additionally, system 42 includes display devices 47 and user-interface devices 48. Some embodiments use distributed processors or parallel processors, and other embodiments use one or more of the following data-storage devices: a read-only memory (ROM), a random-access-memory (RAM), an electrically-erasable and programmable- read-only memory (EEPROM), an optical disk, or a floppy disk.
  • Exemplary display devices include a color monitor
  • exemplary user-interface devices include a keyboard, mouse, joystick, or microphone.
  • the invention is not limited to any genus or species of computerized platforms.
  • Data-storage device 46 includes layout-development software 46a, pattern-filling software 46b, an exemplary input metal layout 46c, and an exemplary output metal layout 46d.
  • Software 46a and 46b can be installed on system 42 separately or in combination through a network-download or through a computer-readable medium, such as an optical or magnetic disc, or through other software transfer methods.
  • Exemplary storage devices include hard disk drives, optical disk drives, or floppy disk drives.
  • software 46b is an add-on tool to layout-development software 46a and layout 46c was developed using software 46a.
  • software 46b operates as a separate application program and layout 46c was developed by non-resident layout-development software.
  • General examples of suitable layout-development software are available from Cadence and Mentor Graphics.. Thus, the invention is not limited to any particular genus or species of layout-development software.
  • Exemplary Integrated Memory Circuit Figure 18 shows an exemplary integrated memory circuit 50 that incorporates one or more nearly planar intermetal dielectric layers and/or metal layers within the scope of the present invention.
  • One more memory circuits resembling circuit 50 can be used in a variety of computer or computerized systems, such as system 42 of Figure 17.
  • Memory circuit 50 which operates according to well-known and understood principles, is generally coupled to a processor (not shown) to form a computer system. More particularly, circuit 50 includes a memory array 52, which comprises a number of memory cells 53a, 53b, 53c, and 53d; a column address decoder 54, and a row address decoder 55; bit lines 56a and 56b; word lines 57a and 57b; and voltage-sense-amplifier circuit 58 coupled in conventional fashion to bit lines 56a and 56b. (For clarity, Figure 18 omits many conventional elements of a memory circuit.)

Abstract

In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers - the insulative layers sandwiched between layers of metal wiring - in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.

Description

METHODS FOR MAKING NEARLY PLANAR DIELECTRIC FILMS
IN INTEGRATED CIRCUITS
Related Application
This application is a continuation of U.S. Provisional Application 60/187,658, which was filed on March 7, 2000 and which is incorporated herein by reference.
Technical Field The present invention concerns methods of making integrated circuits, particularly methods of making metal masks and dielectric, or insulative, films. Background of the Invention
Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically build the circuits layer by layer, using techniques, such as doping, masking, and etching, to form thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then wired, or interconnected, together to define a specific electric circuit, such as a computer memory.
One important concern during fabrication is flatness, or planarity, of various layers of the integrated circuit. For example, planarity significantly affects the accuracy of a photo-imaging process, known as photomasking or photolithography, which entails focusing light on light-sensitive materials to define specific patterns or structures in a layer of an integrated circuit. In this process, the presence of hills and valleys in a layer forces various regions of the layer out of focus, causing photo-imaged features to be smaller or larger than intended. Moreover, hills and valleys can reflect light undesirably onto other regions of a layer and add undesirable features, such as notches, to desired features. These problems can be largely avoided if the layer is sufficiently planar.
One process for making surfaces flat or planar is known as chemical- mechanical planarization or polishing. Chemical-mechanical planarization typically entails applying a fluid containing abrasive particles to a surface of an integrated circuit, and polishing the surface with a rotating polishing head. The process is used frequently to planarize the insulative, or dielectric, layers that lie between layers of metal wiring in integrated circuits. These insulative layers, which typically consist of silicon dioxide, are sometimes called intermetal dielectric layers. In conventional integrated-circuit fabrication, planarization of these layers is necessary because each insulative layer tends to follow the hills and valleys of the underlying metal wiring, similar to the way a bed sheet follows the contours of whatever it covers. Thus, fabricators generally deposit an insulative layer much thicker than necessary to cover the metal wiring and then planarize the insulative layer to remove the hills and valleys.
Unfortunately, conventional methods of forming these intermetal dielectric layers suffer from at least two problems. First, the process of chemical-mechanical planarization is not only relatively costly but also quite time consuming. And second, the thickness of these layers generally varies considerably from point to point because of underlying wiring. Occasionally, the thickness variation leaves metal wiring under a layer too close to metal wiring on the layer, encouraging shorting or crosstalking. Crosstalk, a phenomenon that also occurs in telephone systems, occurs when signals from one wire are undesirable transferred or communicated to another nearby wire. Accordingly, the art needs fabrication methods that reduce the need to planarize intermetal dielectric layers, that reduce thickness variation in these layers, and that improve their electrical properties generally.
Summary of the Invention To address these and other needs, the inventor devised various methods of making dielectric layers on metal layers, which reduce the need for chemical- mechanical planarization procedure. Specifically, a first exemplary method of the invention forms a metal layer with a predetermined maximum feature spacing and then uses a TEOS-based (tetraethyl-orthosilicate-based) oxide deposition procedure to form an oxide film having nearly planar or quasi-planar characteristics. The exemplary method executes a CVD (chemical vapor deposition) TEOS oxide procedure to form an oxide layer on a metal layer having a maximum feature spacing of 0.2-0.5 microns. A second exemplary method includes voids within the oxide, or more generally insulative, film to improve its effective dielectric constant and thus improve its ability to prevent shorting and crosstalk between metal wiring. Specifically, the exemplary method uses a TEOS process at a non-conformal rate sufficient to encourage the formation of voids, and then uses the TEOS process at a conformal rate of deposition to seal the voids. More generally, however, the invention uses a non-conformal deposition procedure to encourage formation of voids and then a more conformal deposition to seal the voids.
A third exemplary method increases the metal-fill density of metal patterns to facilitate formation of intermetal dielectric layers having more uniform thicknesses. The third exemplary method adds floating metal to open areas in a metal layout and then extends non-floating metal dimensions according to an iterative procedure that entails filling in notches, and corners and moving selected edges of the layout. Brief Description of the Drawings
Figure 1 is a cross-sectional view of a partial integrated-circuit assembly 10 including a substrate 12 and metal wires 14a, 14b, and 14c;
Figure 2 is a cross-sectional view of the Figure 1 integrated-circuit assembly after formation of a substantially planar insulative layer 16, including a portion 16a with voids and a portion 16b without voids;
Figure 3 is a cross-sectional view of the Figure 2 assembly after a facet etch to improve the planarity of layer 16;
Figure 4 is a cross-sectional view of the Figure 3 assembly after formation of metal wires 18a and 18b, and substantially planar insulative layer 20, including a portion 20a with voids and a portion 20b without voids;
Figure 5 is a cross-sectional view of a partial integrated-circuit assembly 21 including a substrate 22 and metal wires 24a, 24b, and 24c;
Figure 6 is a cross-sectional view of the Figure 5 assembly after formation of an oxide spacer 26 and a substantially planar insulative layer 28, including a portion 28a with voids and a portion 28b without voids;
Figure 7 is a cross-sectional view of the Figure 6 assembly after a facet etch to improve the planarity of layer 28; Figure 8 is a cross-sectional view of the Figure 7 assembly after formation of metal wires 30a and 30b, and substantially planar insulative layer 34, including a portion 34a with voids and a portion 34b without voids;
Figure 9 is a cross-sectional view of a partial integrated-circuit assembly 35 including a substrate 36 and metal wires 36a, 36b, and 36c;
Figure 10 is a cross-sectional view of the Figure 9 assembly after formation of an oxide spacer 40 and a substantially planar insulative layer 42;
Figure 11 is a flow chart illustrating an exemplary method of modifying a metal layout to facilitate fabrication of intermetal dielectric layers with more uniform thickness;
Figure 12 is a partial top view of a metal layout showing how the exemplary method of Figure 11 adds metal to open areas in a metal layout;
Figure 13 is a partial top view of a metal layout showing how the exemplary method of Figure 11 fills notches in a metal layout; Figure 14 is a partial top view of a metal layout showing how the exemplary method of Figure 11 fills corners in a metal layout;
Figure 15 is a partial view of a metal layout showing how the exemplary method of Figure 11 fills in between opposing edges of live metal regions in a metal layout; Figure 16 is a partial view of a metal layout showing how the exemplary method of Figure 11 moves edges;
Figure 17 is a block diagram of an exemplary computer system 42 for hosting and executing a software implementation of the exemplary pattern- filling method of Figure 11; and Figure 18 is a simplified schematic diagram of an exemplary integrated memory circuit 50 that incorporates one or more nearly planar intermetal dielectric layers and/ or metal layers made in accord with exemplary methods of the invention.
Description of the Preferred Embodiments The following detailed description, which references and incorporates the above-identified Figures, describes and illustrates specific embodiments of the invention. These embodiments, offered not to limit but only to exemplify and teach the invention, are shown and described in sufficient detail to enable those skilled in the art to implement or practice the invention. Thus, where appropriate to avoid obscuring the invention, the description may omit certain information known to those of skill in the art.
First Exemplary Method of Forming Nearly Planar Dielectric Films Figures 1-4 show a number of exemplary integrated-circuit assemblies, which taken collectively and sequentially, illustrate an exemplary method of making nearly planar or quasi planar dielectric films, or layers, within the scope of the present invention. As used herein, a quasi planar film is globally planar with local nonplanarities having slopes less than or equal to 45 degrees and depths less than the thickness of the next metal layer to be deposited. The local nonplanarities typically occur over the gaps between underlying metal features.
The method, as shown in Figure 1 , a cross-sectional view, begins with formation of an integrated-circuit assembly or structure 10, which can exist within any integrated circuit, for example, an integrated memory circuit. Assembly 10 includes a substrate 12. The term "substrate," as used herein, encompasses a semiconductor wafer as well as structures having one or more insulative, semi-insulative, conductive, or semiconductive layers and materials. Thus, for example, the term embraces silicon-on-insulator, silicon-on-sapphire, and other advanced structures. Substrate 12 includes three representative wires or conductive structures
14a, 14b, and 14c, with a maximum (or average) feature spacing 14s. In the exemplary embodiment, wires 14a-14c are approximately 3000-6000 angstroms thick and comprise metals, such as aluminum, gold, or silver, and nonmetals, such as heavily doped polysilicon. Spacing 14s, in the exemplary embodiment, is 0.3 microns.
Wires 14a- 14c can be formed using any number of methods, for example, photolithography and dry etching. To avoid increasing feature spacing during dry etching, the exemplary embodiment forms a lateral-etch-resistant layer, that is, a layer resistant to lateral etching, on a metal layer before etching. Examples of suitable layers include a TEOS, oxide-nitride layer. Alternatively, one can add extensive serif features to the metal mask layout to avoid large open areas, especially to reduce the diagonal distance between features. Figure 2 shows that the exemplary method next entails forming an insulative layer 16 over substrate 12 and wires 14a- 14b. Layer 16 has a thickness 16t of, for example, 6000 angstroms, and includes two layers or sublayers 16a and 16b. Sublayer 16a includes a number of voids, particularly voids 17 between wires 14a and 14b, and between wires 14b and 14c, to increase its dielectric constant. Sublayer 16b is either substantially voidless or includes a substantially fewer number of voids than sublayer 16a. The presence of voids in sublayer 16a reduces lateral electrical coupling between adjacent metal features, for example, between wires 14a and 14b and between wires 14a- 14c and any overlying conductive structures.
The exemplary method forms layer 16 using a combination of a non- conformal and conformal oxide depositions. In particular, it uses a CND TEOS (chemical vapor deposition tetraethyl-orthosilicate) or PECND TEOS (plasma- enhanced CVD TEOS) oxide deposition process at a non-conformal deposition rate to form void- filled sublayer 16a voids and then lowers the TEOS deposition rate to, a conformal rate to form substantially voidless sublayer 16b.
Figure 3 shows that after forming sublayer 16b, which includes some level of nonplanarity, the exemplary method facet etches the sublayer at an angle of about 45 degrees to improve its global planarity. (That layer 16b has undergone further processing is highlighted by its new reference numeral 16b'.) The facet etch reduces or smooths any sharp trenches in regions overlying gaps between metal features, such as wires 14a-14c. As used herein, the term "facet etch" refers to any etch process that etches substantially faster in the horizontal direction than in the vertical direction. Thus, for example, the term includes an angled sputter etch or reactive- ion etch.
To optimize the slopes of any vias, one can perform the facet etch before via printing. More specifically, one can facet etch after etching any necessary vias and stripping photoresist to produce vias having greater slope and smoothness. Figure 4 shows the results of forming a second metallization level according to the procedure outlined in Figures 1-3. In brief, this entails forming conductive structures 18a and 18b on insulative sublayer 16b' and forming an insulative layer 20 on sublayer 16b' and conductive structures 18a and 18b. Insulative layer 20, like insulative layer 16, includes void-filled sublayer 20a and substantially void- free sublayer 20b'. Sublayer 20a includes one or more voids 19 between conductive structures 18a and 18b. Sublayer 20b' was facet etch to improve its planarity. Layer 20 has a thickness 20t, of for example 3000-6000 angstroms.
Second Exemplary Method of Forming Nearly Planar Dielectric Films Figures 5-8 show a number of exemplary integrated-circuit assemblies, which taken collectively and sequentially, illustrate a second exemplary method of making nearly planar or quasi planar dielectric layers within the scope of the present invention. The second method is particularly applicable to maximum metal feature spacing greater than about 0.3 microns or oxide thickness less than 6000 angstroms to allow for shallow via formation, that is, via depths less than about 4000 angstroms.
More particularly, Figure 5 shows that the method begins with formation of an integrated-circuit assembly or structure 21, which, like assembly 10 in Figure 1, can exist within any integrated circuit. Assembly 10 includes a substrate 22 which supports three representative wires or conductive structures 24a, 24b, and 24c, with a desired feature spacing 24s. In the exemplary embodiment, spacing 24s is greater than 0.3 microns. Some embodiments set a minimum spacing of 0.17 microns. However, the present invention is not limited to any particular spacing.
Figure 6 shows that the exemplary method next entails forming an insulative spacer 26 and an insulative layer 28. Insulative spacers 26, which consists of silicon dioxide for example, lies over portions of substrate 22 adjacent wires 24a-24c to reduce the effective separation of wires 24a-24c. The exemplary method uses a TEOS oxide deposition and subsequent etching to form spacers 26. Insulative layer 28 has a thickness 28t of, for example, 4000 angstroms, and includes two sublayers 28a and 28b, analogous to sublayers 16a and 16b in the first embodiment. Specifically, sublayer 28a includes a number of voids 27 between the wires to increase its dielectric constant, and sublayer 28b is either substantially voidless or includes a substantially fewer number of voids than sublayer 28a. A two-stage TEOS oxide deposition process, similar to that used in the first embodiment, is used to form layer 28. Figure 7 shows that after forming sublayer 28b, which includes some level of nonplanarity, the exemplary method facet etches the sublayer at an angle of about 45 degrees to improve its global planarity.
Figure 8 shows the results of forming a second metallization level according to the procedure outlined in Figures 5-7. This entails forming conductive structures 30a and 30b on insulative sublayer 28b' and forming an insulative spacer 32 and an insulative layer 34, which, like insulative layer 28, includes void-filled sublayer 34a and substantially void- free sublayer 34b'. Sublayer 34a includes voids 31 between conductive structures 30a and 30b, and sublayer 34b' is facet etched to improve its planarity.
Third Exemplary Method of Forming Nearly Planar Dielectric Films Figures 9 and 10 show a number of exemplary integrated-circuit assemblies, which taken collectively and sequentially, illustrate a third exemplary method of making nearly planar or quasi planar dielectric layers within the scope of the present invention. In contrast to the first and second embodiment, the third exemplary embodiment is intended for forming insulative films on metal layers with maximum feature spacing up to about 0.5 microns.
Figure 9 shows that the method begins with formation of an integrated- circuit assembly or structure 35, which like assembly 10 in Figure 1 and assembly 21 in Figure 5, can exist within any integrated circuit. Assembly 35 includes a substrate 36 which supports three representative wires or conductive structures 38a, 38b, and 38c, with a desired feature spacing 38s of about 0.5 microns.
Figure 10 shows the results of forming an oxide spacers 40 and an insulative layer 42. The exemplary embodiment forms one or more oxide spacers 40 which is about 1000 angstroms wide, and thus reduces the effective spacing between conductors 38a-38c by 2000 angstroms. Forming insulative layer 42 entails executing a flow-fill procedure, such as TRIKON-200 by Trikon Technologies, Inc. To obtain global and local planarity, one can reduce the maximum feature space by using oxide/TEOS spacer as taught in the second exemplary method, or by enlarging the metal feature, or by adding floating metal between the metal features. Exemplary Method of Promoting Uniform Thickness of Intermetal Dielectric Layers
To facilitate the formation of more uniformly thick inter-metal dielectric layers, such as those described above, the inventor developed specific methods of (and related computer software) for increasing the pattern density of metal layouts. The methods and associated software take a given metal layout and modify, or fill, open areas of the layout to increase pattern density and thus promote uniform thickness or reduce thickness variation across dielectric layers formed on metal layers based on the layouts. These methods and software can thus be used, for example, to facilitate formation of the conductive structures shown in Figures 1, 5, and 9.
The exemplary method generally entails iteratively measuring a given layout, adding floating metal to fill large open areas in the layout, and extending or filling out existing metal areas to meet maximum feature spacing, or gap, criteria. Figure 11 shows a flow chart of the exemplary method, which is suitable for implementation as a computer-executable program.
Specifically, the flow chart includes a number of process or decision blocks 110, 120, 130, and 140. The exemplary method begins at process block 110 which entails measuring a given layout. This entails determining open (unmetallized or nonconductive) areas large enough to be filled with floating metal and identifying live metal areas that require additional metal to obtain desired spacing. Floating metal is metal that is not coupled to a signal path or component, whereas live metal is metal that is coupled to a signal path or component. After executing block 110, the exemplary method proceeds to block 120 which entails adding floating metal to any large areas identified in block 110.
To illustrate, Figure 12 shows a hypothetical layout having a live metal region 200 with open area 210. In general, if dimension A is greater than the sum of dimension SI, dimension S2, and L (the maximum feature spacing criteria), the exemplary method adds floating metal, such as floating metal region 220.
After adding floating metal, the exemplary method adds live metal as indicated in block 120 of Figure 11. Figure 12 is again instructive of the exemplary method. If dimension B is less than the sum of dimension SI, dimension S2, and L, the exemplary method adds metal as indicated by added active metal region 230. process block 104 which entails filling in notches in the layout. More particularly, the exemplary method follows an iterative process for adding live (or non-floating) metal, as indicated by blocks 130a-130g.
Block 130a entails filling notches in the current live metal. Figure 13 shows a live metal region 300 of a hypothetical metal layout having a notch 310. Included within notch 310 are a series of iteratively added live metal regions 320-325. The amount of metal added at each iteration can be selected using a minimum surface area criteria or computed dynamically each iteration. The exemplary embodiment repeatedly adds metal to the notch until it is filled, before advancing to block 310b. However, other embodiments can advance to block 310b before the notch is filled, relying on subsequent trips or iterations through the first loop in the flowchart to complete filling of the notch.
Block 130b entails filling in corners in the current live metal, meaning the live metal after filling notches. Figure 14 illustrates a live metal region 400 having a corner 410 and added L-shaped live metal regions 420-423 and a rectangular live metal region 424. (Other embodiments add other shapes of live metal regions.) The amount of metal added at each iteration can be selected using a minimum surface area or single-dimensional criteria or computed dynamically each iteration. The exemplary embodiment repeatedly adds metal to the corner until it is filled, before advancing to block 130c. However, other embodiments can advance to block 310b before the notch is filled, relying on subsequent trips through the inner loop to complete filling of the notch.
Block 130c entails filling in between opposing edges of adjacent live metal regions to achieve a desired spacing, such as a maximum desired spacing L. Figure 15 shows live metal regions 510 and 520, which have respective opposing edges 510a and 520a. The exemplary method entails adding live metal regions, such as live metal regions 521-523, one edge such as edge 520a to achieved the maximum desired spacing L. However, other embodiments add live metal to both of the opposing edges to achieve the desired spacing. Still other embodiments look at the lengths of the opposing edges and use one or both of the lengths to determine one or more dimensions of the added live metal regions.
After filling in between opposing edges of existing live metal regions, the exemplary method advances to decision block 130d in Figure 11. This block entails determining whether more live metal can be added. More precisely, this entails measuring the layout as modified by the live metal already added and determining whether there are any adjacent regions that violate the desired maximum spacing criteria. (Note that some exemplary embodiments include more than one maximum spacing criteria to account for areas where capacitive effects or crosstalk issues are of greater importance than others.) If the determination indicates that more metal can be added execution proceeds back to block 130a to fill in remaining notches, and so forth. If the determination indicates that no more live metal can be added to satisfy the maximum spacing criteria, execution to proceeds to block 130e in Figure 11. Block 130e entails moving (or redefining) one or more edges (or portions of edges) of live metal regions in the modified layout specification. To illustrate, Figure 16 shows live metal regions 610 and 620, which have respective edges 610a and 620a. It also shows the addition of live metal region 630 to edge 620a, which effectively extends the edge. Similarly, edge 620a has been extended with the iterative addition of live metal regions 631 and 632. The additions can be made iteratively using a dynamic or static step size, or all it once by computing the size of an optimal addition to each edge. Exemplary execution then proceeds to decision block 130f.
In decision block 130f, the exemplary method decides again whether more metal can be added to the layout. If more metal can be added, the exemplary method repeats execution of process blocks 104-122. However, if no metal can be added, the method proceeds to process block 140 to output the modified layout for use in a fabrication process.
Although not show explicitly in the exemplary flow chart in Figure 11 , the exemplary method performs data compaction to minimize or reduce the amount of layout data carried forward from iteration to iteration. Data compaction reduces the number of cells which define the circuit associated with the metal layout and the computing power necessary to create the metal layout. The exemplary compaction scheme flattens all array placement into single instance placements. For example, a single array placement of a cell incorporating a 3x4 matrix flattens to 12 instances of a single cell. It also flattens specific cells, such as array core cells, vias, or contacts, based on layout or user settings. Additionally, it flattens cells which contain less than a predetermined number of shapes regardless of any other effects. For example, one can flatten cells having less than 10, 20, or 40 shapes. Lastly, the exemplary compaction scheme attempts to merge shapes to minimize overlapping shapes and redundant data. The appropriate or optimum degree of flattening depends largely on the processing power and memory capabilities of the computer executing the exemplary method. Faster computers with more core memory and swap space can handle larger number of shapes per cell and thus have less need for flattening than slower computers with less core memory and swap space. In the extreme, a complete circuit layout can be flattened into one cell.
If a given layout design is not a single flat list of shapes but includes two or more cells placed into each other as instances, additional precaution should be taken to reduce the risk of introducing unintended shorts into the layout during the pattern- fill process. In the exemplary embodiment, this entails managing the hierarchy of cells.
The exemplary embodiment implements a hierarchy management process which recognizes that each cell has an associated fill area that will not change throughout the metal-fill process. The exemplary management process entails executing the following steps from the bottom up until all cell dependencies are resolved. For each instance in each cell, the process creates a temporary unique copy of the cell associated with a given instance. After this, the process copies metal from other cells into the cell being examined if it falls into the fill area. The process then copies metal from other cell into the cell if the metal falls into a ring around the fill area. Next, the process identifies, extracts, and marks conflict areas.
This exemplary pattern-filling method and other simpler or more complex methods embodying one or more filling techniques of the exemplary embodiment can be used in combination with the methods of making nearly planar intermetal dielectric layers described using Figures 1-10. More precisely, one can use a pattern-filling method according to the invention to define a layout for a particular metal layer, form a metal layer based on the layout, and then form a nearly planar intermetal dielectric layer according to the invention on the metal layer. The combination of these methods promises to yield not only a nearly planar dielectric layer that reduces or avoids the need for chemical- mechanical planarization, but also a dielectric layer with less thickness deviation because of the adjusted pattern fill density of the underlying metal layer. Exemplary Computer System Incorporating Pattern-Filling Method Figure 17 shows an exemplary computer system or workstation 42 for hosting and executing a software implementation of the exemplary pattern-filling method. The most pertinent features of system 42 include a processor 44, a local memory 45 and a data-storage device 46. Additionally, system 42 includes display devices 47 and user-interface devices 48. Some embodiments use distributed processors or parallel processors, and other embodiments use one or more of the following data-storage devices: a read-only memory (ROM), a random-access-memory (RAM), an electrically-erasable and programmable- read-only memory (EEPROM), an optical disk, or a floppy disk. Exemplary display devices include a color monitor, and exemplary user-interface devices include a keyboard, mouse, joystick, or microphone. Thus, the invention is not limited to any genus or species of computerized platforms.
Data-storage device 46 includes layout-development software 46a, pattern-filling software 46b, an exemplary input metal layout 46c, and an exemplary output metal layout 46d. (Software 46a and 46b can be installed on system 42 separately or in combination through a network-download or through a computer-readable medium, such as an optical or magnetic disc, or through other software transfer methods.) Exemplary storage devices include hard disk drives, optical disk drives, or floppy disk drives. In the exemplary embodiment, software 46b is an add-on tool to layout-development software 46a and layout 46c was developed using software 46a. However, in other embodiments, software 46b operates as a separate application program and layout 46c was developed by non-resident layout-development software. General examples of suitable layout-development software are available from Cadence and Mentor Graphics.. Thus, the invention is not limited to any particular genus or species of layout-development software.
Exemplary Integrated Memory Circuit Figure 18 shows an exemplary integrated memory circuit 50 that incorporates one or more nearly planar intermetal dielectric layers and/or metal layers within the scope of the present invention. One more memory circuits resembling circuit 50 can be used in a variety of computer or computerized systems, such as system 42 of Figure 17.
Memory circuit 50, which operates according to well-known and understood principles, is generally coupled to a processor (not shown) to form a computer system. More particularly, circuit 50 includes a memory array 52, which comprises a number of memory cells 53a, 53b, 53c, and 53d; a column address decoder 54, and a row address decoder 55; bit lines 56a and 56b; word lines 57a and 57b; and voltage-sense-amplifier circuit 58 coupled in conventional fashion to bit lines 56a and 56b. (For clarity, Figure 18 omits many conventional elements of a memory circuit.)
Conclusion In furtherance of the art, the inventor has presented several methods for making nearly planar intermetal dielectric layers without the use of chemical- mechanical planarization. Additionally, the inventor has presented a method of modifying metal layouts to facilitate formation of dielectric films with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness. The embodiments described above are intended only to illustrate and teach one or more ways of practicing or implementing the present invention, not to restrict its breadth or scope. The actual scope of the invention, which embraces all ways of practicing or implementing the invention, is defined only by the following claims and their equivalents.

Claims

Claims
1. A method of forming a nearly planar dielectric film on a metal layer, comprising: forming a metal layer having a predetermined maximum feature spacing; forming an oxide layer on the metal layer using a TEOS-based procedure; facet-etching the oxide layer; and reflowing at least a portion of the oxide layer.
2. The method of claim 1, wherein forming the metal layer comprises forming metal layer with a maximum feature spacing of 0.3 microns.
3. The method of claim 1, wherein forming the metal layer comprises forming metal runners and wherein forming the oxide layer forms oxide on one or more sidewalls of the metal runners.
4. The method of claim 1, wherein forming the oxide layer comprises forming a portion of the oxide layer using a TEOS-based procedure at a first deposition rate and forming a portion of the oxide layer using a TEOS-based procedure at a second deposition rate which is less than the first deposition rate.
5. The method of claim 1, wherein forming the oxide layer comprises forming a portion of the oxide layer using a TEOS-based procedure at a first deposition rate having a tendency to form voids and forming a portion of the oxide layer using a TEOS-based procedure at a second deposition rate having a tendency to form substantially no voids or fewer voids than the first deposition rate.
6. The method of claim 1, further comprising facet etching the oxide layer to reduce severity of any trenches in oxide layer overlying gaps between metal features in the metal layer.
7. A method of forming a nearly planar dielectric film on a metal layer, comprising: forming a metal layer having a predetermined maximum feature spacing of 0.3 microns; forming a first oxide layer using a TEOS-based procedure at a first deposition rate on the metal layer; forming a second oxide layer on the first oxide layer using a TEOS-based procedure at a second deposition rate which is less than the first deposition rate; and facet etching the second oxide layer.
8. A method of forming a nearly planar dielectric film on a metal layer, comprising: forming a metal layer; depositing a film resistant to lateral etching on the metal layer; etching the metal layer to form a metal pattern having a predetermined maximum feature spacing of 0.3 microns; forming a first oxide layer using a TEOS-based procedure at a first deposition rate on the metal pattern; forming a second oxide layer on the first oxide layer using a TEOS-based procedure at a second deposition rate which is less than the first deposition rate; and facet etching the second oxide layer.
9. A method of forming a nearly planar dielectric film on a metal layer, comprising: forming a metal layer; depositing a film resistant to lateral etching on the metal layer; etching the metal layer to form a metal pattern having a predetermined maximum feature spacing; forming two or more oxide spacers on two or more metal features of the metal layer to provide an effective space less than about the predetermined maximum feature spacing between two or more oxide spacers; forming a first oxide layer using a TEOS-based procedure at a first deposition rate on the metal pattern; forming a second oxide layer on the first oxide layer using a TEOS-based procedure at a second deposition rate which is less than the first deposition rate; and facet etching the second oxide layer.
10. A method of forming a nearly planar dielectric film on a metal layer, comprising: forming a metal layer including two or more metal features spaced with a maximum feature spacing greater than 0.3 microns; forming a oxide spacer on the two or more metal features to provide oxide features spaced by less than the maximum feature spacing; and forming an oxide layer on the metal layer having a thickness less than about 6000 angstroms using a TEOS-based procedure.
11. The method of claim 10, wherein forming the oxide layer comprises forming a portion of the oxide layer using a TEOS-based procedure at a first deposition rate and forming a portion of the oxide layer using a TEOS-based procedure at a second deposition rate which is less than the first deposition rate.
12. The method of claim 10, wherein forming the oxide layer comprises forming a portion of the oxide layer using a TEOS-based procedure at a first deposition rate having a tendency to form voids and forming a portion of the oxide layer using a TEOS-based procedure at a second deposition rate having a tendency to form fewer voids than the first deposition rate.
13. The method of claim 10, further comprising facet etching the oxide layer to reduce severity of any trenches in oxide layer overlying gaps between metal features in the metal layer.
14. The method of claim 10, wherein forming an oxide layer on the metal layer having a thickness less than about 6000 angstroms using a TEOS-based procedure comprises forming an oxide layer having a thickness less than about 4000 angstroms.
15. A method of making nearly planar dielectric films on a metal layer, where maximum feature spacing cannot be reduced because of lateral electrical coupling concerns, the method comprising: forming a metal pattern with maximum feature spacing of about five microns; forming an oxide spacer on one or more metal features of the metal layer to provide an effective space less than about five microns; and executing a FLOW-FILL procedure to form a substantially void- free oxide layer on the metal layer and the oxide spacer.
16. The method of claim 15, wherein forming the metal pattern includes forming a metal layer; depositing a film resistant to lateral etching on the metal layer; and etching the metal layer to form the metal pattern.
17. The method of claim 16, wherein the film resistant to lateral etching is a TEOS, oxide-nitride film.
18. The method of claim 15 , wherein forming the metal pattern includes forming a pattern including extensive serif features to avoid large open areas.
19. A method of making a dielectric layer, comprising: depositing a dielectric material at a first deposition rate having a tendency to form voids; and depositing a dielectric material on the deposited dielectric material at a second deposition rate having a tendency to form substantially no voids or fewer voids than the first deposition rate.
20. A method of making a dielectric layer, comprising: depositing a dielectric material at a first deposition rate; and depositing a dielectric material on the deposited dielectric material at a second deposition rate less than the first deposition rate.
21. A method of making a dielectric layer, comprising: depositing a dielectric material using a deposition process having a first conformal tendency; and depositing a dielectric material on the deposited dielectric material using a deposition process having a second conformal tendency greater than the first conformal tendency.
22. The method of claim 21 : wherein depositing a dielectric material using a deposition process having a first conformal tendency comprises depositing a dielectric material using a TEOS-based procedure at a first deposition rate; and wherein depositing a dielectric material using a deposition process having a second conformal tendency comprises depositing a dielectric material using a TEOS-based procedure at a second deposition rate lower than the first deposition rate.
23. A method of making an integrated circuit, comprising: providing a first metal layout having a first pattern fill density; generating a metal layout pattern based on the first metal layout and having a second pattern fill density greater than the first pattern fill density; forming a metal pattern on a layer; depositing a dielectric material on the metal pattern using a deposition process having a first conformal tendency; and depositing a dielectric material on the deposited dielectric material using a deposition process having a second conformal tendency greater than the first conformal tendency.
24. A method of making an integrated circuit, comprising: providing a first metal layout having a first pattern fill density; generating a metal layout pattern based on the first metal layout and having a second pattern fill density greater than the first pattern fill density; forming a metal pattern on a layer; depositing a dielectric material on the metal pattern at a first deposition rate; and depositing a dielectric material on the deposited dielectric material at a second deposition rate less than the first deposition rate.
25. A method of making an integrated circuit, comprising: providing a first metal layout having a first pattern fill density; generating a metal layout pattern based on the first metal layout and having a second pattern fill density greater than the first pattern fill density; forming a metal pattern on a layer; forming a first oxide layer on the metal pattern using a TEOS-based procedure at a first deposition rate; and forming a second oxide layer on the first oxide layer using a TEOS-based procedure at a second deposition rate lower than the first deposition rate.
26. A method of increasing pattern- fill density of a metal layout, comprising: identifying and filling in open areas of the metal layout with floating metal; identifying and filling in notches of the metal layout; and identifying and filling in corners of the metal layout.
27. A method of increasing pattern-fill density of a metal layout, comprising: identifying and filling in one or more open areas of the metal layout with floating metal; identifying and filling in one or more notches of the metal layout after identifying and filling in one or more open areas; and identifying and filling in one or more corners of the metal layout after filling in one or more notches.
28. A method of increasing pattern-fill density of a metal layout, comprising: identifying and filling in one or more notches of the metal layout; identifying and filling in one or more corners of the metal layout; and identifying and filling in between opposing edges of live metal regions of the metal layout.
29. A method of increasing pattern- fill density of a hierarchical metal layout pattern definition, comprising: identifying and filling in one or more notches, inner lines, and corners of the metal layout to define a first derivative metal layout pattern definition; determining whether the first derivative metal layout pattern definition has a predetermined pattern fill density; identifying and filling in one or more notches and corners of the metal layout to define a second derivative metal layout pattern definition; determining whether the second derivative metal layout pattern definition has the predetermined pattern fill density; and redefining one or more edges of the second derivative metal layout in response to determining that the second derivative metal layout does not have the predetermined pattern fill density.
30. A computer-readable medium comprising: instructions for identifying and filling in one or more notches, inner lines, and corners of the metal layout to define a first derivative metal layout pattern definition; and instructions for determining whether the first derivative metal layout pattern definition has a predetermined pattern fill density;
31. A computer-readable medium comprising: instructions for identifying and filling in one or more predetermined forms of non-metallic regions of a metal layout pattern definition to define a derivative metal layout pattern definition; and instructions for determining whether the derivative metal layout pattern definition has a predetermined pattern fill density.
32. A system comprising: at least one processor; and a memory coupled to the processor and comprising: instructions for identifying and filling in one or more notches and corners of the metal layout to define a first derivative metal layout pattern definition; and instructions for determining whether the first derivative metal layout pattern definition has a predetermined pattern fill density;
33. An integrated circuit comprising: one or more conductors; a first insulative layer which is substantially free of voids and which contacts the one or more conductors; a second insulative layer which lies on the first insulative layer and which includes a substantial number of voids.
34. The integrated circuit of claim 33, wherein the first and second insulative layer consist essentially of silicon oxide and have substantially different dielectric constants.
35. An integrated memory circuit comprising: one or more memory cells; one or more conductors coupled to the one or more memory cells; a first insulative layer which is substantially free of voids and which contacts the one or more conductors; and a second insulative layer which lies on the first insulative layer and which includes a substantial number of voids.
36. The integrated memory circuit of claim 35, wherein the first and second insulative layers consist essentially of silicon oxide and have substantially different dielectric constants.
37. A system comprising: a processor; and at least one integrated memory circuit comprising: one or more memory cells; one or more conductors coupled to the one or more memory cells; a first insulative layer which is substantially free of voids and which contacts the one or more conductors; and a second insulative layer which lies on the first insulative layer and which includes a substantial number of voids.
38. The system of claim 37, wherein the first and second insulative layers consist essentially of silicon oxide and have substantially different dielectric constants.
39. The system of claim 1, wherein the processor is a digital signal processor.
PCT/US2001/007336 2000-03-07 2001-03-07 Methods for making nearly planar dielectric films in integrated circuits WO2001067500A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001566176A JP2004501503A (en) 2000-03-07 2001-03-07 Method of forming almost flat insulating film in integrated circuit
AU2001249109A AU2001249109A1 (en) 2000-03-07 2001-03-07 Methods for making nearly planar dielectric films in integrated circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18765800P 2000-03-07 2000-03-07
US60/187,658 2000-03-07

Publications (2)

Publication Number Publication Date
WO2001067500A2 true WO2001067500A2 (en) 2001-09-13
WO2001067500A3 WO2001067500A3 (en) 2002-02-14

Family

ID=22689906

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/007336 WO2001067500A2 (en) 2000-03-07 2001-03-07 Methods for making nearly planar dielectric films in integrated circuits

Country Status (5)

Country Link
US (6) US6627549B2 (en)
JP (2) JP2004501503A (en)
KR (1) KR100530296B1 (en)
AU (1) AU2001249109A1 (en)
WO (1) WO2001067500A2 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627549B2 (en) * 2000-03-07 2003-09-30 Micron Technology, Inc. Methods for making nearly planar dielectric films in integrated circuits
US7135734B2 (en) 2001-08-30 2006-11-14 Micron Technology, Inc. Graded composition metal oxide tunnel barrier interpoly insulators
US6780762B2 (en) * 2002-08-29 2004-08-24 Micron Technology, Inc. Self-aligned, integrated circuit contact and formation method
US6737346B2 (en) * 2002-08-29 2004-05-18 Micron Technology, Inc. Integrated circuit with modified metal features and method of fabrication therefor
JP4387654B2 (en) * 2002-10-10 2009-12-16 パナソニック株式会社 Semiconductor device and manufacturing method thereof
US7364997B2 (en) 2005-07-07 2008-04-29 Micron Technology, Inc. Methods of forming integrated circuitry and methods of forming local interconnects
US7544612B1 (en) * 2006-01-20 2009-06-09 Skyworks Solutions, Inc. Method and structure for reducing the effect of vertical steps in patterned layers in semiconductor structures
US7557002B2 (en) * 2006-08-18 2009-07-07 Micron Technology, Inc. Methods of forming transistor devices
US7648921B2 (en) * 2006-09-22 2010-01-19 Macronix International Co., Ltd. Method of forming dielectric layer
US7989322B2 (en) * 2007-02-07 2011-08-02 Micron Technology, Inc. Methods of forming transistors
US7723227B1 (en) * 2009-03-24 2010-05-25 Micron Technology, Inc. Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry
US7989336B2 (en) * 2009-05-06 2011-08-02 Micron Technology, Inc. Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry
US8507304B2 (en) * 2009-07-17 2013-08-13 Applied Materials, Inc. Method of forming a group III-nitride crystalline film on a patterned substrate by hydride vapor phase epitaxy (HVPE)
US8575000B2 (en) * 2011-07-19 2013-11-05 SanDisk Technologies, Inc. Copper interconnects separated by air gaps and method of making thereof
JP6011340B2 (en) 2011-08-05 2016-10-19 住友電気工業株式会社 Substrate, semiconductor device and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0766291A1 (en) * 1995-08-01 1997-04-02 Texas Instruments Incorporated Integrated circuit insulator and method
US5776834A (en) * 1995-06-07 1998-07-07 Advanced Micro Devices, Inc. Bias plasma deposition for selective low dielectric insulation
US5814555A (en) * 1996-06-05 1998-09-29 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to lessen capacitive coupling
US5858876A (en) * 1996-04-01 1999-01-12 Chartered Semiconductor Manufacturing, Ltd. Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer
US5872058A (en) * 1997-06-17 1999-02-16 Novellus Systems, Inc. High aspect ratio gapfill process by using HDP
US6030881A (en) * 1998-05-05 2000-02-29 Novellus Systems, Inc. High throughput chemical vapor deposition process capable of filling high aspect ratio structures

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051917A (en) * 1987-02-24 1991-09-24 International Business Machines Corporation Method of combining gate array and standard cell circuits on a common semiconductor chip
US5304505A (en) * 1989-03-22 1994-04-19 Emanuel Hazani Process for EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells
US6109775A (en) * 1991-07-19 2000-08-29 Lsi Logic Corporation Method for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereon
US5252520A (en) * 1991-10-31 1993-10-12 At&T Bell Laboratories Integrated circuit interlevel dielectric wherein the first and second dielectric layers are formed with different densities
US5441915A (en) * 1992-09-01 1995-08-15 Taiwan Semiconductor Manufacturing Company Ltd. Process of fabrication planarized metallurgy structure for a semiconductor device
US5503882A (en) 1994-04-18 1996-04-02 Advanced Micro Devices, Inc. Method for planarizing an integrated circuit topography
US5461003A (en) 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US5552996A (en) * 1995-02-16 1996-09-03 International Business Machines Corporation Method and system using the design pattern of IC chips in the processing thereof
US5636133A (en) * 1995-05-19 1997-06-03 International Business Machines Corporation Efficient generation of fill shapes for chips and packages
US5597668A (en) * 1995-07-19 1997-01-28 Vlsi Technology, Inc. Patterned filled photo mask generation for integrated circuit manufacturing
US5641712A (en) * 1995-08-07 1997-06-24 Motorola, Inc. Method and structure for reducing capacitance between interconnect lines
US5518959A (en) * 1995-08-24 1996-05-21 Taiwan Semiconductor Manufacturing Company Method for selectively depositing silicon oxide spacer layers
US5763955A (en) * 1996-07-01 1998-06-09 Vlsi Technology, Inc. Patterned filled layers for integrated circuit manufacturing
US6599847B1 (en) 1996-08-27 2003-07-29 Taiwan Semiconductor Manufacturing Company Sandwich composite dielectric layer yielding improved integrated circuit device reliability
US5790417A (en) * 1996-09-25 1998-08-04 Taiwan Semiconductor Manufacturing Company Ltd. Method of automatic dummy layout generation
US5923563A (en) * 1996-12-20 1999-07-13 International Business Machines Corporation Variable density fill shape generation
US5854125A (en) * 1997-02-24 1998-12-29 Vlsi Technology, Inc. Dummy fill patterns to improve interconnect planarity
US6100205A (en) 1997-04-02 2000-08-08 United Microelectronics Corp. Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process
US5968610A (en) * 1997-04-02 1999-10-19 United Microelectronics Corp. Multi-step high density plasma chemical vapor deposition process
US6080672A (en) 1997-08-20 2000-06-27 Micron Technology, Inc. Self-aligned contact formation for semiconductor devices
US6081272A (en) * 1997-09-30 2000-06-27 Intel Corporation Merging dummy structure representations for improved distribution of artifacts in a semiconductor layer
US6251470B1 (en) 1997-10-09 2001-06-26 Micron Technology, Inc. Methods of forming insulating materials, and methods of forming insulating materials around a conductive component
US6136687A (en) 1997-11-26 2000-10-24 Integrated Device Technology, Inc. Method of forming air gaps for reducing interconnect capacitance
US6087724A (en) * 1997-12-18 2000-07-11 Advanced Micro Devices, Inc. HSQ with high plasma etching resistance surface for borderless vias
US6093631A (en) * 1998-01-15 2000-07-25 International Business Machines Corporation Dummy patterns for aluminum chemical polishing (CMP)
US5949143A (en) * 1998-01-22 1999-09-07 Advanced Micro Devices, Inc. Semiconductor interconnect structure with air gap for reducing intralayer capacitance in metal layers in damascene metalization process
US6189130B1 (en) * 1998-04-30 2001-02-13 International Business Machines Corporation System and method for determining density maps in hierarchical designs
US6223331B1 (en) 1998-07-30 2001-04-24 Micron Technology, Inc. Semiconductor circuit design method for employing spacing constraints and circuits thereof
US6274479B1 (en) * 1998-08-21 2001-08-14 Micron Technology, Inc Flowable germanium doped silicate glass for use as a spacer oxide
US6262435B1 (en) * 1998-12-01 2001-07-17 Marina V. Plat Etch bias distribution across semiconductor wafer
US6319818B1 (en) * 1999-01-04 2001-11-20 International Business Machines Corporation Pattern factor checkerboard for planarization
US6691297B1 (en) * 1999-03-04 2004-02-10 Matsushita Electric Industrial Co., Ltd. Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI
US6255162B1 (en) * 1999-03-16 2001-07-03 United Microelectronics Corp. Method of gap filling
US6305000B1 (en) * 1999-06-15 2001-10-16 International Business Machines Corporation Placement of conductive stripes in electronic circuits to satisfy metal density requirements
US6396158B1 (en) * 1999-06-29 2002-05-28 Motorola Inc. Semiconductor device and a process for designing a mask
US6174808B1 (en) 1999-08-04 2001-01-16 Taiwan Semiconductor Manufacturing Company Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS
US6323113B1 (en) * 1999-12-10 2001-11-27 Philips Electronics North America Corporation Intelligent gate-level fill methods for reducing global pattern density effects
US6436807B1 (en) * 2000-01-18 2002-08-20 Agere Systems Guardian Corp. Method for making an interconnect layer and a semiconductor device including the same
US6627549B2 (en) * 2000-03-07 2003-09-30 Micron Technology, Inc. Methods for making nearly planar dielectric films in integrated circuits
US6531412B2 (en) * 2001-08-10 2003-03-11 International Business Machines Corporation Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5776834A (en) * 1995-06-07 1998-07-07 Advanced Micro Devices, Inc. Bias plasma deposition for selective low dielectric insulation
EP0766291A1 (en) * 1995-08-01 1997-04-02 Texas Instruments Incorporated Integrated circuit insulator and method
US5858876A (en) * 1996-04-01 1999-01-12 Chartered Semiconductor Manufacturing, Ltd. Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer
US5814555A (en) * 1996-06-05 1998-09-29 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to lessen capacitive coupling
US5872058A (en) * 1997-06-17 1999-02-16 Novellus Systems, Inc. High aspect ratio gapfill process by using HDP
US6030881A (en) * 1998-05-05 2000-02-29 Novellus Systems, Inc. High throughput chemical vapor deposition process capable of filling high aspect ratio structures

Also Published As

Publication number Publication date
US20060246736A1 (en) 2006-11-02
US20060261435A1 (en) 2006-11-23
US7125800B2 (en) 2006-10-24
US20060001022A1 (en) 2006-01-05
KR20020080474A (en) 2002-10-23
WO2001067500A3 (en) 2002-02-14
US6627549B2 (en) 2003-09-30
US20010053612A1 (en) 2001-12-20
AU2001249109A1 (en) 2001-09-17
US20050023695A1 (en) 2005-02-03
US20040061196A1 (en) 2004-04-01
JP2007189236A (en) 2007-07-26
US7235865B2 (en) 2007-06-26
JP2004501503A (en) 2004-01-15
KR100530296B1 (en) 2005-11-22

Similar Documents

Publication Publication Date Title
US20060246736A1 (en) Methods for making nearly planar dielectric films in integrated circuits
US5790417A (en) Method of automatic dummy layout generation
US5789313A (en) Process for producing a semiconductor device with a planar top surface
JP2548888B2 (en) Method for manufacturing semiconductor device
US5212114A (en) Process for global planarizing of surfaces for integrated semiconductor circuits
CN100375267C (en) Method for manufacturing semiconductor devices
US20100252907A1 (en) Shallow Trench Isolation Dummy Pattern and Layout Method Using the Same
US5580826A (en) Process for forming a planarized interlayer insulating film in a semiconductor device using a periodic resist pattern
EP0304077A2 (en) Method of forming a fine pattern
US6232043B1 (en) Rule to determine CMP polish time
US6448183B1 (en) Method of forming contact portion of semiconductor element
KR100460064B1 (en) Method for forming metal wiring of semiconductor device
JP2000012538A (en) Manufacture of semiconductor device
US7279267B2 (en) Method for manipulating the topography of a film surface
JPH04359544A (en) Formation method of flat wiring layer
JPH0974136A (en) Manufacture for semiconductor device
KR20010035659A (en) A method of reducing capacitance in semiconductor devices
US6326310B1 (en) Method and system for providing shallow trench profile shaping through spacer and etching
JPH0677182A (en) Flattening method of rugged insulating film
KR20030049571A (en) Method for forming metal line of semiconductor device using dual-damascene process
KR100756864B1 (en) forming method of insulator for semiconductor device
KR20010063640A (en) Method for forming interlayer dielectric of semiconductor device
JPH03151636A (en) Flattening method for insulating film
JPH06252141A (en) Manufacture of semiconductor device
JPH0225251B2 (en)

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 1020027011717

Country of ref document: KR

ENP Entry into the national phase

Ref country code: JP

Ref document number: 2001 566176

Kind code of ref document: A

Format of ref document f/p: F

WWP Wipo information: published in national office

Ref document number: 1020027011717

Country of ref document: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
WWG Wipo information: grant in national office

Ref document number: 1020027011717

Country of ref document: KR