WO2001067500A3 - Methods for making nearly planar dielectric films in integrated circuits - Google Patents

Methods for making nearly planar dielectric films in integrated circuits Download PDF

Info

Publication number
WO2001067500A3
WO2001067500A3 PCT/US2001/007336 US0107336W WO0167500A3 WO 2001067500 A3 WO2001067500 A3 WO 2001067500A3 US 0107336 W US0107336 W US 0107336W WO 0167500 A3 WO0167500 A3 WO 0167500A3
Authority
WO
WIPO (PCT)
Prior art keywords
methods
dielectric layers
integrated circuits
making
nearly planar
Prior art date
Application number
PCT/US2001/007336
Other languages
French (fr)
Other versions
WO2001067500A2 (en
Inventor
Werner Juengling
Original Assignee
Micron Technology Inc
Werner Juengling
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Werner Juengling filed Critical Micron Technology Inc
Priority to JP2001566176A priority Critical patent/JP2004501503A/en
Priority to AU2001249109A priority patent/AU2001249109A1/en
Publication of WO2001067500A2 publication Critical patent/WO2001067500A2/en
Publication of WO2001067500A3 publication Critical patent/WO2001067500A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31695—Deposition of porous oxides or porous glassy oxides or oxide based porous glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers - the insulative layers sandwiched between layers of metal wiring - in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.
PCT/US2001/007336 2000-03-07 2001-03-07 Methods for making nearly planar dielectric films in integrated circuits WO2001067500A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001566176A JP2004501503A (en) 2000-03-07 2001-03-07 Method of forming almost flat insulating film in integrated circuit
AU2001249109A AU2001249109A1 (en) 2000-03-07 2001-03-07 Methods for making nearly planar dielectric films in integrated circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18765800P 2000-03-07 2000-03-07
US60/187,658 2000-03-07

Publications (2)

Publication Number Publication Date
WO2001067500A2 WO2001067500A2 (en) 2001-09-13
WO2001067500A3 true WO2001067500A3 (en) 2002-02-14

Family

ID=22689906

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/007336 WO2001067500A2 (en) 2000-03-07 2001-03-07 Methods for making nearly planar dielectric films in integrated circuits

Country Status (5)

Country Link
US (6) US6627549B2 (en)
JP (2) JP2004501503A (en)
KR (1) KR100530296B1 (en)
AU (1) AU2001249109A1 (en)
WO (1) WO2001067500A2 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627549B2 (en) * 2000-03-07 2003-09-30 Micron Technology, Inc. Methods for making nearly planar dielectric films in integrated circuits
US7135734B2 (en) 2001-08-30 2006-11-14 Micron Technology, Inc. Graded composition metal oxide tunnel barrier interpoly insulators
US6737346B2 (en) * 2002-08-29 2004-05-18 Micron Technology, Inc. Integrated circuit with modified metal features and method of fabrication therefor
US6780762B2 (en) 2002-08-29 2004-08-24 Micron Technology, Inc. Self-aligned, integrated circuit contact and formation method
JP4387654B2 (en) * 2002-10-10 2009-12-16 パナソニック株式会社 Semiconductor device and manufacturing method thereof
US7364997B2 (en) 2005-07-07 2008-04-29 Micron Technology, Inc. Methods of forming integrated circuitry and methods of forming local interconnects
US7544612B1 (en) * 2006-01-20 2009-06-09 Skyworks Solutions, Inc. Method and structure for reducing the effect of vertical steps in patterned layers in semiconductor structures
US7557002B2 (en) * 2006-08-18 2009-07-07 Micron Technology, Inc. Methods of forming transistor devices
US7648921B2 (en) * 2006-09-22 2010-01-19 Macronix International Co., Ltd. Method of forming dielectric layer
US7989322B2 (en) 2007-02-07 2011-08-02 Micron Technology, Inc. Methods of forming transistors
US7723227B1 (en) 2009-03-24 2010-05-25 Micron Technology, Inc. Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry
US7989336B2 (en) * 2009-05-06 2011-08-02 Micron Technology, Inc. Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry
US8507304B2 (en) * 2009-07-17 2013-08-13 Applied Materials, Inc. Method of forming a group III-nitride crystalline film on a patterned substrate by hydride vapor phase epitaxy (HVPE)
US8575000B2 (en) 2011-07-19 2013-11-05 SanDisk Technologies, Inc. Copper interconnects separated by air gaps and method of making thereof
DE112012003260T5 (en) 2011-08-05 2014-05-15 Sumitomo Electric Industries, Ltd. Substrate, semiconductor device and method of making the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0766291A1 (en) * 1995-08-01 1997-04-02 Texas Instruments Incorporated Integrated circuit insulator and method
US5776834A (en) * 1995-06-07 1998-07-07 Advanced Micro Devices, Inc. Bias plasma deposition for selective low dielectric insulation
US5814555A (en) * 1996-06-05 1998-09-29 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to lessen capacitive coupling
US5858876A (en) * 1996-04-01 1999-01-12 Chartered Semiconductor Manufacturing, Ltd. Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer
US5872058A (en) * 1997-06-17 1999-02-16 Novellus Systems, Inc. High aspect ratio gapfill process by using HDP
US6030881A (en) * 1998-05-05 2000-02-29 Novellus Systems, Inc. High throughput chemical vapor deposition process capable of filling high aspect ratio structures

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051917A (en) * 1987-02-24 1991-09-24 International Business Machines Corporation Method of combining gate array and standard cell circuits on a common semiconductor chip
US5304505A (en) * 1989-03-22 1994-04-19 Emanuel Hazani Process for EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells
US6109775A (en) * 1991-07-19 2000-08-29 Lsi Logic Corporation Method for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereon
US5252520A (en) * 1991-10-31 1993-10-12 At&T Bell Laboratories Integrated circuit interlevel dielectric wherein the first and second dielectric layers are formed with different densities
US5441915A (en) * 1992-09-01 1995-08-15 Taiwan Semiconductor Manufacturing Company Ltd. Process of fabrication planarized metallurgy structure for a semiconductor device
US5503882A (en) * 1994-04-18 1996-04-02 Advanced Micro Devices, Inc. Method for planarizing an integrated circuit topography
US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US5552996A (en) * 1995-02-16 1996-09-03 International Business Machines Corporation Method and system using the design pattern of IC chips in the processing thereof
US5636133A (en) * 1995-05-19 1997-06-03 International Business Machines Corporation Efficient generation of fill shapes for chips and packages
US5597668A (en) * 1995-07-19 1997-01-28 Vlsi Technology, Inc. Patterned filled photo mask generation for integrated circuit manufacturing
US5641712A (en) * 1995-08-07 1997-06-24 Motorola, Inc. Method and structure for reducing capacitance between interconnect lines
US5518959A (en) * 1995-08-24 1996-05-21 Taiwan Semiconductor Manufacturing Company Method for selectively depositing silicon oxide spacer layers
US5763955A (en) * 1996-07-01 1998-06-09 Vlsi Technology, Inc. Patterned filled layers for integrated circuit manufacturing
US6599847B1 (en) * 1996-08-27 2003-07-29 Taiwan Semiconductor Manufacturing Company Sandwich composite dielectric layer yielding improved integrated circuit device reliability
US5790417A (en) * 1996-09-25 1998-08-04 Taiwan Semiconductor Manufacturing Company Ltd. Method of automatic dummy layout generation
US5923563A (en) * 1996-12-20 1999-07-13 International Business Machines Corporation Variable density fill shape generation
US5854125A (en) * 1997-02-24 1998-12-29 Vlsi Technology, Inc. Dummy fill patterns to improve interconnect planarity
US5968610A (en) * 1997-04-02 1999-10-19 United Microelectronics Corp. Multi-step high density plasma chemical vapor deposition process
US6100205A (en) * 1997-04-02 2000-08-08 United Microelectronics Corp. Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process
US6080672A (en) 1997-08-20 2000-06-27 Micron Technology, Inc. Self-aligned contact formation for semiconductor devices
US6081272A (en) * 1997-09-30 2000-06-27 Intel Corporation Merging dummy structure representations for improved distribution of artifacts in a semiconductor layer
US6251470B1 (en) * 1997-10-09 2001-06-26 Micron Technology, Inc. Methods of forming insulating materials, and methods of forming insulating materials around a conductive component
US6136687A (en) * 1997-11-26 2000-10-24 Integrated Device Technology, Inc. Method of forming air gaps for reducing interconnect capacitance
US6087724A (en) * 1997-12-18 2000-07-11 Advanced Micro Devices, Inc. HSQ with high plasma etching resistance surface for borderless vias
US6093631A (en) * 1998-01-15 2000-07-25 International Business Machines Corporation Dummy patterns for aluminum chemical polishing (CMP)
US5949143A (en) * 1998-01-22 1999-09-07 Advanced Micro Devices, Inc. Semiconductor interconnect structure with air gap for reducing intralayer capacitance in metal layers in damascene metalization process
US6189130B1 (en) * 1998-04-30 2001-02-13 International Business Machines Corporation System and method for determining density maps in hierarchical designs
US6223331B1 (en) 1998-07-30 2001-04-24 Micron Technology, Inc. Semiconductor circuit design method for employing spacing constraints and circuits thereof
US6274479B1 (en) * 1998-08-21 2001-08-14 Micron Technology, Inc Flowable germanium doped silicate glass for use as a spacer oxide
US6262435B1 (en) * 1998-12-01 2001-07-17 Marina V. Plat Etch bias distribution across semiconductor wafer
US6319818B1 (en) * 1999-01-04 2001-11-20 International Business Machines Corporation Pattern factor checkerboard for planarization
US6691297B1 (en) * 1999-03-04 2004-02-10 Matsushita Electric Industrial Co., Ltd. Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI
US6255162B1 (en) * 1999-03-16 2001-07-03 United Microelectronics Corp. Method of gap filling
US6305000B1 (en) * 1999-06-15 2001-10-16 International Business Machines Corporation Placement of conductive stripes in electronic circuits to satisfy metal density requirements
US6396158B1 (en) * 1999-06-29 2002-05-28 Motorola Inc. Semiconductor device and a process for designing a mask
US6174808B1 (en) * 1999-08-04 2001-01-16 Taiwan Semiconductor Manufacturing Company Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS
US6323113B1 (en) * 1999-12-10 2001-11-27 Philips Electronics North America Corporation Intelligent gate-level fill methods for reducing global pattern density effects
US6436807B1 (en) * 2000-01-18 2002-08-20 Agere Systems Guardian Corp. Method for making an interconnect layer and a semiconductor device including the same
US6627549B2 (en) * 2000-03-07 2003-09-30 Micron Technology, Inc. Methods for making nearly planar dielectric films in integrated circuits
US6531412B2 (en) * 2001-08-10 2003-03-11 International Business Machines Corporation Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5776834A (en) * 1995-06-07 1998-07-07 Advanced Micro Devices, Inc. Bias plasma deposition for selective low dielectric insulation
EP0766291A1 (en) * 1995-08-01 1997-04-02 Texas Instruments Incorporated Integrated circuit insulator and method
US5858876A (en) * 1996-04-01 1999-01-12 Chartered Semiconductor Manufacturing, Ltd. Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer
US5814555A (en) * 1996-06-05 1998-09-29 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to lessen capacitive coupling
US5872058A (en) * 1997-06-17 1999-02-16 Novellus Systems, Inc. High aspect ratio gapfill process by using HDP
US6030881A (en) * 1998-05-05 2000-02-29 Novellus Systems, Inc. High throughput chemical vapor deposition process capable of filling high aspect ratio structures

Also Published As

Publication number Publication date
US20040061196A1 (en) 2004-04-01
AU2001249109A1 (en) 2001-09-17
KR20020080474A (en) 2002-10-23
US20060246736A1 (en) 2006-11-02
US20060261435A1 (en) 2006-11-23
US20050023695A1 (en) 2005-02-03
US6627549B2 (en) 2003-09-30
US7235865B2 (en) 2007-06-26
KR100530296B1 (en) 2005-11-22
JP2004501503A (en) 2004-01-15
US20060001022A1 (en) 2006-01-05
JP2007189236A (en) 2007-07-26
US7125800B2 (en) 2006-10-24
US20010053612A1 (en) 2001-12-20
WO2001067500A2 (en) 2001-09-13

Similar Documents

Publication Publication Date Title
WO2001067500A3 (en) Methods for making nearly planar dielectric films in integrated circuits
WO2006037933A3 (en) Method for providing mixed stacked structures, with various insulating zones and/or electrically conducting zones vertically localized
WO2004027834A3 (en) Mim capacitor structures and fabrication methods in dual-damascene structures
TW200629273A (en) Magnetic random access memory and fabricating method thereof
TW200512875A (en) Semiconductor apparatus utilizing multi-level interconnection to prevent peeling-off of low-k layer
WO2002005298A3 (en) Semiconductor inductor and methods for making the same
WO2004001814A3 (en) Method of forming a raised contact for a substrate
SG170113A1 (en) Integrated circuit package with open substrate
WO2002050894A3 (en) Structural reinforcement of highly porous low k dielectric films by cu diffusion barrier structures
AU2002217931A1 (en) Structural reinforcement of highly porous low k dielectric films by ild posts
WO2001084553A3 (en) Three-dimensional memory array and method of fabrication
WO2007068714A3 (en) Method of making a contact in a semiconductor device
TW200717887A (en) Thermoelectric device and method for fabricating the same and chip and electronic device
TW200511384A (en) Self-aligned buried contact pair and method of forming the same
TW200715470A (en) Semiconductor structure and integrated circuit
TW200610463A (en) Circuit board and method of manufacturing the same
WO2009061789A3 (en) Methods of forming magnetic vias to maximize inductance in integrated circuits and structures formed thereby
WO2003017330A3 (en) Forming a semiconductor structure using a combination of planarizing methods and electropolishing
TWI264084B (en) Interconnect structure and method for its fabricating
TW200515501A (en) Method of improving low-k film property and damascene process using the same
WO2007043972A8 (en) Device carrying an integrated circuit/components and method of producing the same
EP1396884A3 (en) Interlayer insulation film used for multilayer interconnect of semiconductor integrated circuit and method of manufacturing the same
TWI265570B (en) Semiconductor device with composite etch stop layer and fabrication method thereof
WO2009033837A3 (en) Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
TW200618175A (en) Method for fabricating low leakage interconnect layers in integrated circuits

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 1020027011717

Country of ref document: KR

ENP Entry into the national phase

Ref country code: JP

Ref document number: 2001 566176

Kind code of ref document: A

Format of ref document f/p: F

WWP Wipo information: published in national office

Ref document number: 1020027011717

Country of ref document: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
WWG Wipo information: grant in national office

Ref document number: 1020027011717

Country of ref document: KR