WO2001075891A2 - Current conveyor and method for readout of mtj memories - Google Patents
Current conveyor and method for readout of mtj memories Download PDFInfo
- Publication number
- WO2001075891A2 WO2001075891A2 PCT/US2001/010334 US0110334W WO0175891A2 WO 2001075891 A2 WO2001075891 A2 WO 2001075891A2 US 0110334 W US0110334 W US 0110334W WO 0175891 A2 WO0175891 A2 WO 0175891A2
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- WIPO (PCT)
- Prior art keywords
- current
- terminal
- transistor
- coupled
- operational amplifier
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/067—Single-ended amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/06—Sense amplifier related aspects
- G11C2207/063—Current sense amplifiers
Definitions
- This invention relates to MTJ memories and more particularly, to apparatus and a method for reading data stored in MTJ memories .
- MRAMs Thin film Magnetic Random Access Memories
- MTJ Magnetic Tunneling Junction
- the MTJ cell essentially consists of a pair of magnetic layers with an insulating layer sandwiched therebetween.
- One of the magnetic layers has a fixed magnetic vector and the other magnetic layer has a changeable magnetic vector that is either aligned with or opposed to the fixed magnetic vector.
- the resistance of the MTJ cell i.e. the resistance to current flow between the magnetic layers, is a minimum and when the magnetic vectors are opposed or misaligned the resistance of the MTJ cell is a maximum.
- Data is stored in the MTJ cell by applying a magnetic field to the MTJ cell directed so as to move the changeable magnetic vector to a selected orientation.
- the aligned orientation can be designated a logic 1 or 0 and the misaligned orientation is the opposite, i.e., a logic 0 or 1.
- Stored data is read or sensed by passing a current through the MTJ cell from one magnetic layer to the other. The amount of current passing through the MTJ cell, or the voltage drop across the MTJ cell, will vary according to the orientation of the changeable magnetic vector. Additional information as to the fabrication and operation of MTJ memory cells can be found in Patent No.
- reading data stored in MTJ cells is achieved by passing a current through a series circuit including a load resistor and the MTJ cell .
- the current passing through the MTJ cell is controlled by a transistor with a bias voltage on the gate, and an output voltage is obtained at a junction between the load resistor and the current controlling transistor.
- a bitline and a data line for the MTJ cell (and other MTJ cells in the array) are clamped at a desired voltage by the transistor.
- the load resistor must be much larger than the resistance of the MTJ cell, which makes operation at low supply voltages very difficult.
- the operation of the circuit is dependent upon the clamping voltage provided by the transistor and the bias voltage.
- the clamping voltage is a function of the resistance of the MTJ cell, the bias voltage, and the load resistance, any or all of which can vary with a specific readout process, variations in the supply voltage, changes in temperature, changes in the resistance of the MTJ cell, etc.
- the large load resistance and the other components in this prior art circuit require large chip areas preventing the fabrication of high density memory arrays.
- the input impedance is high due to the presence of the load resistor.
- FIG. 1 is a schematic diagram of a prior art MTJ readout circuit
- FIG. 2 is a simplified schematic diagram of an MTJ readout circuit in accordance with the present invention
- FIG. 3 is a simplified schematic diagram of another embodiment of an MTJ readout circuit in accordance with the present invention.
- FIG. 4 is a simplified schematic diagram of another embodiment of an MTJ readout circuit in accordance with the present invention
- FIG. 5 is a simplified schematic diagram of a complete readout circuit incorporating the MTJ readout circuit of FIG. 4;
- FIG. 6 is a more detailed schematic diagram of the complete readout circuit of FIG. 5.
- Circuit 10 includes a plurality of magnetic tunneling junction memory cells 11, 12, etc.
- each cell 11, 12, etc. includes an MTJ device, represented as a resistance RMTJ an d a control or activating transistor.
- RMTJ resistance
- RMTJ resistance
- d control or activating transistor.
- One terminal of cell 11 is connected to a current return, such as a circuit common or ground.
- the other terminal of cell 11 is connected to a bit line 13 which is connected to one or more memory cells (not shown) in a well known manner.
- the drain of a column decode transistor 14 is connected to bitline 13 and the gate is connected to a column decoder which selects one column at a time to be readout.
- the source of column decode transistor 14, and all of the other column decode transistors are connected to a data line 15.
- Data line 15 is connected to the drain of a transistor 16, the gate of which is connected to a bias voltage Vbi as .
- the source of transistor 16 is connected through a load resistor 17 to a current supply 18.
- the source of transistor 16 is also connected to a data output terminal 19.
- load resistor 17 is chosen to be much larger than the resistance R TJ to provide voltage gain for the circuit.
- Current source 18 supplies bitline current sunk by the resistance TJ depending upon its R m i n or R ma ⁇ state.
- Transistor 16 clamps data line 15 and the bitlines 13 at a desired voltage depending upon the bias voltage Vki as .
- Transistor 16 provides for low input impedance for current mode operation, since the impedance looking into transistor 16 from data line 15 is small.
- the clamping voltage (provided by transistor 16 and the voltage V D j_ as applied to the gate) will vary with the readout process, the power supply (e.g. current source 18 and voltage Vbi as ) , operating temperature, and the resistance RMTJ °f cell 11.
- the resistance RMTJ Large variations of the resistance RMTJ (i.e. a large ratio between R m in and R max ) can render the circuit virtually useless, since voltage changes may extend beyond the operating region of the circuit .
- Such large variations of the resistance RMTJ will change the current in bitline
- FIG. 2 a simplified schematic diagram is illustrated of an MTJ readout circuit 25 in accordance with the present invention.
- An array 26 of MTJ memory cells 27 arranged in rows and columns is illustrated.
- column decode transistors 29 are considered to be a part of each data readout line 28 with which they are associated, since they are simply switches included to select a specific line. Further, since the column decode transistors 29 are well known in the art and not a part of this invention, in several of the following descriptions they are omitted for simplicity.
- Current conveyor 30 includes a transistor 32 (which may be, for example, a field effect transistor, an HFET, a thin film transistor, or the like) having one current terminal (e.g. the source or drain) connected to data readout line 28 and the other current terminal (e.g. the drain or source) connected to a current source 33.
- the control terminal or gate of transistor 32 is connected to the output terminal of an operational amplifier 35.
- a negative input terminal of operational amplifier 35 is connected to receive negative feedback from data readout line 28 and a positive input terminal is connected to have a bias voltage ⁇ g supplied thereto. It should be noted that the negative input terminal of operational amplifier 35 has a very high (substantially infinite) input impedance so that little or no current flows from data readout line 28.
- operational amplifier 35 compares the voltage V b l on data readout line 28 to Vbi a s and by means of the negative feedback clamps Vbl to V ias (since operational amplifier 35 looks essentially like a short circuit between Vbl to V ias) ⁇ essentially providing current mode operation.
- Current conveyor 30 has a very low input impedance, isolating the data readout line 28 from the high output impedance of current source 33. The low input impedance combined with the clamping of Vbl limits the voltage swing of data readout line 28 and achieves high speed readout for very high density MTJ arrays.
- current conveyor 30 provides and maintains a constant bias across the MTJ memory cell 27 regardless of operating temperatures, changes in the supply voltage, and process conditions. Also, current conveyor 30 provides a small swing in the voltage on data readout line 28 to allow for high speed operation.
- operational amplifier is a generic term for any circuit which will provide the described operation and is not limited to any specific circuit.
- current source 33 provides a current equal to the current required by an MTJ memory cell 27 to yield a voltage drop of V ias across the cell.
- current conveyor 30 performs three functions: it clamps the voltage across RMTJ (the MTJ memory cell) to the desired bias voltage (Vbi a s) ; it makes a small data readout line voltage swing possible for high speed readout and low current consumption; and it is a current-to-voltage converter (i.e. the change in current is proportional to the voltage at the gate terminal of transistor 32) .
- Circuit 40 includes a current conveyor 41 coupled to at least one MTJ memory cell 42 by a data readout line 43, generally as described above.
- data readout line 43 is a bitline and includes a column decode switch or transistor 44.
- a current source 45 is coupled to data readout line 43 through current conveyor 41, as described above.
- a load resistor 47 is coupled to a junction 48 between current source 45 and current conveyor 41. Load resistor 47 is much larger than RMTJ °f MTJ memory cell 42.
- An enable switch 49 illustrated herein as a transistor with the gate connected to receive an "enable" signal, couples load resistor 47 to a current return, such as ground.
- An output signal V 0 is available at a terminal 50 coupled to junction
- Circuit 40 has at least two advantages over MTJ readout circuit 25 of FIG. 2. Since the resistance RL of load resistor 47 is much larger than the resistance R TJ °f MTJ memory cell 42, small changes in the current Ibl through data readout line 43 due to changes in the resistance RMTJ (i.e. Rmin to R m ax or v ce versa) are amplified by load resistor 47. This feature is better understood by noting that the current I from current source 45 splits at junction 48 with part of the current, Ibl flowing through data readout line 43 and the remainder of the current II flowing through load resistor 47.
- V 0 is a linear function of V i a s since Vbias i s a linear function of I, as explained above.
- Circuit 60 includes a current conveyor 61 coupled to at least one MTJ memory cell 62 by a data readout line 63, generally as described above.
- Current conveyor 61 includes a transistor 62 and an operational amplifier 66 connected as described in conjunction with current conveyor 30 of FIG. 2.
- data readout line 63 is a bitline and includes a column decode switch or transistor 64.
- a current source 65 is coupled to data readout line 63 through current conveyor 61, as described above .
- a second current conveyor 67 is coupled to a junction 68 between current source 65 and current conveyor 61.
- Current conveyor 67 is essentially the same as current conveyor 61 and includes a transistor 70 having a first current terminal (in this embodiment the drain terminal) connected to junction 68 and a second current terminal (the source terminal) connected to a current return, such as ground.
- Current conveyor 67 further includes an operational amplifier 71 having a first input terminal connected to junction 68 for negative feedback, a second input terminal connected to receive a second bias voltage V ias2 anc a n output terminal connected to the gate of transistor 70.
- An output signal V 0 is available at a terminal 72 coupled to the gate of transistor 70.
- MTJ readout circuit 60 has all of the advantages of MTJ readout circuits 40 and 25 plus some additional advantages. Specifically, current conveyor 61 clamps data readout line 63 to Vbias1 (the bias on the operational amplifier of current conveyor 61) . In this manner, absolute changes of RMTJ will not change the current Ibl in data readout line 63 and the read operation will be insensitive to RMTJ changes as long as the R TJ variation range is within the linear range of current conveyor 61.
- Transistor 62 of current conveyor 61 is a source follower, that is, the impedance looking into the source terminal of transistor 62 from data readout line 63 is low. This eliminates voltage swings of data readout line 63 to a large extent and makes current mode operation possible.
- second current conveyor 67 provides the following functions/advantages .
- Transistor 62 isolates data readout line 63 (bitline and dataline in this embodiment) from high impedance of current source 65 and output impedance of transistor 70, which provides a highly sensitive and high impedance at junction 68.
- Current conveyor 67 operates as a secondary clamp circuit and is responsible for sensing the same MTJ memory cell 62 current changes (as current sensor 61) and providing an output V 0 at output terminal
- Current conveyor 67 clamps junction 68 to a predetermined voltage such that transistor 62 and current source 65, which in this embodiment is a MOSFET current, are maintained and kept in deep saturation under all process, supply, and temperature conditions, plus all variations of MTJ memory cell 62 within the linearity limits of operational amplifier 71.
- second current conveyor 67 boosts the output voltage based on changes in current caused by changes in RMTJ °f MTJ memory cell 62.
- transistor 70 Since transistor 70 operates in deep saturation, the resistance between the drain terminal and the source terminal (r(j s ) is very much greater than RMTJ- Small changes in the current in data readout line 63 (Ibl) due to RMTJ resistance changes (Rmin to max and vice versa) are amplified by transistor 70.
- V68 Ids ⁇ ds
- Vgg voltage at junction 68
- Vg S gate to source voltage
- circuit 76 is connected to sense the current of a reference MTJ cell 78 (which will generally include a plurality of cells) and circuit 77 is connected to sense the current of a memory MTJ cell 79 (which will generally include a similar plurality of cells) .
- Circuit 76 includes MTJ reference cell 78 coupled by a data line 81 to a current conveyor 82.
- Current conveyor 82 is connected to a junction 83, which is also connected to a current source 84 and a second current conveyor 85.
- a reference output voltage (V 0 R) is available at the gate of transistor 86 of current conveyor 85.
- circuit 77 includes MTJ data memory cell 90 coupled by a data line 91 to a current conveyor 92.
- Current conveyor 92 is connected to a junction 93, which is also connected to a current source 94 and a second current conveyor 95.
- a data output voltage (V 0 D) is available at the gate of transistor 96 of current conveyor
- differential readout circuit 75 provides an offset free output V 0 D - V 0 R. This can be better understood by referring to the following.
- differential readout circuit 75 in this preferred embodiment both transistors 86 and 96 operate in saturation so that the voltage dropped across each transistor 86 and 96 is approximately equal (and is designated Vt hereinafter) and the beta of each transistor 86 and
- transistor 96 is approximately equal (and is designated ⁇ hereinafter) .
- the current flowing in transistor 86 (I 8 6) an ⁇ ⁇ in transistor 96 (I96) is as follows :
- VoD - V oR (2I 96 / ⁇ ) 1/2 + V t - (2I 86 / ⁇ ) 12 - V t
- V oD - V oR (2I 96 / ⁇ ) 12 - (2I 86 / ⁇ ) 1/2
- the output signal V 0 rj - V oR from differential amplifier 100 is independent of the voltage across the drain-source of transistors 86 and 96, which means that the output signal V 0 rj) - V oR is not affected by offset voltages in the operational amplifiers in current conveyors 85 and 95 as long as transistors 86 and 96 are in saturation.
- Circuit 110 includes an array of MTJ memory cells arranged in rows and columns in a well known manner. For convenience of this description only five columns 112 through 116 are illustrated and only a small portion of each these columns is shown. Either of columns 112 or 113 is coupled through a pair of column decode transistors 120 to an MTJ readout circuit 121 (similar in construction and operation to MTJ readout circuit 60 of FIG. 4) . Column 114 is coupled as a reference column through a transistor 122 to an MTJ reference circuit 123 (also similar in construction and operation to MTJ readout circuit 60 of FIG. 4) . Either of columns 115 or 116 is coupled through a pair of column decode transistors 124 to an MTJ readout circuit 125 (similar in construction and operation to MTJ readout circuit 60 of FIG. 4) .
- Columns 112 through 116 are differentially connected by supplying a pair of differential amplifiers 130 and 131.
- the output signal of MTJ readout circuit 121 is supplied to the positive input of differential amplifier 130 and the reference signal from MTJ reference circuit 123 is supplied to the negative input.
- the output signal of MTJ readout circuit 125 is supplied to the positive input of differential amplifier 131 and the reference signal from MTJ reference circuit 123 is supplied to the negative input.
- the value of the bias voltage applied to the first operational amplifier in the MTJ reference circuit 123 is selected so that the voltage of the reference signal from MTJ reference circuit 123 is placed at approximately the midpoint between the voltage of the output signal of MTJ readout circuit 121 and the voltage of the output signal of MTJ readout circuit 125.
- the output voltages will retain this relationship under all process, supply, temperature, and MTJ resistance conditions.
- a new and improved current conveyor which greatly improves the operation and reliability of MTJ readout circuits. Because of the new and improved current conveyor, circuit operation and output signals are independent of all process, supply, temperature, and MTJ resistance conditions. Because of the new and improved current conveyor, voltage swings on data lines or bitlines are virtually eliminated so that the speed of the readout process is greatly increased.
- the new and improved current conveyor operates as a current-voltage converter to improve the operation and the voltage is amplified, to improve readout characteristics.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001573483A JP4776855B2 (en) | 2000-03-31 | 2001-03-29 | Current conveyor and method for reading MTJ memory |
EP01922931A EP1273009B1 (en) | 2000-03-31 | 2001-03-29 | Current conveyor and method for readout of mtj memories |
KR1020027013047A KR100785259B1 (en) | 2000-03-31 | 2001-03-29 | Current conveyor for readout of MTJ memories |
AU2001249680A AU2001249680A1 (en) | 2000-03-31 | 2001-03-29 | Current conveyor and method for readout of mtj memories |
DE60101380T DE60101380T2 (en) | 2000-03-31 | 2001-03-29 | ELECTRIC TRANSMITTER AND METHOD FOR READING MTJ STORAGE |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/540,794 US6205073B1 (en) | 2000-03-31 | 2000-03-31 | Current conveyor and method for readout of MTJ memories |
US09/540,794 | 2000-03-31 |
Publications (2)
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WO2001075891A2 true WO2001075891A2 (en) | 2001-10-11 |
WO2001075891A3 WO2001075891A3 (en) | 2002-01-31 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/US2001/010334 WO2001075891A2 (en) | 2000-03-31 | 2001-03-29 | Current conveyor and method for readout of mtj memories |
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US (1) | US6205073B1 (en) |
EP (1) | EP1273009B1 (en) |
JP (1) | JP4776855B2 (en) |
KR (1) | KR100785259B1 (en) |
AU (1) | AU2001249680A1 (en) |
DE (1) | DE60101380T2 (en) |
TW (1) | TW492056B (en) |
WO (1) | WO2001075891A2 (en) |
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JP3714696B2 (en) * | 1994-10-21 | 2005-11-09 | 富士通株式会社 | Semiconductor memory device |
JP3454661B2 (en) * | 1996-02-26 | 2003-10-06 | 三洋電機株式会社 | Non-volatile semiconductor memory |
US5761110A (en) * | 1996-12-23 | 1998-06-02 | Lsi Logic Corporation | Memory cell capable of storing more than two logic states by using programmable resistances |
-
2000
- 2000-03-31 US US09/540,794 patent/US6205073B1/en not_active Expired - Lifetime
-
2001
- 2001-03-29 DE DE60101380T patent/DE60101380T2/en not_active Expired - Fee Related
- 2001-03-29 KR KR1020027013047A patent/KR100785259B1/en not_active IP Right Cessation
- 2001-03-29 WO PCT/US2001/010334 patent/WO2001075891A2/en active IP Right Grant
- 2001-03-29 JP JP2001573483A patent/JP4776855B2/en not_active Expired - Lifetime
- 2001-03-29 AU AU2001249680A patent/AU2001249680A1/en not_active Abandoned
- 2001-03-29 EP EP01922931A patent/EP1273009B1/en not_active Expired - Lifetime
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US4539491A (en) * | 1981-07-20 | 1985-09-03 | Pioneer Electronic Corporation | Voltage/current conversion circuit |
US5525897A (en) * | 1988-05-24 | 1996-06-11 | Dallas Semiconductor Corporation | Transistor circuit for use in a voltage to current converter circuit |
US5640343A (en) * | 1996-03-18 | 1997-06-17 | International Business Machines Corporation | Magnetic memory array using magnetic tunnel junction devices in the memory cells |
CN1242606A (en) * | 1998-07-16 | 2000-01-26 | 国际商业机器公司 | Magnetic random access memory (MRAM) array with magnetic tunnel junction (MTJ) cells and remote diodes |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008135167A (en) * | 2002-01-18 | 2008-06-12 | Freescale Semiconductor Inc | Mram without isolation device |
CN1295708C (en) * | 2002-01-30 | 2007-01-17 | 三菱电机株式会社 | Film magnet memory with high precision data reading structure |
Also Published As
Publication number | Publication date |
---|---|
JP4776855B2 (en) | 2011-09-21 |
KR100785259B1 (en) | 2007-12-13 |
TW492056B (en) | 2002-06-21 |
US6205073B1 (en) | 2001-03-20 |
JP2003529879A (en) | 2003-10-07 |
KR20030014376A (en) | 2003-02-17 |
EP1273009A2 (en) | 2003-01-08 |
EP1273009B1 (en) | 2003-12-03 |
DE60101380D1 (en) | 2004-01-15 |
WO2001075891A3 (en) | 2002-01-31 |
DE60101380T2 (en) | 2004-05-27 |
AU2001249680A1 (en) | 2001-10-15 |
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