WO2001075898A3 - Interface command architecture for synchronous flash memory - Google Patents

Interface command architecture for synchronous flash memory Download PDF

Info

Publication number
WO2001075898A3
WO2001075898A3 PCT/US2001/010374 US0110374W WO0175898A3 WO 2001075898 A3 WO2001075898 A3 WO 2001075898A3 US 0110374 W US0110374 W US 0110374W WO 0175898 A3 WO0175898 A3 WO 0175898A3
Authority
WO
WIPO (PCT)
Prior art keywords
flash memory
signal
synchronous flash
command register
interface command
Prior art date
Application number
PCT/US2001/010374
Other languages
French (fr)
Other versions
WO2001075898A2 (en
Inventor
Frankie F Roohparvar
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to KR10-2002-7013095A priority Critical patent/KR100508041B1/en
Priority to DE10196001T priority patent/DE10196001B4/en
Priority to JP2001573490A priority patent/JP3725479B2/en
Priority to AU2001249686A priority patent/AU2001249686A1/en
Publication of WO2001075898A2 publication Critical patent/WO2001075898A2/en
Publication of WO2001075898A3 publication Critical patent/WO2001075898A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device comprises an array of non-volatile memory cells, and a command register to store command data used to control flash memory operation. In operation, the command register is loaded by initiating a command register load operation using a predefined combination of a column address strobe (CAS#) signal, a row address strobe (RAS#) signal, and a write enable (WE#) signal.
PCT/US2001/010374 2000-03-30 2001-03-30 Interface command architecture for synchronous flash memory WO2001075898A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR10-2002-7013095A KR100508041B1 (en) 2000-03-30 2001-03-30 Interface command architecture for synchronous flash memory
DE10196001T DE10196001B4 (en) 2000-03-30 2001-03-30 Interface command architecture for synchronous flash memory
JP2001573490A JP3725479B2 (en) 2000-03-30 2001-03-30 Interface command architecture for synchronous flash memory
AU2001249686A AU2001249686A1 (en) 2000-03-30 2001-03-30 Interface command architecture for synchronous flash memory

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US19350600P 2000-03-30 2000-03-30
US60/193,506 2000-03-30
US60704100A 2000-06-30 2000-06-30
US09/607,041 2000-06-30

Publications (2)

Publication Number Publication Date
WO2001075898A2 WO2001075898A2 (en) 2001-10-11
WO2001075898A3 true WO2001075898A3 (en) 2002-05-30

Family

ID=26889064

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/010374 WO2001075898A2 (en) 2000-03-30 2001-03-30 Interface command architecture for synchronous flash memory

Country Status (6)

Country Link
JP (1) JP3725479B2 (en)
KR (1) KR100508041B1 (en)
AU (1) AU2001249686A1 (en)
DE (1) DE10196001B4 (en)
TW (1) TW559806B (en)
WO (1) WO2001075898A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100466980B1 (en) * 2002-01-15 2005-01-24 삼성전자주식회사 Nand flash memory device
JP4005909B2 (en) 2002-12-26 2007-11-14 スパンション インク Semiconductor memory device and method for controlling semiconductor memory device
EP1501100B1 (en) * 2003-07-22 2018-11-28 Samsung Electronics Co., Ltd. Nonvolatile memory device, memory system, and operating methods
US7702839B2 (en) 2005-04-12 2010-04-20 Nokia Corporation Memory interface for volatile and non-volatile memory devices
US7849302B2 (en) 2006-04-10 2010-12-07 Apple Inc. Direct boot arrangement using a NAND flash memory
KR100833189B1 (en) * 2006-11-03 2008-05-28 삼성전자주식회사 Non-volatile memory device and method for setting configuration information thereof
KR100909965B1 (en) 2007-05-23 2009-07-29 삼성전자주식회사 A semiconductor memory system having a volatile memory and a nonvolatile memory sharing a bus and a method of controlling the operation of the nonvolatile memory
JP2008310371A (en) 2007-06-12 2008-12-25 Spansion Llc Synchronous memory controller, synchronous memory, and its control method
JP5323170B2 (en) * 2011-12-05 2013-10-23 ウィンボンド エレクトロニクス コーポレーション Nonvolatile semiconductor memory and data reading method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892777A (en) * 1997-05-05 1999-04-06 Motorola, Inc. Apparatus and method for observing the mode of a memory device
US5903509A (en) * 1995-12-29 1999-05-11 Micron Technology, Inc. Memory device with multiple internal banks and staggered command execution
DE19839570A1 (en) * 1997-11-20 1999-05-27 Samsung Electronics Co Ltd Synchronous semiconductor memory device with programmable latency
US6026465A (en) * 1994-06-03 2000-02-15 Intel Corporation Flash memory including a mode register for indicating synchronous or asynchronous mode of operation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026465A (en) * 1994-06-03 2000-02-15 Intel Corporation Flash memory including a mode register for indicating synchronous or asynchronous mode of operation
US5903509A (en) * 1995-12-29 1999-05-11 Micron Technology, Inc. Memory device with multiple internal banks and staggered command execution
US5892777A (en) * 1997-05-05 1999-04-06 Motorola, Inc. Apparatus and method for observing the mode of a memory device
DE19839570A1 (en) * 1997-11-20 1999-05-27 Samsung Electronics Co Ltd Synchronous semiconductor memory device with programmable latency

Also Published As

Publication number Publication date
WO2001075898A2 (en) 2001-10-11
DE10196001B4 (en) 2008-07-03
KR20030014379A (en) 2003-02-17
TW559806B (en) 2003-11-01
JP2003529885A (en) 2003-10-07
KR100508041B1 (en) 2005-08-17
AU2001249686A1 (en) 2001-10-15
JP3725479B2 (en) 2005-12-14
DE10196001T1 (en) 2003-02-27

Similar Documents

Publication Publication Date Title
KR102370156B1 (en) Memory system, and memory module and semiconductor memory device for the same
KR100273725B1 (en) Auto-activate on synchronous dynamic random access memory
KR100746229B1 (en) Semiconductor memory device
US6201760B1 (en) Apparatus and method for performing data read operation in DDR SDRAM
KR100948090B1 (en) Memory interface for volatile and non-volatile memory devices
US20050027928A1 (en) SDRAM memory device with an embedded NAND flash controller
US20060140043A1 (en) Flash memory architecture for optimizing performance of memory having multi-level memory cells
US6570791B2 (en) Flash memory with DDRAM interface
JPH11250657A (en) Synchronous semiconductor memory
JP2014211939A (en) Register read for volatile memory
WO2001075895A3 (en) Elimination of precharge operation in synchronous flash memory
WO2006121874A3 (en) Memory device and method having a data bypass path to allow rapid testing and calibration
US6453381B1 (en) DDR DRAM data coherence scheme
WO2001075898A3 (en) Interface command architecture for synchronous flash memory
US8654603B2 (en) Test operation for a low-power double-data-rate (LPDDR) nonvolatile memory device
US7414899B2 (en) Method and apparatus for early write termination in a semiconductor memory
KR100438779B1 (en) Synchronous semiconductor memory device comprising multi-bank scheme
US10535395B2 (en) Memory device with improved latency and operating method thereof
KR100265589B1 (en) Syschronous memory device
WO2007080097A1 (en) Memory having status register read function
KR100444703B1 (en) Memory device having high bus efficiency of network and the operation method thereof and memory system including the same
US20190355410A1 (en) Half-Width, Double Pumped Data Path
US6859901B2 (en) Method for testing memories with seamless data input/output by interleaving seamless bank commands
US6396755B2 (en) Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory
US6751130B2 (en) Integrated memory device, method of operating an integrated memory, and memory system having a plurality of integrated memories

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

ENP Entry into the national phase

Ref country code: JP

Ref document number: 2001 573490

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 1020027013095

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020027013095

Country of ref document: KR

122 Ep: pct application non-entry in european phase
WWG Wipo information: grant in national office

Ref document number: 1020027013095

Country of ref document: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8607