WO2001091176A3 - Trilayer/bilayer solder bumps and fabrication methods therefor - Google Patents

Trilayer/bilayer solder bumps and fabrication methods therefor Download PDF

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Publication number
WO2001091176A3
WO2001091176A3 PCT/US2001/014674 US0114674W WO0191176A3 WO 2001091176 A3 WO2001091176 A3 WO 2001091176A3 US 0114674 W US0114674 W US 0114674W WO 0191176 A3 WO0191176 A3 WO 0191176A3
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WO
WIPO (PCT)
Prior art keywords
solder
solder layer
layer
tin
lead
Prior art date
Application number
PCT/US2001/014674
Other languages
French (fr)
Other versions
WO2001091176A2 (en
Inventor
Glenn A Rinne
Original Assignee
Unitive Electronics Inc
Glenn A Rinne
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unitive Electronics Inc, Glenn A Rinne filed Critical Unitive Electronics Inc
Priority to AU2001261234A priority Critical patent/AU2001261234A1/en
Publication of WO2001091176A2 publication Critical patent/WO2001091176A2/en
Publication of WO2001091176A3 publication Critical patent/WO2001091176A3/en

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

Solder bumps are fabricated by plating a first solder layer (150) on an underbump metallurgy (130), plating a second solder layer (160) having higher melting point than the first solder layer on the first solder layer and plating a third solder layer (170) having lower melting point than the second solder layer on the second solder layer. The structure then is heated to below the melting point of the second solder layer but above the melting point of the first solder layer and the third solder layer, to alloy at least some of the first solder layer with at least some of the underbump metallurgy and to round the third solder layer. Accordingly, a trilayer solder bump may be fabricated wherein the first and third layers melt at lower temperatures than the second solder layer, to thereby round the outer surface of the solder bump and alloy the base of the solder bump to the underbump metallurgy, while allowing the structure of the intermediate layer to be preserved. Solder bump fabrication as described above may be particularly useful with lead-tin solder wherein the first solder layer is eutectic lead-tin solder, the second solder layer is lead-tin solder having higher lead content than eutectic lead-tin solder and the third solder layer is eutectic lead-tin solder. In yet other embodiments, the thickness and/or composition of the outer underbump metallurgy layer and/or of the first solder layer may be selected so that upon heating, sufficient tin from the first solder layer is alloyed with at least some of the outer underbump metallurgy layer, such that the first solder layer is converted to a fourth solder layer having the same lead content as the second solder layer. Bilayer solder bumps thereby may be provided.
PCT/US2001/014674 2000-05-23 2001-05-07 Trilayer/bilayer solder bumps and fabrication methods therefor WO2001091176A2 (en)

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US09/576,477 US6492197B1 (en) 2000-05-23 2000-05-23 Trilayer/bilayer solder bumps and fabrication methods therefor
US09/576,477 2000-05-23

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WO2001091176A3 true WO2001091176A3 (en) 2002-04-18

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AU (1) AU2001261234A1 (en)
MY (1) MY122810A (en)
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WO (1) WO2001091176A2 (en)

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US6492197B1 (en) 2002-12-10
TW507300B (en) 2002-10-21
MY122810A (en) 2006-05-31
WO2001091176A2 (en) 2001-11-29

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