WO2001093334A1 - Procede de fabrication d'une plaquette collee et cette derniere - Google Patents
Procede de fabrication d'une plaquette collee et cette derniere Download PDFInfo
- Publication number
- WO2001093334A1 WO2001093334A1 PCT/JP2001/004499 JP0104499W WO0193334A1 WO 2001093334 A1 WO2001093334 A1 WO 2001093334A1 JP 0104499 W JP0104499 W JP 0104499W WO 0193334 A1 WO0193334 A1 WO 0193334A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wafer
- ion implantation
- bonded
- ion
- implanted
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/974—Substrate surface preparation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Definitions
- the present invention relates to a method of manufacturing a bonded wafer, in which a wafer into which hydrogen or a rare gas ion has been implanted is bonded to another wafer and then peeled off with an implanted layer, and more particularly to a bonding method free from defects called a microphone opening void.
- the manufacturing method of the lamination is a method of manufacturing a bonded wafer, in which a wafer into which hydrogen or a rare gas ion has been implanted is bonded to another wafer and then peeled off with an implanted layer, and more particularly to a bonding method free from defects called a microphone opening void.
- a technique for bonding SOI (silicononinsulator) wafers using a bonding method, in which two silicon wafers are bonded via a silicon oxide film, is disclosed, for example, in Japanese Patent Publication No. 5-46686.
- an oxide film is formed on at least one of the wafers, adhered to each other without intervening foreign matter on the bonding surface, and then heat-treated at a temperature of 200 to 1200 ° C.
- a method for increasing the bonding strength has been conventionally known.
- the bonded wafer whose bonding strength has been increased by performing the heat treatment in this manner can be subjected to a subsequent grinding and polishing process, the wafer to be manufactured on the element manufacturing side is reduced in thickness to a desired thickness by grinding and polishing. Thereby, an SOI layer for forming an element can be formed.
- the bonded SOI wafer fabricated in this way has the advantage of excellent crystallinity of the SOI layer and high reliability of the buried oxide film directly under the SOI layer.However, it is thinned by grinding and polishing. Therefore, it takes a long time to reduce the film thickness, wastes materials, and achieves a film thickness uniformity of at most about the target film thickness of ⁇ 0.3.
- the thickness of the SOI layer is required to be further reduced in thickness and the uniformity of the film thickness is improved.
- a film thickness and film thickness uniformity of about 0 1 ⁇ m are required. Since thin film SOI with such film thickness and film thickness uniformity and wafer bonding are not possible by conventional grinding and polishing, it is impossible to achieve this with a wafer.
- a method called an ion implantation separation method or a hydrogen ion separation method disclosed in Japanese Patent Application Laid-Open No. 5-221118 has been developed.
- the method of manufacturing a bonded SOI wafer by the ion implantation delamination method is to form an oxide film on at least one of the two silicon wafers and to form hydrogen ions or rare ions from the upper surface of one of the silicon wafers (also referred to as bonde wafer).
- the ion-implanted surface is brought into close contact with the other wafer (also referred to as a base wafer) via an oxide film, followed by heat treatment (peeling).
- Heat treatment is applied to make the microbubble layer a cleavage surface (separation surface), one of the wafers is separated into a thin film, and then heat treatment (bonding heat treatment) is applied to form a firm bond to form an SOI wafer.
- the peeled surface is a good mirror surface, SOI wafers with extremely high uniformity of the SOI layer thickness can be obtained relatively easily, and one of the peeled wafers can be reused. It also has the advantage that it can be used.
- this method can be used to bond silicon wafers directly without passing through an oxide film. Not only when silicon wafers are bonded together, but also by ion implantation into silicon wafers, quartz, sapphire, It is also possible to combine silicon nitride, aluminum nitride, and other insulating wafers with different coefficients of thermal expansion, or by ion-implanting insulating wafers and combining them with other wafers to produce wafers with these thin films. Used.
- This ion implantation delamination method is an extremely excellent method for manufacturing bonded SOI wafers, but in order to produce these SOI wafers at a high yield at the mass production level, bonding called voids generated at the bonded interface is required. Defects need to be reduced.
- the main cause is particles attached to the bonding surface.
- the particle size of the particles is 0.5 ⁇ m or more. It is stated that if any, a void will occur. In other words, when such particles are present on the bonding surface when two wafers are bonded, an unbonded portion (void) is formed at the bonding interface. Since the size of the formed void is approximately 0.5 mm to several 10 mm in diameter, it is almost circular, so the wafer is left bonded at room temperature or heat treatment is applied to strengthen the bonding. After that, it can be observed with X-ray topograph, ultrasonic flaw detector, infrared interferometry, etc. Therefore, in order to reduce such voids, it is necessary to perform wafer cleaning to remove particles adhering to the surface to be bonded and remove particles as much as possible before bonding. Good.
- this diameter a connection failure part (hereinafter, referred to as “this diameter”) of much smaller size (about several Xm to several 10 ⁇ m or less) are called microvoids). Disclosure of the invention
- an object of the present invention is to provide a method for manufacturing a bonded wafer for reducing such a ⁇ void generated by the ion implantation separation method, and a bonded wafer free of a microphone opening void.
- a method for manufacturing a bonded wafer according to the present invention comprises: An ion implantation step of forming an (implanted layer); an adhesion step of adhering the surface of the first wafer to which the ion implantation has been performed and the surface of the second wafer; A method of manufacturing a bonded wafer having a peeling step of peeling off the ion, wherein the ion implantation step is performed by dividing it into a plurality of times.
- the ion implantation process is divided into multiple steps, bubbles gradually diffuse into the shadows of the ion implantation that can be created immediately below the particles attached to the ion implantation surface, which causes microvoids.
- a region having an extremely low ion concentration is reduced, and the occurrence of microvoids can be prevented without peeling failure due to peeling heat treatment.
- ion implantation is performed by changing the implantation angle of the implanted ions in a plurality of ion implantation processes, even if particles are attached to the wafer surface, the unimplanted region of the ions below the particles (shadow). Part) can be reduced and can be uniformly peeled.
- a silicon single crystal wafer can be used as the first wafer.
- an SOI wafer having an SOI layer with a very uniform film thickness can be manufactured at low cost, so that it can be widely applied to various devices.
- a silicon single crystal wafer can be used as the second wafer. If a silicon single crystal wafer is used as the second wafer, that is, a silicon wafer as the base wafer, a wafer with excellent flatness can be obtained, and a large diameter wafer having a diameter of 200 mm, 300 mm or more can be obtained. be able to.
- an oxide film may be formed in advance on the surface of the second wafer before the contact.
- the generation of voids due to the bonding with the first wafer can be reduced.
- the method of the present invention it is possible to obtain an extremely high-quality bonded wafer with reduced generation of microvoids.
- the bonded wafer according to the present invention includes a first wafer having a microbubble layer (implanted layer) into which at least one of hydrogen ions and rare gas ions has been implanted, and a first wafer having an ion-implanted surface of the first wafer.
- microvoids generated due to particles adhering to the ion implantation surface can be reduced or eliminated, and high quality bonding can be easily performed. Can be manufactured.
- FIG. 1 is a process chart showing the steps of the ion implantation delamination method of the present invention.
- FIG. 2 is a process chart showing another process of the ion implantation delamination method of the present invention.
- FIG. 3 is an explanatory diagram illustrating a mechanism of generating a microphone mouth void in a conventional ion implantation separation method.
- the generation position is determined by the particle position measured immediately before bonding, that is, after the ion implantation and cleaning process. There were many matches. However, some of them were generated irrespective of the position of the particles immediately before bonding.
- FIG. 3 is a diagram schematically illustrating the generation mechanism of the microvoids.
- FIG. 3A shows the first wafer just before hydrogen ion implantation.
- 1st AEHA (Bonduea) 1 was cleaned, but particles 7 adhered to the 1st AEHA surface while being set in the ion implanter or during ion implantation. May be. If ion implantation is performed with the particles 7 attached, a region where the hydrogen ions 5 are not implanted is generated in a shadowed portion of the particles, as shown in FIG. 3 (b).
- ion implantation is performed in a plurality of times, and the total implantation dose in each implantation step is set to be the implantation dose necessary for exfoliation. For example, at least one wafer is used between each implantation step. If cleaning is performed, even if particles have adhered in the first injection step, the probability of particles adhering to the same part again is extremely low if the particles are removed by cleaning. The ions are also implanted into the regions not implanted in the implantation step.
- cleaning using a chemical solution such as ammonia, hydrogen peroxide, or a water-based chemical cleaning (SC-1) which is usually used for removing particles
- SC-1 water-based chemical cleaning
- the present invention is not limited to this, and cleaning that does not use a chemical solution such as cleaning with pure water rinse and electrolytic ion water to which ultrasonic waves are applied may be used as long as particles can be removed.
- Figure 1 shows the process of manufacturing the bonded wafer when the ion implantation is performed twice and the cleaning is performed once in the intervening process.
- Figure 1 (a) shows the first wafer before the first hydrogen ion implantation.
- the first wafer 1 was cleaned before the hydrogen ion implantation.
- Particles 7 may adhere to the first wafer surface during setting or during ion implantation. If the ion implantation is performed with the particles 7 attached, a region where the hydrogen ions are not implanted is generated in the shadowed portion of the particles 7 as shown in FIG. 1 (b).
- the area where the particles adhered was smaller than the area where the total implantation dose was completely implanted, and it is possible that the implantation dose required for separation was not reached. Therefore, if a certain number of defect layers (microbubble layer, injection layer) are formed, peeling can be caused due to excessive bubbles diffusing from the periphery of the region.
- Figure 2 shows the process when the ion implantation angle was changed.
- the first ion implantation is performed from the upper left of the particle (Fig. 2 (b)), and the second ion implantation is performed from the upper right of the particle (Fig. 2 (b)). c))).
- the wafer to be bonded can be arbitrarily selected according to the purpose, and is not particularly limited. For example, if a silicon single crystal wafer is used as the first wafer, the film thickness can be reduced. Since an SOI wafer having an extremely uniform SOI layer can be manufactured at low cost, it can be widely applied to various devices. Silicon wafers are also suitable for large diameters.
- an oxide film is formed on the surface of the first wafer before implantation. This is because if a thermal oxide film or a CVD oxide film is formed on the surface before ion implantation, deterioration of the implantation profile (spreading in the depth direction) due to the channeling phenomenon during ion implantation can be reduced. This is because the generation of voids (unconnected portions) at the time of connection with the second wafer can be reduced.
- a silicon single crystal wafer can be used as the second wafer, or a wafer other than silicon can be used according to the purpose. If a silicon single crystal wafer is used as the second wafer, that is, a silicon wafer as a base wafer, a wafer with excellent flatness can be obtained, and thus the flat wafer after bonding can be obtained. The degree of improvement is also improved, which is preferable in the subsequent device processes. Moreover, it is relatively easy to obtain a large diameter wafer having a diameter of 200 mm, 300 mm or more.
- an oxide film may be formed in advance on the surface of the second wafer before the contact.
- a thermal oxide film, a CVD oxide film, or the like on the surface of the second wafer, the occurrence of voids due to the bonding with the first wafer can be reduced.
- Adhesion Adhere to silicon single crystal 2nd wafer (no oxide film) at room temperature.
- Peeling Peeling by heat treatment at 500 ° C for 30 minutes in a nitrogen atmosphere.
- the micro-bodies use a light scattering type particle measuring instrument that uses a laser or other light source to measure the surface of the bonded wafer and obtain the coordinates of the particles within the bonded wafer to obtain strong intensity of the scattered light. By observing what is detected as large bright spots (particles) with an optical microscope, it is It can be confirmed as a microvoid. Since a certain degree of correlation can be obtained from the size of the bright spot detected by the particle measuring instrument and the result of optical microscopy observation, simple evaluation is possible using only the particle measuring instrument. Then, using a particle measuring instrument and an optical microscope as the measuring device, and observing the entire surface of the wafer, no microvoids were observed in any of the wafers.
- the density of microvoids with a diameter of about 1 ⁇ was extremely low, with an average of about 3 pieces and a diameter of 200 mm diameter.
- a silicon single crystal wafer of 0 nm was prepared.
- the density of the microphone mouth void with a diameter of about 1 ⁇ m was very defective, with an average of about 28 pieces / diameter of 200 mm diameter e-ha.
- the present invention is not limited to the above embodiment.
- the above embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the claims of the present invention. It is included in the technical scope of the invention.
- a wafer manufactured by an ion implantation delamination method can be an SOI wafer having an SOI layer as well as the silicon single crystal wafer bonded together, It is also possible to provide silicon single crystal wafers and insulating wafers, and wafers in which insulating wafers are bonded together.
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01932319A EP1302985A1 (en) | 2000-05-30 | 2001-05-29 | Method for producing bonded wafer and bonded wafer |
KR1020027016061A KR100741541B1 (ko) | 2000-05-30 | 2001-05-29 | 접합웨이퍼의 제조방법 및 접합웨이퍼 |
US10/296,900 US6900113B2 (en) | 2000-05-30 | 2001-05-29 | Method for producing bonded wafer and bonded wafer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-160499 | 2000-05-30 | ||
JP2000160499 | 2000-05-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001093334A1 true WO2001093334A1 (fr) | 2001-12-06 |
Family
ID=18664684
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2001/004499 WO2001093334A1 (fr) | 2000-05-30 | 2001-05-29 | Procede de fabrication d'une plaquette collee et cette derniere |
Country Status (4)
Country | Link |
---|---|
US (1) | US6900113B2 (ja) |
EP (1) | EP1302985A1 (ja) |
KR (1) | KR100741541B1 (ja) |
WO (1) | WO2001093334A1 (ja) |
Cited By (10)
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JP2002313689A (ja) * | 2001-04-18 | 2002-10-25 | Shin Etsu Handotai Co Ltd | 貼り合せ基板の製造方法 |
JP2005086041A (ja) * | 2003-09-09 | 2005-03-31 | Sumitomo Mitsubishi Silicon Corp | 半導体ウェーハのイオン注入方法 |
JP2007533123A (ja) * | 2004-03-30 | 2007-11-15 | エス オー イ テク シリコン オン インシュレータ テクノロジース | 別のウェハと接合するための半導体ウェハ表面の調製 |
US7534728B2 (en) | 2005-04-19 | 2009-05-19 | Sumco Corporation | Process for cleaning silicon substrate |
JP2011228650A (ja) * | 2010-03-31 | 2011-11-10 | Semiconductor Energy Lab Co Ltd | 半導体基板の作製方法及び半導体装置の作製方法 |
JP2012019125A (ja) * | 2010-07-09 | 2012-01-26 | Semiconductor Energy Lab Co Ltd | 半導体基板の作製方法、及び半導体装置の作製方法 |
WO2012164822A1 (ja) * | 2011-05-30 | 2012-12-06 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法及び貼り合わせsoiウェーハ |
JP2014011272A (ja) * | 2012-06-28 | 2014-01-20 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
JP2017508280A (ja) * | 2014-02-07 | 2017-03-23 | サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited | 層状半導体構造体の製造方法 |
JP2017509166A (ja) * | 2014-03-12 | 2017-03-30 | オーイーウェーブス, インク.Oewaves, Inc. | モードファミリーを除去するためのシステム及び方法 |
Families Citing this family (15)
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US6846718B1 (en) | 1999-10-14 | 2005-01-25 | Shin-Etsu Handotai Co., Ltd. | Method for producing SOI wafer and SOI wafer |
US7052978B2 (en) * | 2003-08-28 | 2006-05-30 | Intel Corporation | Arrangements incorporating laser-induced cleaving |
JP4730581B2 (ja) * | 2004-06-17 | 2011-07-20 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
FR2884647B1 (fr) * | 2005-04-15 | 2008-02-22 | Soitec Silicon On Insulator | Traitement de plaques de semi-conducteurs |
TWI270928B (en) * | 2005-07-22 | 2007-01-11 | Sino American Silicon Products | Method of manufacturing composite wafer sructure |
US20070023850A1 (en) * | 2005-07-30 | 2007-02-01 | Chien-Hua Chen | Bonding surfaces together via plasma treatment on both surfaces with wet treatment on only one surface |
US7781309B2 (en) * | 2005-12-22 | 2010-08-24 | Sumco Corporation | Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method |
DE102006062947B3 (de) | 2006-08-30 | 2023-05-17 | Infineon Technologies Austria Ag | Verfahren zur Herstellung einer Halbleitervorrichtung mit einer Feldstoppzone in einer vorbestimmten Eindringtiefe |
EP1993128A3 (en) * | 2007-05-17 | 2010-03-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate |
EP2040285A1 (en) * | 2007-09-19 | 2009-03-25 | S.O.I. TEC Silicon | Method for fabricating a mixed orientation substrate |
US8101501B2 (en) * | 2007-10-10 | 2012-01-24 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor device |
US7696058B2 (en) * | 2007-10-31 | 2010-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
US7811901B1 (en) * | 2007-12-03 | 2010-10-12 | Silicon Genesis Corporation | Method and edge region structure using co-implanted particles for layer transfer processes |
FR2988516B1 (fr) * | 2012-03-23 | 2014-03-07 | Soitec Silicon On Insulator | Procede d'implantation de fragilisation de substrats ameliore |
KR102529986B1 (ko) | 2022-12-26 | 2023-05-08 | 한국해양과학기술원 | 해양 치유용 머드 및 이의 제조방법 |
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2001
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- 2001-05-29 WO PCT/JP2001/004499 patent/WO2001093334A1/ja not_active Application Discontinuation
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- 2001-05-29 EP EP01932319A patent/EP1302985A1/en not_active Withdrawn
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Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2002313689A (ja) * | 2001-04-18 | 2002-10-25 | Shin Etsu Handotai Co Ltd | 貼り合せ基板の製造方法 |
JP4628580B2 (ja) * | 2001-04-18 | 2011-02-09 | 信越半導体株式会社 | 貼り合せ基板の製造方法 |
JP2005086041A (ja) * | 2003-09-09 | 2005-03-31 | Sumitomo Mitsubishi Silicon Corp | 半導体ウェーハのイオン注入方法 |
JP2007533123A (ja) * | 2004-03-30 | 2007-11-15 | エス オー イ テク シリコン オン インシュレータ テクノロジース | 別のウェハと接合するための半導体ウェハ表面の調製 |
US7534728B2 (en) | 2005-04-19 | 2009-05-19 | Sumco Corporation | Process for cleaning silicon substrate |
JP2011228650A (ja) * | 2010-03-31 | 2011-11-10 | Semiconductor Energy Lab Co Ltd | 半導体基板の作製方法及び半導体装置の作製方法 |
JP2012019125A (ja) * | 2010-07-09 | 2012-01-26 | Semiconductor Energy Lab Co Ltd | 半導体基板の作製方法、及び半導体装置の作製方法 |
WO2012164822A1 (ja) * | 2011-05-30 | 2012-12-06 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法及び貼り合わせsoiウェーハ |
JP2012248739A (ja) * | 2011-05-30 | 2012-12-13 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法及び貼り合わせsoiウェーハ |
US8987109B2 (en) | 2011-05-30 | 2015-03-24 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing bonded wafer and bonded SOI wafer |
JP2014011272A (ja) * | 2012-06-28 | 2014-01-20 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
JP2017508280A (ja) * | 2014-02-07 | 2017-03-23 | サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited | 層状半導体構造体の製造方法 |
JP2017509166A (ja) * | 2014-03-12 | 2017-03-30 | オーイーウェーブス, インク.Oewaves, Inc. | モードファミリーを除去するためのシステム及び方法 |
Also Published As
Publication number | Publication date |
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EP1302985A1 (en) | 2003-04-16 |
KR100741541B1 (ko) | 2007-07-20 |
KR20030004440A (ko) | 2003-01-14 |
US6900113B2 (en) | 2005-05-31 |
US20030153162A1 (en) | 2003-08-14 |
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