WO2001097286A3 - High density three dimensional chip package assembly systems and methods - Google Patents

High density three dimensional chip package assembly systems and methods Download PDF

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Publication number
WO2001097286A3
WO2001097286A3 PCT/US2001/016470 US0116470W WO0197286A3 WO 2001097286 A3 WO2001097286 A3 WO 2001097286A3 US 0116470 W US0116470 W US 0116470W WO 0197286 A3 WO0197286 A3 WO 0197286A3
Authority
WO
WIPO (PCT)
Prior art keywords
microelectronic
chip
jig
methods
present
Prior art date
Application number
PCT/US2001/016470
Other languages
French (fr)
Other versions
WO2001097286A2 (en
Inventor
Vince Rogers
Mark W Roberson
Glenn A Rinne
Philip A Deane
Richard Baldwin
Original Assignee
Mcnc
Vince Rogers
Mark W Roberson
Glenn A Rinne
Philip A Deane
Richard Baldwin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mcnc, Vince Rogers, Mark W Roberson, Glenn A Rinne, Philip A Deane, Richard Baldwin filed Critical Mcnc
Priority to AU2001274890A priority Critical patent/AU2001274890A1/en
Publication of WO2001097286A2 publication Critical patent/WO2001097286A2/en
Publication of WO2001097286A3 publication Critical patent/WO2001097286A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

The present invention comprises a number of systems and methods for precisely aligning and spacing microelectronic chips during the fabrication and assembly of three-dimensional microelectronic packages. The present invention precisely aligns and spaces microelectronic chips via an alignment jig comprising two or more opposing walls or surfaces, at least two of which are substantially parallel, and fixed in relation to one another. Support features on the at least two substantially opposing walls of the jig maintain the alignment and spacing of the microelectronic chips placed in the jig. In another embodiment of the present invention, an end effector for a chip pick and place tool includes a vacuum block, including a thermocouple and heating element. Thus, the pressure of the vacuum block may engage and hold a microelectronic chip as the chip is lifted and placed where desired on a substrate. The heating element may be utilized to heat the associated solder bumps to bond the microelectronic chip to the substrate.
PCT/US2001/016470 2000-06-13 2001-05-22 High density three dimensional chip package assembly systems and methods WO2001097286A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001274890A AU2001274890A1 (en) 2000-06-13 2001-05-22 High density three dimensional chip package assembly systems and methods

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59272600A 2000-06-13 2000-06-13
US09/592,726 2000-06-13

Publications (2)

Publication Number Publication Date
WO2001097286A2 WO2001097286A2 (en) 2001-12-20
WO2001097286A3 true WO2001097286A3 (en) 2003-10-02

Family

ID=24371829

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/016470 WO2001097286A2 (en) 2000-06-13 2001-05-22 High density three dimensional chip package assembly systems and methods

Country Status (2)

Country Link
AU (1) AU2001274890A1 (en)
WO (1) WO2001097286A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015108909B4 (en) * 2015-06-05 2021-02-18 Infineon Technologies Ag Arrangement of several power semiconductor chips and method for producing the same
CN112518166B (en) * 2021-02-10 2021-08-03 北京中科同志科技股份有限公司 Packaging method for chip reliability vacuum packaging welding equipment

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0531724A1 (en) * 1991-09-13 1993-03-17 International Business Machines Corporation Stepped electronic device package
US5279991A (en) * 1992-05-15 1994-01-18 Irvine Sensors Corporation Method for fabricating stacks of IC chips by segmenting a larger stack
US5682064A (en) * 1993-08-16 1997-10-28 Micron Technology, Inc. Repairable wafer scale integration system
US5786632A (en) * 1993-10-14 1998-07-28 Micron Technology, Inc. Semiconductor package
US5786985A (en) * 1991-05-31 1998-07-28 Fujitsu Limited Semiconductor device and semiconductor device unit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786985A (en) * 1991-05-31 1998-07-28 Fujitsu Limited Semiconductor device and semiconductor device unit
EP0531724A1 (en) * 1991-09-13 1993-03-17 International Business Machines Corporation Stepped electronic device package
US5279991A (en) * 1992-05-15 1994-01-18 Irvine Sensors Corporation Method for fabricating stacks of IC chips by segmenting a larger stack
US5682064A (en) * 1993-08-16 1997-10-28 Micron Technology, Inc. Repairable wafer scale integration system
US5786632A (en) * 1993-10-14 1998-07-28 Micron Technology, Inc. Semiconductor package

Also Published As

Publication number Publication date
WO2001097286A2 (en) 2001-12-20
AU2001274890A1 (en) 2001-12-24

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