WO2001097469A3 - Packet transmission scheduler - Google Patents

Packet transmission scheduler Download PDF

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Publication number
WO2001097469A3
WO2001097469A3 PCT/NO2001/000247 NO0100247W WO0197469A3 WO 2001097469 A3 WO2001097469 A3 WO 2001097469A3 NO 0100247 W NO0100247 W NO 0100247W WO 0197469 A3 WO0197469 A3 WO 0197469A3
Authority
WO
WIPO (PCT)
Prior art keywords
packet transmission
transmission scheduler
scheduler
relates
present
Prior art date
Application number
PCT/NO2001/000247
Other languages
French (fr)
Other versions
WO2001097469A2 (en
Inventor
Hans Rygh
Original Assignee
Sun Microsystems Inc
Hans Rygh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc, Hans Rygh filed Critical Sun Microsystems Inc
Priority to AU2001282688A priority Critical patent/AU2001282688A1/en
Publication of WO2001097469A2 publication Critical patent/WO2001097469A2/en
Publication of WO2001097469A3 publication Critical patent/WO2001097469A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes

Abstract

The present invention relates to a method and an apparatus for transferring information through a communication medium. More particularly, the present invention relates to a multithreading, non-blocking packet transmission scheduler and a method of operation. The packet transmission scheduler described is based on a set of atomic operations and a number of linked lists. The scheduler uses the lists to keep track of previous and current state, like what packets have been sent and what have been rejected, so that fairness combined with optimal exploitation of the connection can be delivered.
PCT/NO2001/000247 2000-06-14 2001-06-12 Packet transmission scheduler WO2001097469A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001282688A AU2001282688A1 (en) 2000-06-14 2001-06-12 Packet transmission scheduler

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59345000A 2000-06-14 2000-06-14
US09/593,450 2000-06-14

Publications (2)

Publication Number Publication Date
WO2001097469A2 WO2001097469A2 (en) 2001-12-20
WO2001097469A3 true WO2001097469A3 (en) 2002-05-02

Family

ID=24374759

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/NO2001/000247 WO2001097469A2 (en) 2000-06-14 2001-06-12 Packet transmission scheduler

Country Status (2)

Country Link
AU (1) AU2001282688A1 (en)
WO (1) WO2001097469A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG155038A1 (en) * 2001-09-28 2009-09-30 Consentry Networks Inc A multi-threaded packet processing engine for stateful packet processing

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923656A (en) * 1996-10-22 1999-07-13 Board Of Trustees Of The University Of Illinois Scalable broad band input-queued ATM switch including weight driven cell scheduler
US5996019A (en) * 1995-07-19 1999-11-30 Fujitsu Network Communications, Inc. Network link access scheduling using a plurality of prioritized lists containing queue identifiers
WO2000007126A1 (en) * 1998-07-30 2000-02-10 Teledyne Technologies Incorporated Aircraft flight data acquisition and transmission system
WO2000028701A1 (en) * 1998-11-09 2000-05-18 Cabletron Systems, Inc. Method and apparatus for fair and efficient scheduling of variable size data packets in input buffered switch
EP1009189A2 (en) * 1998-12-08 2000-06-14 Nec Corporation RRGS-round-robin greedy scheduling for input/output buffered terabit switches

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5996019A (en) * 1995-07-19 1999-11-30 Fujitsu Network Communications, Inc. Network link access scheduling using a plurality of prioritized lists containing queue identifiers
US5923656A (en) * 1996-10-22 1999-07-13 Board Of Trustees Of The University Of Illinois Scalable broad band input-queued ATM switch including weight driven cell scheduler
WO2000007126A1 (en) * 1998-07-30 2000-02-10 Teledyne Technologies Incorporated Aircraft flight data acquisition and transmission system
WO2000028701A1 (en) * 1998-11-09 2000-05-18 Cabletron Systems, Inc. Method and apparatus for fair and efficient scheduling of variable size data packets in input buffered switch
EP1009189A2 (en) * 1998-12-08 2000-06-14 Nec Corporation RRGS-round-robin greedy scheduling for input/output buffered terabit switches

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BOGENENI K ET AL: "Low-complexity multiple access protocols for wavelength-division multiplexed photonic networks", IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS. PROTOCOLS FOR GIGABIT NETWORKS, vol. 12, no. 2, February 1993 (1993-02-01), pages 1 - 35, XP002902333 *
DUAN H ET AL: "A high-performance OC-12/OC-48 queue design prototype for input-buffered ATM switches. In: INFOCOM'97. Sixteenth annual joint conference of the IEEE computer and communications societies. Driving the information revolution", PROCEEDINGS IEEE, vol. 1, 7 April 1997 (1997-04-07) - 11 April 1997 (1997-04-11), Kobe, Japan, pages 20 - 28, XP010252017 *

Also Published As

Publication number Publication date
WO2001097469A2 (en) 2001-12-20
AU2001282688A1 (en) 2001-12-24

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