WO2002005285A3 - Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible - Google Patents

Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible Download PDF

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Publication number
WO2002005285A3
WO2002005285A3 PCT/US2001/040768 US0140768W WO0205285A3 WO 2002005285 A3 WO2002005285 A3 WO 2002005285A3 US 0140768 W US0140768 W US 0140768W WO 0205285 A3 WO0205285 A3 WO 0205285A3
Authority
WO
WIPO (PCT)
Prior art keywords
host
flash memory
data
memory unit
memory banks
Prior art date
Application number
PCT/US2001/040768
Other languages
French (fr)
Other versions
WO2002005285A2 (en
Inventor
Petro Estakhri
Original Assignee
Lexar Media Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lexar Media Inc filed Critical Lexar Media Inc
Priority to DE60122155T priority Critical patent/DE60122155T2/en
Priority to JP2002508803A priority patent/JP4945792B2/en
Priority to EP01937811A priority patent/EP1299884B1/en
Priority to AU2001263509A priority patent/AU2001263509A1/en
Publication of WO2002005285A2 publication Critical patent/WO2002005285A2/en
Publication of WO2002005285A3 publication Critical patent/WO2002005285A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A Flash Memory Unit comprises a plurality of memory banks capable of simultaneously programming a plurality of pages into a plurality of data blocks within the respective memory banks. On start up, the Flash Memory System sends a signal to a Host. If the Host fails to respond, the Flash Memory Unit determines that the Host is a standard Host and stores data one page at a time. If the Host responds with a proper signal, the Flash Memory Unit determines that the Host is a high performance Host and stores multiple pages of data simultaneously. The high performance Host is configured to select identical LBA offsets from a plurality of Virtual Logical Blocks of User Data, and send the data defined by these Logical Block Addresses to the Flash Memory Unit for storage. The plurality of Logical Blocks of data are respectively transmitted to a plurality of RAM Data Registers, and simultaneously programmed into their respective memory banks. In sequential steps of programming, data defined by consecutive Logical Block Addresses are stored in Physical Pages defined by consecutive Physical Block Addresses. Data stored by a high performance Host is therefore retrievable by a standard Host.
PCT/US2001/040768 2000-07-07 2001-05-17 Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible WO2002005285A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE60122155T DE60122155T2 (en) 2000-07-07 2001-05-17 FLASH MEMORY ARCHITECTURE FOR IMPLEMENTING SIMULTANEOUS PROGRAMMABLE FLASH MEMORY BANKS WITH HOST COMPATIBILITY
JP2002508803A JP4945792B2 (en) 2000-07-07 2001-05-17 Flash memory system and programming method
EP01937811A EP1299884B1 (en) 2000-07-07 2001-05-17 Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible
AU2001263509A AU2001263509A1 (en) 2000-07-07 2001-05-17 Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/611,676 2000-07-07
US09/611,676 US6721843B1 (en) 2000-07-07 2000-07-07 Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible

Publications (2)

Publication Number Publication Date
WO2002005285A2 WO2002005285A2 (en) 2002-01-17
WO2002005285A3 true WO2002005285A3 (en) 2002-06-20

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/040768 WO2002005285A2 (en) 2000-07-07 2001-05-17 Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible

Country Status (8)

Country Link
US (1) US6721843B1 (en)
EP (2) EP1299884B1 (en)
JP (1) JP4945792B2 (en)
AT (2) ATE336065T1 (en)
AU (1) AU2001263509A1 (en)
DE (2) DE60122155T2 (en)
ES (1) ES2297787T3 (en)
WO (1) WO2002005285A2 (en)

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Also Published As

Publication number Publication date
EP1693759A2 (en) 2006-08-23
US6721843B1 (en) 2004-04-13
DE60122155D1 (en) 2006-09-21
DE60122155T2 (en) 2007-06-28
EP1299884B1 (en) 2006-08-09
AU2001263509A1 (en) 2002-01-21
ES2297787T3 (en) 2008-05-01
EP1299884A2 (en) 2003-04-09
ATE373843T1 (en) 2007-10-15
EP1693759A3 (en) 2006-09-13
JP2004511030A (en) 2004-04-08
JP4945792B2 (en) 2012-06-06
WO2002005285A2 (en) 2002-01-17
ATE336065T1 (en) 2006-09-15
DE60130593T2 (en) 2008-01-31
DE60130593D1 (en) 2007-10-31
EP1693759B1 (en) 2007-09-19

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