带每个棋子性质判断的电子棋盘 Electronic chessboard with judgment of each piece's nature
本发明所属技术领域 TECHNICAL FIELD
本实用新型涉及棋类用品, 特别是电子棋盘。 The utility model relates to chess articles, especially an electronic chess board.
在本发明之前的现有技术 Prior art prior to the present invention
. 传统的棋类运动使用的棋盘只有单一的摆棋功能, 而中国专利 9 0 2 0 0 7 3 6提供的电子棋盘, 只有位置感应, 对于记时难以准确地按竞赛规则记录, 且 对推行棋子, 平移棋子等的误动作无法正确判断, 这样就难以实现电子棋盘应有 的功能。 The board used in traditional chess sports has only a single swing function. The electronic board provided by Chinese patent 9202 0 7 3 6 has only position sensing. It is difficult to accurately record time according to competition rules for timekeeping. The wrong actions of chess pieces, translation pieces, etc. cannot be correctly judged, so it is difficult to realize the functions that an electronic chessboard should have.
本发明的目的 Object of the invention
本实用新型的目的在于提供一种能按竞赛规则准确记录比赛的电子棋盘。 . 本发明的技术方案 The purpose of the utility model is to provide an electronic chessboard which can accurately record a match according to the rules of the match. . Technical Solution of the Invention
本实用新型的技术方案是: 由棋盘、 棋子、 微处理器及显示装置组成, 其特 征在于: 棋盘每个着棋点下部装有一射频发射及接收装置, 每棋子内装有一与棋 子性质对应的特定编码的射频应答装置, 每一发射及接收装置连接一逻辑编码电 路,逻辑编码电路连接微处理器。 The technical solution of the utility model is composed of a chessboard, chess pieces, a microprocessor, and a display device, and is characterized in that: a radio frequency transmitting and receiving device is arranged below each chess point of the chessboard, and each chess piece is equipped with a specific one corresponding to the nature of the chess piece. A coded radio frequency response device, each transmitting and receiving device is connected to a logic coding circuit, and the logic coding circuit is connected to a microprocessor.
本实用新型的优点: 1、 可直接进行自动计时、 记谱, 并对行棋手数给予提 示报警, 避免影响选手水平的正常发挥; 2、 可直接将比赛在显示装置上实时模 拟再现或通过互联网络实时传送比赛的模拟图像、 数据。 Advantages of the utility model: 1. It can directly perform automatic timing and notation, and give a prompt alarm to the number of players, so as to avoid affecting the normal performance of players; 2. It can directly simulate or reproduce the game on the display device in real time or pass The internet transmits real-time simulation images and data of the game.
附图说明 . BRIEF DESCRIPTION OF THE DRAWINGS.
下面通过附图进一步说明本实用新型。 The present invention is further described below with reference to the drawings.
图 1本实用新型棋盘棋子的结构示意图; FIG. 1 is a schematic structural diagram of a chessboard piece of the present invention;
图 2本实用新型的原理图; FIG. 2 is a schematic diagram of the present invention;
图 3逻辑编码电路图; Figure 3 logic coding circuit diagram;
图 4微处理器连接框图。 Figure 4 Block diagram of the microprocessor connection.
图 1中, 棋盘面 11, 位置感应盘 1 2, 射频发射及接收芯片 1 3, 棋子 2, 发射芯片 2 1。 棋盘面下面藏有一位置感应盘 1 2, 位置感应盘 1 2内对应棋盘 的每个着棋点有一射频发射及接收芯片 1 3, 而每一祺子 2内装有一与棋子性质 对应的特定编码的发射芯片 2 1。 每一射频发射及接收芯片 1 3都连接到微处理
器, 将本位置有无祺, 棋的特定编码送微处理器, 微处理器就能判断每个着棋点 有棋是什么棋。 In FIG. 1, a chessboard surface 11, a position sensing plate 12, a radio frequency transmitting and receiving chip 1 3, a chess piece 2, and a transmitting chip 21 are provided. A position sensing board 12 is hidden under the chessboard surface. Each position of the chessboard in the position sensing board 12 has a radio frequency transmitting and receiving chip 1 3, and each of the chess pieces 2 contains a specific code corresponding to the nature of the chess piece. Transmitting chip 2 1. Each RF transmitting and receiving chip 1 3 is connected to the microprocessor The device sends the current position to the microprocessor, and the specific code of the chess is sent to the microprocessor, and the microprocessor can determine what chess is at each position.
实施例 Examples
1、 按棋子下部嵌入一个射频应答芯片, 不改变棋子的外观及手感。 1. A radio frequency response chip is embedded in the lower part of the chess piece, which does not change the appearance and feel of the chess piece.
2、 在每个着棋点下部埋藏一个寻呼器芯片。 榫子内的应答芯片釆用 PHIPS 的 PCF7930或 7931,着棋点下的寻呼器采用 PHIPS 的对应基站 IC用 MFCM200。 (基站 IC感应距离为 20mm)原理图如图 2。 2. A pager chip is buried under each move. The answer chip in the tongue is PCF7930 or 7931 of PHIPS, and the pager under the checker adopts the corresponding base station IC for PHIPS MFCM200. (Base station IC sensing distance is 20mm) The schematic diagram is shown in Figure 2.
对每个着棋点下的进行统一的逻辑编排, 通过基站 IC对 7930或 7931进行 读写操作, 可实现每个着棋点上棋子的有无判断和性质判断。 The unified logical arrangement of each move is performed, and the base station IC reads and writes the 7930 or 7931 to realize the judgment of the presence or absence and the nature of the pieces at each move.
3、 逻辑编码电路如图 3所示, 给出的是 9 0个点实施例 (中国象棋), 国 际象棋、 围棋原理类似, 只在检测点数量有所不同。 3. The logic coding circuit is shown in Figure 3. An example of 90 points (Chinese chess) is given. The principles of international chess and Go are similar, except that the number of detection points is different.
由于不对应答芯片进行编程操作, 将基站 IC 的数据输入线屏蔽, 数据输出 线接在多路模拟开关的输出端, 微处理器对译码电路及多路模拟开关提供地址编 码, 选通某一路模拟开关, 输出端将基站 IC读取的数据送至微处理器的串行口 中进行处理。 图中: IC7(74HC244)为总线驱动器, 用以提高负载能力 IC1-IC6为 16位模拟开关 4067,可组成 6 X 16=96路的多路输入一路输出的多路开关 (这里只 用到 90路),由微处理提供 8位的地址线,低 4位地址通过 244的驱动接到每片 4067 的编码端 (S0、 Sl、 S2、 S3)高 4位中的低 3位分别接在 3-8位 IC8译码器 138的 编码端 A、 B、 C译码器的输出 Y0-Y5分别接在 6片 4067的片选端上, 96路多路 开关可由 8位连续的编码选通。 Because the response chip is not programmed, the data input line of the base station IC is shielded, and the data output line is connected to the output end of the multi-channel analog switch. The microprocessor provides address coding for the decoding circuit and the multi-channel analog switch, and selects a channel. Analog switch, the output end sends the data read by the base station IC to the serial port of the microprocessor for processing. In the picture: IC7 (74HC244) is a bus driver, used to improve the load capacity. IC1-IC6 is a 16-bit analog switch 4067, which can form 6 X 16 = 96 multi-input, one-output multi-switch (only 90 is used here). The 8-bit address line is provided by the microprocessor.The lower 4 bits of the address are connected to the encoding end (S0, Sl, S2, S3) of each 4067 through the 244 driver.The lower 3 bits of the upper 4 bits are connected to 3 respectively. The outputs Y0-Y5 of the encoder A, B, and C decoders of the 8-bit IC8 decoder 138 are connected to 6 chip select terminals of 4067 respectively. The 96-channel multiplexer can be gated by 8-bit continuous code.
4、 微处理器部分如图 4所示:实施例中采用的是 51系列单片机。 由 P1口提 供连续的地址编码用以选通逻辑编码电路 ,Κ)口作为数据总线 ,ΡΟ口、 Ρ2口作为地 址总线,对所有的外接功能电路 (如 LCD显示电路、 LED电路、 键盘、 CRT控制板 等)统一编址,用译码电路选通接口电路。 多路开关的输出端经一门电路送至串口, 由单片机读入数据,该门电路由 P3、 4端控制开启,串行通信口接有电平转换电路 (232或 485),可与上位机或调制解调器相匹实现数据传送的功能。
4. The microprocessor part is shown in Figure 4. The 51 series single-chip microcomputer is used in the embodiment. The P1 port provides continuous address coding for strobe logic coding circuit, and K) port is used as the data bus, and P0 and P2 ports are used as the address bus. For all external function circuits (such as LCD display circuit, LED circuit, keyboard, CRT) Control board, etc.) unified addressing, and the interface circuit is gated with a decoding circuit. The output end of the multiplex switch is sent to the serial port through a gate circuit, and the data is read by the microcontroller. The gate circuit is controlled to be opened by P3 and 4 terminals. Machine or modem to match the data transmission function.