WO2002023594A2 - Apparatus and method for reducing contamination on thermally processed semiconductor substrates - Google Patents
Apparatus and method for reducing contamination on thermally processed semiconductor substrates Download PDFInfo
- Publication number
- WO2002023594A2 WO2002023594A2 PCT/EP2001/009969 EP0109969W WO0223594A2 WO 2002023594 A2 WO2002023594 A2 WO 2002023594A2 EP 0109969 W EP0109969 W EP 0109969W WO 0223594 A2 WO0223594 A2 WO 0223594A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- chamber
- silica
- silicon
- reactive gas
- flange
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
- C23C16/4404—Coatings or surface treatment on the inside of the reaction chamber or on parts thereof
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/08—Reaction chambers; Selection of materials therefor
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
- C30B31/06—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor by contacting with diffusion material in the gaseous state
- C30B31/10—Reaction chambers; Selection of materials therefor
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/005—Oxydation
Definitions
- This invention relates to the field of thermal processing of semiconductor substrates, and, more particularly, to reducing metal contamination, such as aluminum iron and copper contamination, on the surface of thermally processed semiconductor substrates.
- Deposition techniques include processes such as physical vapor deposition (PND), chemical vapor deposition (CND), sputtering, and immersion of the substrate into an electrolyte solution. Following such deposition, the semiconductor substrates may be heated to elevated temperatures in ovens or rapid thermal processing (RTP) chambers to anneal the structures formed thereon.
- PND physical vapor deposition
- CND chemical vapor deposition
- RTP rapid thermal processing
- a large number of semiconductor substrates are formed from silicon.
- heat- treating or thermal processing of silicon wafers takes place in an RTP chamber.
- Each wafer is individually placed within an RTP reaction chamber formed primarily of quartz, and certain components of the chamber may be formed from stainless steel, aluminum or other generally non-corrosive material.
- RTP chamber elements associated with the RTP chamber that may be formed from stainless steel and/or aluminum.
- Untreated stainless steel surfaces generally contain some free iron (Fe) and iron oxide (FeO) in thousands of minute inclusions, cracks and crannies within the surfaces. Other possible heavy metal surface contaminants, such as free nickel, may also be present.
- FeO FeO
- electropolished steel may be used. During electropolishing, the exposed steel surface is immersed in a heated electrolytic bath that contains metal plates connected to a cathode (negative terminal). An anode is connected to the steel surface. When a direct current is applied, the electrical reaction causes an ionic conduction that removes particles of metal from the steel surface. The unwanted Fe scales, protrusions, nooks and crannies are normally first to be removed in the electrolytic reaction. The end result is less free Fe on the steel surfaces.
- the stainless steel may be coated with Teflon or a solid polymer material. The coating holds contaminant heavy metal particles onto the steel surface. Unfortunately, such coatings cannot withstand temperatures over about 300°C, and RTP processes may exceed 1000°C, in which case the temperatures of associated elements of the reaction chamber often exceeds 300°C.
- an electropolished stainless steel surface may be passivated by being immersed in an acid (such as citric or nitric acid), as recommended by standards, such as ASTM 380-99.
- an acid such as citric or nitric acid
- ASTM 380-99 an acid bath
- the free iron is removed and the steel surface undergoes an oxidation in which the Cr, Ni and Mo are oxidized very quickly to form an extra protective coating.
- the protective layer of CrO is much thicker and more effective against corrosion than the CrO layer formed with natural passivation.
- the steel surface may not always be sealed uniformly and completely enough to protect the reaction chamber components and associated elements formed from such steel against corrosion and subsequent release of metallic elements that contaminate thermally processed semiconductor substrates.
- the stainless steel itself may be specially fabricated to resist corrosion.
- VIM-VAR vacuum induction melting-vacuum arc remelting
- An apparatus for thermal processing a semiconductor substrate, such as a silicon semiconductor wafer, with reactive gases has a reaction chamber for processing the substrate with the reactive gas when the substrate is held within the chamber.
- reactive gases such as e.g. steam, oxygen, hydrogen, nitrogen, NH 3 , N O, NO, chlorine containing gas, oxygen containing gas, nitrogen containing gas, ozone, hydrocarbon compounds, metal-organic compounds, radicals or a combination of such gases.
- a reaction chamber for processing the substrate with the reactive gas when the substrate is held within the chamber.
- At least one element forming a part of or associated with the reaction chamber and adapted for contacting the reactive gas introduced into the chamber is formed of a metal coated with a layer comprising silicon or a silica-containing compound.
- the base metal that is coated with the silicon or silica-containing compound is selected from stainless steel, 316L stainless steel, 316L-SCQ stainless steel, 317LM stainless steel or aluminum or an aluminum alloy.
- Other stainless steels with similar compositions to those of 316L, 317LM and 316L-SCQ could be used.
- the silicon or silica-containing layer preferably is SiO 2 or Si 3 N 4 .
- a method for reducing metal contamination on surfaces of a semiconductor substrate when said substrates are thermal processed according to this invention includes the steps of: (a) providing a reaction chamber with at least one element constructed of a metal forming a part of or associated with said chamber and adapted for contacting a reactive gas introduced into the chamber, wherein at least a portion of said element that is adapted for contacting the reactive gas is coated with a silicon or silica-containing layer;
- the at least one element constructed of metal is constructed of stainless steel, 316L stainless steel, 316L-SCQ stainless steel or 317LM stainless steel or any of the steels mentioned above.
- the metal also can be aluminum or an aluminum alloy.
- the level of iron contamination can be further reduced to levels below 1 E10/cm ⁇ Nickel, zinc, copper, magnesium and other heavy metal surface contaminants are reduced to applicable acceptable levels as well.
- a further advantage of the method in which metal elements are coated with a silicon or silica-containing layer is that the corrosion rate of that metal is reduced when steam or chlorine- containing reactive gases are used in the thermal processing.
- the advantages of the invention are best obtained when all metal elements of the reaction chamber and associated with the reaction chamber that come into contact with steam or other reactive gases are coated with a silicon or silica-containing layer.
- One such element associated with the reaction chamber is a flange that is attached to the reaction chamber at the inlet for reactive gases.
- the flange preferably is constructed of a metal, such as stainless steel, and at least the portion of the flange adapted for contacting the reactive gas is coated with a silicon or silica-containing layer.
- a flange that is attached to the chamber at the outlet for reactive gases.
- the flange preferably is constructed of a metal, such as stainless steel, and at least the portion of the flange adapted for contacting the reactive gas is coated with a silicon or silica-containing layer.
- Other flanges such as, e.g., a nitrogen curtain flange, that may come into contact with the reactive gases preferably are also constructed of a silica or silicon-coated metal.
- various tubes associated with the inlet and/or outlet to the reaction chamber may be constructed of a metal, and have at least the portion of the tubes adapted for contacting the reactive gases coated with a silicon or silica- containing layer.
- the silicon or silica-containing layer is applied to the metal (preferably stainless steel or aluminum) to a coating thickness greater than about 1000D, and preferably in the range of about 1200 A to about 4800 A. Good results have been achieved when the silica-containing layer is applied to the stainless steel parts with a chemical vapor deposition (CVD) process using silica in a vacuum at a temperature in the range of 300°C to 400°C. In the most preferred embodiment, the silicon or silica-containing layer is applied to all stainless steel surfaces of parts of the reaction chamber or associated with the reaction chamber that may come into contact with the reactive gases. For aluminum parts, the silica-containing layer is preferably applied with a chemical vapor deposition (CVD) process using silica in a vacuum at a temperature in the range of 200°C to 600°C.
- CVD chemical vapor deposition
- the present invention focuses on coating metal elements of or associated with a reaction chamber for a thermal processing system, especially a rapid thermal processing (RTP) system, in which reactive gases are used for thermal processing of semiconductor substrates, such as silicon semiconductor wafers.
- the metal elements that come into contact with the reactive gases are at least partly coated with a silicon or silica-containing layer to reduce contamination on the semiconductor substrate that might otherwise be caused by the metal and/or impurities or alloy elements contained in the metal elements liberated therefrom by reaction with the reactive gases.
- the coating layer also may have an advantage in reducing the corrosion rate of the metal elements if the thermal processing is conducted with reactive gases that may cause corrosion of unprotected metal.
- the coating layer protects the semiconductor substrate (i.e., a silicon wafer) from contaminants that otherwise would be emitted when the metal elements corrode.
- compositions for the coating layer may be chosen, depending upon the composition of the semiconductor substrate being processed in the reaction chamber.
- the coating layer composition is chosen to complement the composition of the semiconductor substrate.
- the coating layer for the metal elements of the reaction chamber and associated with the reaction chamber comprise at least one element of the compound semiconductor wafer - silicon or silica-containing if the compound semiconductor wafer is silicon carbide (SiC) and/or silicon, SiC, SiO or Si 3 N 4 .
- FIG. 1 is a schematic cross-sectional view in side elevation of a stainless steel reaction chamber, nitrogen supply, steam generator and semiconductor substrate transport device;
- FIG. 2 is a schematic cross-sectional view taken along line 2-2 in FIG. 1 ;
- FIG. 3 is a schematic cross-sectional view taken along line 3-3 in FIG. 1; and FIG. 4 is a schematic cross-sectional view taken along line 4-4 in FIG 1.
- FIG. 1 there is shown a schematic of a cross section in side elevation of the components of an example stainless steel RTP processing chamber 100.
- the reaction chamber 20 houses a quartz sleeve 22.
- the quartz sleeve 22 defines an envelope into which a semiconductor substrate, such as a semiconductor wafer 30, is inserted and from which said substrate is extracted.
- the quartz sleeve has an inlet 23.
- the semiconductor wafer 30 is held upon supports 28 while positioned within the quartz sleeve 22 inside the cavity of the reaction chamber 20 (See also FIG. 3).
- an aluminum RTP processing chamber typically does not incorporate a quartz sleeve and the steam and process gases introduced into the chamber will contact the chamber surfaces.
- the robot 14 is provided with an arm 16 that selectively reciprocates back and forth in the directions as indicated by arrow 17.
- the top array has a series of fourteen heat lamps 32 disposed substantially parallel to one another.
- the bottom array has a series of fourteen heat lamps 32' disposed substantially parallel to one another and substantially perpendicularly to the lamps 32 in the top array.
- the heat lamps are activated to heat a semiconductor substrate and reactive gases held within the quartz sleeve envelope 22.
- the quartz walls of the sleeve 22 remain cooler than the semiconductor substrate 30.
- Typical RTP treatments such as, for example, described in prior U.S. Patent Nos.
- 4,331,485, 4,356,384 and 4,680,451 involve heating the semiconductor substrate from room temperature to a prescribed elevated process temperature, such as from 200°C to 1700°C in a matter of 1 to 300 seconds.
- the semiconductor substrate 30 is held at that elevated temperature for only a short time, such as 30 to 60 seconds.
- the temperature and time selected depend upon the processing or treatment intended for the semiconductor substrate and the type of semiconductor material.
- silicon semiconductor wafers there are mainly two types of heat treatment applications: first, an implant annealing or film annealing or restructuring process; and second, a film growing process, such as the formation of an SiO 2 layer of a certain thickness on the semiconductor substrate.
- Most processing for silicon semiconductor wafers uses temperatures below 1250°C and process times between 1 and 180 seconds.
- the quartz sleeve 22 of the reaction chamber 20 is held between a rear gas flange 46 and a process exhaust flange 7.
- a front nitrogen curtain flange 24 preferably is also provided adjacent the exhaust flange 7. Nitrogen gas flows into the quartz sleeve 22 from the nitrogen supply 12 through an inlet 26 into the nitrogen curtain flange 24, then into the reaction chamber 20 and all the way into the flange 6 to prevent air or other atmospheric contaminants from entering the sleeve 22 when the chamber door (not shown) is opened.
- the chamber door is opened to permit a semiconductor wafer 30 to be inserted into or extracted from the chamber 20 and sleeve 22.
- the door remains closed when the semiconductor wafer is thermally processed within the chamber.
- the nitrogen curtain flange 24, shown in Figures 1 and 4 is formed from stainless steel and is connected to a series of tubes 45, also formed of stainless steel.
- the nitrogen curtain flange 24, including its inlet passageway 26 and inner cavity 27 and all openings through which reactive gases may contact, is coated with a silicon or silica-containing layer to a coating thickness of about from 1200 and 4800A.
- the steam and process gas inlet flange 18, shown in Figures 1 and 3, is formed from stainless steel and is connected to a series of tubes 50 through which the reactive gas, such as steam or water vapor in the preferred embodiment, passes.
- the steam and process gas inlet flange 18 further defines an inner cavity 42 that communicates with the interior 23 of the quartz envelope 22 and through which the robotic transfer system 14 inserts and extracts the semiconductor wafer 30 into and out of the quartz envelope 22.
- the steam and process gas inlet flange 18, including its inlet passageway 44 and inner cavity 42 and all openings through which reactive gases may contact, is coated with a silicon or silica-containing layer to a coating thickness of about 1200 to 480 ⁇ A.
- a process gas exhaust flange 7 Associated with the reaction chamber 20 and adjacent to the quartz sleeve 22, and preferably adjacent to the nitrogen curtain flange 24, is a process gas exhaust flange 7, shown in
- the exhaust flange 7 selectively exhausts reactive gases that come from the gas inlet flange 18 and through the reaction chamber quartz sleeve 22.
- the exhaust flange 7 defines an imier cavity 23 that communicates with the interior of the quartz sleeve 22 envelope.
- the inner cavity 23 communicates with an outlet 45 for the exliaust.
- the exhaust flange 7 preferably also serves as a means for conducting oxygen sampling for the gaseous contents held within the chamber 20.
- the exhaust flange 7 is formed from stainless steel and is coated with a silicon or silica-containing layer to a coating thickness of about 1200 to 4800A.
- the rear flange 6 defines a central cavity 40 and an outlet 38 for leaking nitrogen. During thermal processing, leaking nitrogen preferably is exhausted from the central cavity 40 outside the O-rings (not shown) in flange 6.
- the rear flange 6 is formed of stainless steel.
- the central cavity 40 and all passageways through which gases may flow in the nitrogen curtain flange 6 are coated with a silicon or silica-containing layer to a uniform thickness of about 1200 to 4800A.
- any stainless steel tubing assemblies through which reactive gases may pass are also coated with a silicon or silica-containing layer.
- the stainless steel tubing 50 that connects the gas supply (steam generator 10 in the preferred embodiment) to the gas inlet flange 18 is also coated with silicon at a coating thickness of about 1200 to 4800 A.
- the stainless steel tubing 48 that connects the nitrogen supply 12 to the nitrogen curtain flange 24 and the stainless steel tubing 52 used for exhaust are coated with a protective silicon or silica- containing layer.
- the silicon or silica-containing layer is applied to the stainless steel using a chemical vapor deposition (CVD) process, in which the stainless steel parts are placed in a closed chamber. A vacuum is drawn in this chamber, and silica is deposited on the metal surfaces at a temperature in the range of 300°C to 400°C.
- the silica-containing coating is ⁇ a applied to a thickness of from 1200 A to 4800 A.
- Such silica-containing coated stainless steel is stable to temperatures over 600°C. Thicker coatings may be more apt to shed particles, and thinner coatings may not sufficiently protect the steel surface from corrosion or particle emission.
- Restek Corporation of Bellefonte, Pennsylvania USA uses such a CVD process to apply inert silica coatings to stainless steel, which Restek calls the SILICOSTEEL® process.
- SILICOSTEEL a layer of inert silica is permanently bonded to the base metal to improve corrosion resistance by shielding the base metal from mineral acids and alcohols.
- stainless steel flanges and tubing coated with silicon/silica using the SILICOSTEEL process were incorporated into a RTP thermal processing apparatus of the preferred embodiment, the semiconductor substrates processed in the RTP apparatus had lower iron contamination than those processed in an apparatus without silicon coated parts.
- the silicon or silica-containing layer preferably is applied using a CVD process conducted at temperatures in the range of about 200°C to 600°C.
- the silica-containing coating is applied to the aluminum to a thicl ⁇ iess of at least about 1000A (lOOnm).
- the corrosion resistivity to steam or thermal process gases may be improved by more than a factor of 10 when an SiO -coating is applied. Tests were conducted to investigate whether and to what extent a silicon or silica- containing coating on stainless steel would reduce corrosion etching weight loss, and thus the likely contamination of semiconductor substrates.
- Stainless steel coupons of various grades, 316L, 317LM and 316L-SCQ were prepared. Table I shows the typical compositions for these grades of stainless steel. Table II shows the results of experiments to study the corrosion rate as a function of the substrate material, silicon coating thickness, treatments and steel surface finish.
- Table II shows the results of experiments to study the corrosion rate as a function of the substrate material, silicon coating thickness, treatments and steel surface finish.
- Several samples of 316L stainless steel were electropolished. Two of these samples were also passivated for expected increased corrosion resistance. All of the stainless steel samples were immersed in an 18%) hydrochloric acid solution for 24 hours to determine the corrosion rates with and without a silica-containing coating applied. The coated samples were then immersed in the hydrochloric acid solution for 24 hours to determine the corrosion rates. Additional details and the results of the tests are set forth in Table II below.
- silica-coated 316L stainless steel samples exhibit improved corrosion resistance by a factor of 5 to 6 over uncoated steel of equivalent grade, whether electropohshed only or also passivated.
- the corrosion rate expressed in 100 times grams per hour per square centimeter of sample surface area, was assessed by measuring weight loss after the sample was immersed 24 hours in the 18 > hydrochloric acid solution.
- the surface finish before coating should be better than about 60 micro-inch, preferably better than 25 micro-inch, and most preferably in the range between 1 and 20 micro-inch. Taking into account the costs for preparing a high quality surface finish, sufficiently good results are achieved with 16 micro-inch. However, if the requirements of Fe or FeO contamination levels become more exacting in the future, a higher surface finish quality may become necessary.
- the reactive gas for processing the semiconductor substrate comprises chlorine
- the test results show that preferably steel with a higher Mo concentration, like 317LM, may be selected for forming the metal elements to be coated.
- a non-coated 317LM stainless steel had the best corrosion resistivity of all non-coated steels, with the non-coated 316L-SCQ stainless steel having a rate similar to that of ordinary 316L stainless steel.
- the 316L- SCQ surface has lower surface contaminants, after coating, it had a higher corrosion resistivity against corrosion by HC1 than the other samples.
- the silicon or silica-containing coating is influenced by surface impurities such as Na and K, which are lower for the 316L-SCQ due to its VIM-VAR processing.
- Special steel with a higher Mo concentration (such as above 3% like 317LM), may also undergo the VIM-VAR processing, and this may additionally increase the corro sion resistivity against HC1.
- coated samples resisted emitting Fe particles and demonstrated greater corrosion resistance than the uncoated samples.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-7003575A KR20030031183A (en) | 2000-09-15 | 2001-08-30 | Apparatus and method for reducing contamination on thermally processed semiconductor substrates |
EP01971981A EP1323182A2 (en) | 2000-09-15 | 2001-08-30 | Apparatus and method for reducing contamination on thermally processed semiconductor substrates |
JP2002527548A JP2004509461A (en) | 2000-09-15 | 2001-08-30 | Apparatus and method for reducing contamination of a heat treated semiconductor substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US66394600A | 2000-09-15 | 2000-09-15 | |
US09/663,946 | 2000-09-15 |
Publications (2)
Publication Number | Publication Date |
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WO2002023594A2 true WO2002023594A2 (en) | 2002-03-21 |
WO2002023594A3 WO2002023594A3 (en) | 2002-06-06 |
Family
ID=24663865
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/EP2001/009969 WO2002023594A2 (en) | 2000-09-15 | 2001-08-30 | Apparatus and method for reducing contamination on thermally processed semiconductor substrates |
Country Status (5)
Country | Link |
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EP (1) | EP1323182A2 (en) |
JP (1) | JP2004509461A (en) |
KR (1) | KR20030031183A (en) |
TW (1) | TW516129B (en) |
WO (1) | WO2002023594A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150069407A1 (en) * | 2012-04-26 | 2015-03-12 | Sharp Kabushiki Kaisha | Group iii nitride semiconductor multilayer substrate and group iii nitride semiconductor field effect transistor |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100791010B1 (en) * | 2007-01-12 | 2008-01-03 | 삼성전자주식회사 | Apparatus for fabricating semiconductor products and method of processing semiconductor substrates using the same |
CN112658605B (en) * | 2020-12-11 | 2022-03-25 | 无锡市星达石化配件有限公司 | Machining process for oversized outer circular flange |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0387656A1 (en) * | 1989-03-14 | 1990-09-19 | Fujitsu Limited | Chemical vapor deposition method |
US5599732A (en) * | 1995-08-21 | 1997-02-04 | Northwestern University | Method for growing III-V semiconductor films using a coated reaction chamber |
US5647953A (en) * | 1995-12-22 | 1997-07-15 | Lam Research Corporation | Plasma cleaning method for removing residues in a plasma process chamber |
US5654043A (en) * | 1996-10-10 | 1997-08-05 | Eaton Corporation | Pulsed plate plasma implantation system and method |
US5972114A (en) * | 1995-03-10 | 1999-10-26 | Tokyo Electron Limited | Film deposition apparatus with anti-adhesion film and chamber cooling means |
-
2001
- 2001-08-30 KR KR10-2003-7003575A patent/KR20030031183A/en not_active Application Discontinuation
- 2001-08-30 EP EP01971981A patent/EP1323182A2/en not_active Withdrawn
- 2001-08-30 WO PCT/EP2001/009969 patent/WO2002023594A2/en active Application Filing
- 2001-08-30 JP JP2002527548A patent/JP2004509461A/en active Pending
- 2001-09-12 TW TW090122662A patent/TW516129B/en not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0387656A1 (en) * | 1989-03-14 | 1990-09-19 | Fujitsu Limited | Chemical vapor deposition method |
US5972114A (en) * | 1995-03-10 | 1999-10-26 | Tokyo Electron Limited | Film deposition apparatus with anti-adhesion film and chamber cooling means |
US5599732A (en) * | 1995-08-21 | 1997-02-04 | Northwestern University | Method for growing III-V semiconductor films using a coated reaction chamber |
US5647953A (en) * | 1995-12-22 | 1997-07-15 | Lam Research Corporation | Plasma cleaning method for removing residues in a plasma process chamber |
US5654043A (en) * | 1996-10-10 | 1997-08-05 | Eaton Corporation | Pulsed plate plasma implantation system and method |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150069407A1 (en) * | 2012-04-26 | 2015-03-12 | Sharp Kabushiki Kaisha | Group iii nitride semiconductor multilayer substrate and group iii nitride semiconductor field effect transistor |
Also Published As
Publication number | Publication date |
---|---|
WO2002023594A3 (en) | 2002-06-06 |
KR20030031183A (en) | 2003-04-18 |
JP2004509461A (en) | 2004-03-25 |
EP1323182A2 (en) | 2003-07-02 |
TW516129B (en) | 2003-01-01 |
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