WO2002027481A3 - System and method for pre-fetching for pointer linked data structures - Google Patents

System and method for pre-fetching for pointer linked data structures Download PDF

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Publication number
WO2002027481A3
WO2002027481A3 PCT/US2001/030225 US0130225W WO0227481A3 WO 2002027481 A3 WO2002027481 A3 WO 2002027481A3 US 0130225 W US0130225 W US 0130225W WO 0227481 A3 WO0227481 A3 WO 0227481A3
Authority
WO
WIPO (PCT)
Prior art keywords
cache
data
memory system
lines
fetching
Prior art date
Application number
PCT/US2001/030225
Other languages
French (fr)
Other versions
WO2002027481A2 (en
Inventor
Peter C Damron
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/677,092 external-priority patent/US6668307B1/en
Priority claimed from US09/677,090 external-priority patent/US6782454B1/en
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AU2001294788A priority Critical patent/AU2001294788A1/en
Priority to EP01975464A priority patent/EP1320801A2/en
Publication of WO2002027481A2 publication Critical patent/WO2002027481A2/en
Publication of WO2002027481A3 publication Critical patent/WO2002027481A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A system and method are provided for improved handling of data in a memory system (305). In one embodiment, the memory system (305) has at least one cache (335) with several cache-lines (360) capable of caching data therein. In the method, a cache address space is provided for each cache (335) and special instructions are generated and inserted into the program to directly control caching of data in at least one of the cache-lines (360). Special instructions received in the cache memory system (305) are then executed to cache the data. The special instructions can be generated by a compiler during compiling of the program. Where the cache memory system (305) includes a set-associative-cache having a number of sets each with several cache-lines (360), the method can further include the step of determining which cache-line in a set to flush to main-memory (315) before caching new data to the set.
PCT/US2001/030225 2000-09-29 2001-09-26 System and method for pre-fetching for pointer linked data structures WO2002027481A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2001294788A AU2001294788A1 (en) 2000-09-29 2001-09-26 System and method for pre-fetching for pointer linked data structures
EP01975464A EP1320801A2 (en) 2000-09-29 2001-09-26 System and method for pre-fetching for pointer linked data structures

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/677,092 US6668307B1 (en) 2000-09-29 2000-09-29 System and method for a software controlled cache
US09/677,092 2000-09-29
US09/677,090 US6782454B1 (en) 2000-09-29 2000-09-29 System and method for pre-fetching for pointer linked data structures
US09/677,090 2000-09-29

Publications (2)

Publication Number Publication Date
WO2002027481A2 WO2002027481A2 (en) 2002-04-04
WO2002027481A3 true WO2002027481A3 (en) 2002-12-19

Family

ID=27101704

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/030225 WO2002027481A2 (en) 2000-09-29 2001-09-26 System and method for pre-fetching for pointer linked data structures

Country Status (3)

Country Link
EP (1) EP1320801A2 (en)
AU (1) AU2001294788A1 (en)
WO (1) WO2002027481A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108874691B (en) * 2017-05-16 2021-04-30 龙芯中科技术股份有限公司 Data prefetching method and memory controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0723221A2 (en) * 1995-01-20 1996-07-24 Hitachi, Ltd. Information processing apparatus for prefetching data structure either from a main memory or its cache memory
US5652858A (en) * 1994-06-06 1997-07-29 Hitachi, Ltd. Method for prefetching pointer-type data structure and information processing apparatus therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652858A (en) * 1994-06-06 1997-07-29 Hitachi, Ltd. Method for prefetching pointer-type data structure and information processing apparatus therefor
EP0723221A2 (en) * 1995-01-20 1996-07-24 Hitachi, Ltd. Information processing apparatus for prefetching data structure either from a main memory or its cache memory

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KARLSSON M ET AL: "A prefetching technique for irregular accesses to linked data structures", HIGH-PERFORMANCE COMPUTER ARCHITECTURE, 2000. HPCA-6. PROCEEDINGS. SIXTH INTERNATIONAL SYMPOSIUM ON TOULUSE, FRANCE 8-12 JAN. 2000, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 8 January 2000 (2000-01-08), pages 206 - 217, XP010371910, ISBN: 0-7695-0550-3 *

Also Published As

Publication number Publication date
EP1320801A2 (en) 2003-06-25
WO2002027481A2 (en) 2002-04-04
AU2001294788A1 (en) 2002-04-08

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