WO2002033556A3 - Dynamic queuing structure for a memory controller - Google Patents

Dynamic queuing structure for a memory controller Download PDF

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Publication number
WO2002033556A3
WO2002033556A3 PCT/US2001/029850 US0129850W WO0233556A3 WO 2002033556 A3 WO2002033556 A3 WO 2002033556A3 US 0129850 W US0129850 W US 0129850W WO 0233556 A3 WO0233556 A3 WO 0233556A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
attributes
control unit
service instructions
memory controller
Prior art date
Application number
PCT/US2001/029850
Other languages
French (fr)
Other versions
WO2002033556A2 (en
Inventor
Liuxi Yang
Tung Pham
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AU2001293027A priority Critical patent/AU2001293027A1/en
Publication of WO2002033556A2 publication Critical patent/WO2002033556A2/en
Publication of WO2002033556A3 publication Critical patent/WO2002033556A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

Abstract

A memory management system is disclosed including a processor, a memory control unit coupled to the processor, and a memory coupled to the memory control unit. The memory is configured in a plurality of banks, where the memory control unit includes a dynamic queuing structure, a pointer register defining a plurality of queues associated with the plurality of banks of the memory, an attributes register configured to store attributes of memory service instructions, a content addressable memory configured to store memory access addresses of the memory service instructions, and a queue control configured to control placement of memory service instructions in the plurality of queues based upon the attributes and the memory access address thereof.
PCT/US2001/029850 2000-10-19 2001-09-24 Dynamic queuing structure for a memory controller WO2002033556A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001293027A AU2001293027A1 (en) 2000-10-19 2001-09-24 Dynamic queuing structure for a memory controller

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69230400A 2000-10-19 2000-10-19
US09/692,304 2000-10-19

Publications (2)

Publication Number Publication Date
WO2002033556A2 WO2002033556A2 (en) 2002-04-25
WO2002033556A3 true WO2002033556A3 (en) 2003-08-21

Family

ID=24780042

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/029850 WO2002033556A2 (en) 2000-10-19 2001-09-24 Dynamic queuing structure for a memory controller

Country Status (2)

Country Link
AU (1) AU2001293027A1 (en)
WO (1) WO2002033556A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7418540B2 (en) 2004-04-28 2008-08-26 Intel Corporation Memory controller with command queue look-ahead
US20060064535A1 (en) * 2004-09-22 2006-03-23 Walker Robert M Efficient multi-bank memory queuing system
US8327057B1 (en) * 2007-04-16 2012-12-04 Juniper Networks, Inc. Ordering write bursts to memory
JP4746699B1 (en) * 2010-01-29 2011-08-10 株式会社東芝 Semiconductor memory device and control method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5375215A (en) * 1990-11-09 1994-12-20 Hitachi, Ltd. Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US6092158A (en) * 1997-06-13 2000-07-18 Intel Corporation Method and apparatus for arbitrating between command streams

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5375215A (en) * 1990-11-09 1994-12-20 Hitachi, Ltd. Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US6092158A (en) * 1997-06-13 2000-07-18 Intel Corporation Method and apparatus for arbitrating between command streams

Also Published As

Publication number Publication date
AU2001293027A1 (en) 2002-04-29
WO2002033556A2 (en) 2002-04-25

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