WO2002045134A3 - Gate process for dram array and logic devices on same chip - Google Patents

Gate process for dram array and logic devices on same chip Download PDF

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Publication number
WO2002045134A3
WO2002045134A3 PCT/US2001/051214 US0151214W WO0245134A3 WO 2002045134 A3 WO2002045134 A3 WO 2002045134A3 US 0151214 W US0151214 W US 0151214W WO 0245134 A3 WO0245134 A3 WO 0245134A3
Authority
WO
WIPO (PCT)
Prior art keywords
array
gate conductor
dielectric
support device
support
Prior art date
Application number
PCT/US2001/051214
Other languages
French (fr)
Other versions
WO2002045134A2 (en
Inventor
Ramachandra Divakaruni
Mary E Weybright
Peter Horn
Gary Bronner
Richard A Conti
Uwe Schroeder
Jeffrey Peter Gambino
Original Assignee
Infineon Technologies Corp
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp, Ibm filed Critical Infineon Technologies Corp
Priority to DE60133214T priority Critical patent/DE60133214T2/en
Priority to KR10-2003-7006533A priority patent/KR100533511B1/en
Priority to EP01988493A priority patent/EP1334517B1/en
Publication of WO2002045134A2 publication Critical patent/WO2002045134A2/en
Publication of WO2002045134A3 publication Critical patent/WO2002045134A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.
PCT/US2001/051214 2000-11-15 2001-11-13 Gate process for dram array and logic devices on same chip WO2002045134A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE60133214T DE60133214T2 (en) 2000-11-15 2001-11-13 GATE MANUFACTURING PROCESS FOR THE DRAM AREA AND LOGIC COMPONENTS ON THE SAME CHIP
KR10-2003-7006533A KR100533511B1 (en) 2000-11-15 2001-11-13 Modified gate processing for optimized definition of array and logic devices on same chip
EP01988493A EP1334517B1 (en) 2000-11-15 2001-11-13 Gate fabrication process for dram array and logic devices on same chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/713,272 2000-11-15
US09/713,272 US6403423B1 (en) 2000-11-15 2000-11-15 Modified gate processing for optimized definition of array and logic devices on same chip

Publications (2)

Publication Number Publication Date
WO2002045134A2 WO2002045134A2 (en) 2002-06-06
WO2002045134A3 true WO2002045134A3 (en) 2003-04-03

Family

ID=24865486

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/051214 WO2002045134A2 (en) 2000-11-15 2001-11-13 Gate process for dram array and logic devices on same chip

Country Status (5)

Country Link
US (2) US6403423B1 (en)
EP (1) EP1334517B1 (en)
KR (1) KR100533511B1 (en)
DE (1) DE60133214T2 (en)
WO (1) WO2002045134A2 (en)

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DE10234931A1 (en) * 2002-07-31 2004-02-26 Advanced Micro Devices, Inc., Sunnyvale Production of a gate electrode of a MOST comprises determining the height of a metal silicide layer formed in a crystalline layer, selecting a design height for the metal silicide layer, and further processing
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US6734089B1 (en) * 2003-01-16 2004-05-11 Micron Technology Inc Techniques for improving wordline fabrication of a memory device
US6828181B2 (en) * 2003-05-08 2004-12-07 International Business Machines Corporation Dual gate material process for CMOS technologies
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US7074666B2 (en) * 2004-07-28 2006-07-11 International Business Machines Corporation Borderless contact structures
US7485910B2 (en) * 2005-04-08 2009-02-03 International Business Machines Corporation Simplified vertical array device DRAM/eDRAM integration: method and structure
US7462534B2 (en) * 2005-08-02 2008-12-09 Micron Technology, Inc. Methods of forming memory circuitry
US20070200149A1 (en) * 2006-02-28 2007-08-30 Veronika Polei Semiconductor device and method of production
JP4921837B2 (en) * 2006-04-14 2012-04-25 株式会社東芝 Manufacturing method of semiconductor device
US7858514B2 (en) * 2007-06-29 2010-12-28 Qimonda Ag Integrated circuit, intermediate structure and a method of fabricating a semiconductor structure
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US20090159947A1 (en) * 2007-12-19 2009-06-25 International Business Machines Corporation SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION
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US8530971B2 (en) 2009-11-12 2013-09-10 International Business Machines Corporation Borderless contacts for semiconductor devices
US8907405B2 (en) 2011-04-18 2014-12-09 International Business Machines Corporation Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures
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Also Published As

Publication number Publication date
DE60133214T2 (en) 2009-04-23
EP1334517A2 (en) 2003-08-13
US6403423B1 (en) 2002-06-11
US20020111025A1 (en) 2002-08-15
KR20030060933A (en) 2003-07-16
KR100533511B1 (en) 2005-12-06
EP1334517B1 (en) 2008-03-12
US6548357B2 (en) 2003-04-15
DE60133214D1 (en) 2008-04-24
WO2002045134A2 (en) 2002-06-06

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