WO2002054451A3 - Method for stacking integrated circuits - Google Patents

Method for stacking integrated circuits Download PDF

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Publication number
WO2002054451A3
WO2002054451A3 PCT/FR2001/004118 FR0104118W WO02054451A3 WO 2002054451 A3 WO2002054451 A3 WO 2002054451A3 FR 0104118 W FR0104118 W FR 0104118W WO 02054451 A3 WO02054451 A3 WO 02054451A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
bond pads
bearing
integrated circuits
stacking
Prior art date
Application number
PCT/FR2001/004118
Other languages
French (fr)
Other versions
WO2002054451A2 (en
Inventor
Myriam Oudart
Francois Bernard
Marie-Jose Molino
Bruno Reig
Original Assignee
Thales Sa
Myriam Oudart
Francois Bernard
Marie-Jose Molino
Bruno Reig
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales Sa, Myriam Oudart, Francois Bernard, Marie-Jose Molino, Bruno Reig filed Critical Thales Sa
Publication of WO2002054451A2 publication Critical patent/WO2002054451A2/en
Publication of WO2002054451A3 publication Critical patent/WO2002054451A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
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    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Abstract

The invention concerns a method for stacking a component (6) (small-size integrated circuit) on a large-size integrated circuit (10). Said method is characterised in that the surface of the component (6) opposite the surface bearing its bond pads is bonded to the surface of the integrated circuit (10) bearing the bond pads. The two types of circuits have thus their surfaces bearing their bond pads accessible on the same side of the stack produced. The invention is applicable to stacking different types of components, for example MMIC on ASIC.
PCT/FR2001/004118 2000-12-28 2001-12-20 Method for stacking integrated circuits WO2002054451A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR00/17232 2000-12-28
FR0017232A FR2819100B1 (en) 2000-12-28 2000-12-28 METHOD FOR STACKING INTEGRATED CIRCUITS

Publications (2)

Publication Number Publication Date
WO2002054451A2 WO2002054451A2 (en) 2002-07-11
WO2002054451A3 true WO2002054451A3 (en) 2002-10-10

Family

ID=8858352

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2001/004118 WO2002054451A2 (en) 2000-12-28 2001-12-20 Method for stacking integrated circuits

Country Status (2)

Country Link
FR (1) FR2819100B1 (en)
WO (1) WO2002054451A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10214847A1 (en) * 2002-04-04 2003-10-23 Diehl Munitionssysteme Gmbh Flexible thin circuit construction
JP4137659B2 (en) * 2003-02-13 2008-08-20 新光電気工業株式会社 Electronic component mounting structure and manufacturing method thereof
WO2004112136A1 (en) * 2003-06-12 2004-12-23 Koninklijke Philips Electronics N.V. Electronic device
CN112956019B (en) * 2018-11-09 2023-06-02 华为技术有限公司 Chip integrated with at least two bare chips

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0149317A2 (en) * 1984-01-13 1985-07-24 Stc Plc Circuit packaging
US5422513A (en) * 1992-10-16 1995-06-06 Martin Marietta Corporation Integrated circuit chip placement in a high density interconnect structure
US5994739A (en) * 1990-07-02 1999-11-30 Kabushiki Kaisha Toshiba Integrated circuit device
US6025995A (en) * 1997-11-05 2000-02-15 Ericsson Inc. Integrated circuit module and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0149317A2 (en) * 1984-01-13 1985-07-24 Stc Plc Circuit packaging
US5994739A (en) * 1990-07-02 1999-11-30 Kabushiki Kaisha Toshiba Integrated circuit device
US5422513A (en) * 1992-10-16 1995-06-06 Martin Marietta Corporation Integrated circuit chip placement in a high density interconnect structure
US6025995A (en) * 1997-11-05 2000-02-15 Ericsson Inc. Integrated circuit module and method

Also Published As

Publication number Publication date
WO2002054451A2 (en) 2002-07-11
FR2819100A1 (en) 2002-07-05
FR2819100B1 (en) 2003-08-08

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