WO2002054659A1 - Emetteur, recepteur et procede de communication - Google Patents
Emetteur, recepteur et procede de communication Download PDFInfo
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- WO2002054659A1 WO2002054659A1 PCT/JP2001/011448 JP0111448W WO02054659A1 WO 2002054659 A1 WO2002054659 A1 WO 2002054659A1 JP 0111448 W JP0111448 W JP 0111448W WO 02054659 A1 WO02054659 A1 WO 02054659A1
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- parity
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- symbol
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
- H04L1/1829—Arrangements specially adapted for the receiver end
- H04L1/1835—Buffer management
- H04L1/1845—Combining techniques, e.g. code combining
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0066—Parallel concatenated codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0067—Rate matching
- H04L1/0068—Rate matching by puncturing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
- H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
- H04L1/1819—Hybrid protocols; Hybrid automatic repeat request [HARQ] with retransmission of additional or different redundancy
Definitions
- the present invention relates to a communication system, a transmission device, and a reception device that perform error control in data transmission by performing an automatic retransmission request.
- ARQ Automatic Repeat: Request: ARQ
- This ARQ connects the transmitting side and the receiving side via a bidirectional transmission path.
- the transmitting side first sends a bucket containing a codeword generated by performing error detection coding on information bits to the receiving side, Is detected. If no error is detected in the received data, the receiving side returns a positive acknowledgment signal (Positive Acknowledgment: ACK, sometimes referred to as AC ⁇ below) to the transmitting side to confirm that the data has been received correctly. If it is detected, it returns a retransmission request signal (Negative Acknowledgment: NACK, sometimes referred to as NACK hereinafter) to the transmitting side.
- the sender retransmits the same packet upon receiving NACK. The sender repeats retransmission of the same packet until it receives ACK.
- the transmitting side transmits the first packet, and if the receiving side correctly receives the codeword contained in the first packet, it transmits an ACK to the transmitting side. Upon receiving this ACK, the transmitting side transmits the next second packet. Next, if the receiving side erroneously receives this second bucket, Send NA CK to the receiving party. When the transmitting side receives the NACK from the receiving side, it transmits (retransmits) the second packet again. That is, the transmitting side continues to transmit the same packet as the previously transmitted packet without transmitting the next new packet unless an ACK is received from the receiving side. ARQ achieves high-quality transmission in this way.
- Hybrid ARQ is a method in which an ARQ is combined with an error correction code, and aims to improve the error rate of the received signal by using error correction, thereby reducing the number of retransmissions and improving the throughput.
- Two promising hybrid ARQ schemes, the Chase Combining scheme and the Incremental Redundanc scheme, have been proposed.
- the above-mentioned Chase Combining type hybrid AR Q (hereinafter sometimes referred to as “CC type AR Q”) is characterized in that the transmitting side retransmits the same packet as the packet transmitted last time. Upon receiving the retransmitted packet, the receiving side receives the codeword (systematic bit and parity bit) included in the packet received so far and the codeword (systematic bit and systematic bit) included in the packet retransmitted this time. Performs symbol combination with the parity bit, and performs error correction decoding on the combined signal.
- codeword systematic bit and parity bit
- the codeword included in the packet received up to the previous time and the codeword included in the packet retransmitted this time are symbol-synthesized to improve the reception level, so that retransmission is repeated.
- the error rate of the received signal improves.
- the received signal becomes error-free with a smaller number of retransmissions than the ARQ that does not perform error correction, so that the throughput can be improved.
- the Incremental Redundancy type hybrid ARQ hereinafter, “IR type”) AR Q " is characterized by retransmitting a packet containing a parity bit different from the parity bit contained in the packet transmitted up to the previous time.
- Each parity bit is held in a buffer, and when a retransmission packet is received, error correction decoding is performed using both the parity bit included in the packet received up to the previous time and the parity bit included in the packet received at the time of retransmission.
- the parity bit used for error correction decoding is incremented each time retransmission is performed, so that the error correction capability of the receiving side is improved, thereby reducing the number of retransmissions compared to ARQ without error correction. Since the received signal becomes error-free by the number of times, the throughput can be improved.
- An object of the present invention is to improve a reception level and an error correction capability, thereby reducing the number of retransmissions until no error occurs and improving the throughput, a reception device, and a reception device used for a communication method. It is to provide.
- the present inventors have found that, in IR-type ARQ, when comparing a packet received in the last retransmission unit with a packet received in the current retransmission unit, only the noise bits are different from each other, and the information bits (systematic Focused on the fact that the same bit was retransmitted as is.
- the present inventors combine the systematic bit included in the packet transmitted in the previous retransmission unit and the systematic bit included in the packet transmitted in the current retransmission unit on the receiving side, and The present inventors have found that the reception level is improved and the error rate of received data is improved, and the present invention has been made.
- the above-mentioned object is achieved in the IR-type ARQ in which the transmitting side arranges the systematic bits and the parity bits in different symbols.
- the packet is transmitted, and the receiving side symbol-combines the systematic bits contained in the packet transmitted in the previous retransmission unit with the systematic bits contained in the packet retransmitted this time. This is achieved by performing error correction decoding of systematic bits using parity bits received up to the current retransmission unit.
- FIG. 1 is a diagram showing a schematic configuration of a data transmission apparatus according to Embodiment 1 of the present invention.
- FIG. 2 is a block diagram showing an internal configuration of a transmitting apparatus according to Embodiment 1 of the present invention. Is a block diagram showing the internal configuration of the receiving apparatus according to Embodiment 1 of the present invention,
- FIG. 4 is a flowchart showing the flow of ARQ processing according to this embodiment,
- FIG. 5 is a schematic diagram showing a processing flow in receiving apparatus 200 according to Embodiment 1 of the present invention.
- FIG. 6 is a block diagram showing an internal configuration of a transmitting apparatus according to Embodiment 2 of the present invention
- FIG. 7 is a block diagram showing an internal configuration of a receiving apparatus according to Embodiment 2 of the present invention
- FIG. 9 is a schematic diagram showing a flow of ARQ processing according to Embodiment 2 of the present invention
- FIG. 9 is a schematic diagram showing a flow of processing in a receiving device according to Embodiment 2 of the present invention
- FIG. 10 is a diagram showing a schematic configuration of a data transmission apparatus according to Embodiment 3 of the present invention.
- FIG. 11 is a block diagram showing an internal configuration of a transmitting apparatus according to Embodiment 3 of the present invention.
- FIG. 12 is a block diagram illustrating a configuration of a shared receiving apparatus according to Embodiment 3 of the present invention.
- FIG. 13 is a schematic diagram illustrating a processing flow in the receiving apparatus according to Embodiment 3 of the present invention.
- FIG. 14 is a block diagram showing an internal configuration of a CC receiving apparatus according to Embodiment 3 of the present invention.
- FIG. 15 is a block diagram showing an internal configuration of an IR receiver according to Embodiment 3 of the present invention.
- FIG. 16 is a diagram showing a schematic configuration of a data transmission apparatus according to Embodiment 4 of the present invention.
- FIG. 17 is a block diagram showing an internal configuration of a transmitting apparatus according to Embodiment 4 of the present invention.
- FIG. 18 is a schematic diagram showing a processing flow in the receiving apparatus according to Embodiment 4 of the present invention.
- FIG. 1 is a diagram showing a schematic configuration of a data transmission apparatus according to Embodiment 1 of the present invention.
- the transmitting apparatus 100 is connected to the receiving apparatus 200 by a bidirectional transmission path.
- the transmitting apparatus 100 performs error detection coding and error correction coding on the information bits divided into L blocks from the first block to the L-th block to generate systematic bits and parity bits. Since this error correction coding is performed using a self-organizing code, the information bit is output as it is as a systematic bit. In this specification, information bits output as they are during encoding are referred to as systematic bits.
- the transmitting device 100 generates a packet by adding a protocol header to the systematic bit and the parity bit, and transmits the generated packet to the receiving device 200. Note that a packet is an example of a data transmission unit, and another data transmission unit includes a frame-per-spar frame.
- the receiving device 200 receives the packet transmitted from the transmitting device 100, and The systematic bit and the parity bit are separated and received from the received packet. Then, the systematic bits are subjected to error correction decoding using the parity bits as check bits, and the decoded result is subjected to error detection processing. If no error is detected in the decoding result due to error detection, receiving apparatus 200 sends a positive acknowledgment signal (Positive Acknowledgment: ACK, hereinafter referred to as ACK) to transmitting apparatus 100, and the decoding result shows no error. If it is detected, it sends a retransmission request signal (Negative Acknowledgment: NACK, hereinafter referred to as NACK) to transmitting apparatus 100.
- ACK Positive Acknowledgment
- NACK retransmission request signal
- transmitting apparatus 100 Upon receiving the NACK, transmitting apparatus 100 transmits a symbol in which the same systematic bit as the systematic bit in the previous retransmission unit is arranged, and a parity bit in the previous retransmission unit.
- a retransmission packet is generated by multiplexing a symbol in which a parity bit different from the above is arranged and a protocol header, and the generated retransmission packet is transmitted to the receiving apparatus 200.
- receiving apparatus 200 separates the symbol in which the systematic bits are arranged and the symbol in which the parity bit is arranged from the received packet, and outputs the symbol in which the separated systematic bits are arranged, Symbol combining (par combining) with the symbol in which the systematic bit received in the previous retransmission unit is arranged.
- the systematic bits after symbol combination are decoded using the parity bits received in the previous retransmission unit and the parity bits received in the current retransmission unit.
- An error is detected from this decoding result, and ACK or NACK is transmitted to transmitting apparatus 100 according to the error detection result.
- transmitting apparatus 100 When receiving the NACK, transmitting apparatus 100 generates and transmits a new retransmission packet. Transmission apparatus 1000 repeats retransmission until ACK is received, and upon receiving ACK, starts transmitting information bits of the next block.
- the transmission of the information bits of the M-th block that is, the transmission device 100 A series of processes until the ACK is received is collectively referred to as ARQ process.
- the processing unit from when a packet is transmitted from the transmitting apparatus 100 to when an ACK or a NACK is transmitted from the receiving apparatus 200 that has received the packet to the transmitting apparatus 100 is " Retransmission unit ".
- the ARQ process is performed on the information bit of a predetermined block
- the processing unit from the transmission of the packet at the k-th time until the reception of the ACK or NACK is referred to as the “k-th retransmission unit”.
- FIG. 2 is a block diagram showing an internal configuration of transmitting apparatus 100.
- an encoder 101 sequentially performs error detection coding and error correction coding on information bits divided into L blocks from a first block to an L-th block. .
- this error correction coding a systematic code is used, and a systematic bit as an information bit itself and a coded sequence (parity bit) in which the information bit is convolutionally coded are generated.
- a one-third encoder with a coding rate of 1/3 is used as the encoder 101, a one-bit systematic bit (S) is input to the input of the information bit.
- S systematic bit
- Encoder 101 according to the present embodiment is preferably a systematic code and performs encoding using a turbo code having excellent error correction capability.
- the systematic bits output from the encoder 101 are rearranged in accordance with a predetermined rule in the receiver 103, and are output to the modulation circuit 104.
- the interleaved systematic bits are arranged in a symbol on rectangular coordinates using a QPSK 16 QAM or the like in a modulation circuit 104, multiplied by a spreading code A in a spreader 105, and stored in a buffer 1. 0 is written in 6. That is, modulation circuit 104 and spreader 105 assign the systematic bit to spreading code A.
- a symbol in which a systematic bit is arranged is referred to as a "symbol-converted systematic bit". It may be called.
- a symbol in which parity bits are arranged may be referred to as a “symbol-converted parity bit”.
- the puncturing circuit 102 performs a puncturing process on the input parity bit. That is, the puncture circuit 102 performs puncture processing on the input parity bits to generate parity bits P1 to Pn, and outputs the generated parity bits P1 to Pn to the interleaver 107.
- the inbox revever 107 rearranges the order of the data of the parity bits P1 to Pn according to a predetermined rule.
- Encoder 101 encodes the input information bits and outputs two series of parity bits.
- the parity bits output in the first sequence are, in order, Pa1, Pa2, Pa3,...
- the parity pits output from the second sequence are in order, Pbl, Pb2, Pb3,. That is, the parity bits from both streams are input to the puncture circuit 102 in the order of ⁇ Pal, Pb Is Pa2, Pb2, Pa3, Pb3,... ⁇ .
- the puncturing circuit 102 performs puncturing by erasing a part of the input parity bit sequence at a predetermined cycle, and generates a parity bit sequence of P 1 to Pn. For example, by erasing the even-numbered bits, ⁇ Pal, Pa2, Pa3,... ⁇ Are generated as the parity bit string P1, and by erasing the odd-numbered bit strings, ⁇ Pbl, Pb 2 Pb 3s... ⁇ Are generated as a parity bit string P 2.
- the cycle at which bits are erased in puncturing can be changed as appropriate according to the coding rate and the communication efficiency required in the system.
- the parity bits Pl to Pn output from the receiver 107 are arranged on symbols on orthogonal coordinates using a QPSK, 16QAM, or the like in a modulation circuit 108, and are multiplied by a spreading code B in a spreader 109 to form a buffer. It is written in 110. That is, the modulation circuit 108 and the spreader 109 are the symbols converted symbols. Priority bits Pl to Pn are assigned to spreading code B. Thus, the parity bit P l ⁇ P n is assigned to a different spreading code systematic bi Uz DOO 0
- the selection circuit 111 reads a parity bit corresponding to the number of transmissions from the parity bits P1 to Pn held in the buffer 110 and outputs the parity bit to the multiplexing circuit 112. In other words, the selection circuit 111 determines the number of transmissions (the retransmission units) of the information bits of the predetermined block based on information notified from a control station (not shown). Select the parity bit according to the number of transmissions. For example, in the case of the k-th transmission of the information bits of the predetermined block (in the case of the k-th retransmission unit), the parity bit P k is read from the buffer 110 and output to the multiplexing circuit 112. This k corresponds to the number of repetitions shown in FIG. 4 described later.
- the multiplexing circuit 112 reads the symbol in which the systematic bits are arranged from the buffer 106, reads the symbol, the parity bit after the symbol conversion output from the selection circuit 111, and the header. And multiplexed to generate a transmission packet, and output the generated transmission packet to the transmission RF 113.
- the transmission RF 113 implements predetermined transmission processing such as frequency conversion and amplification on the transmission packet output from the multiplexing circuit 112 and transmits the transmission packet to the reception device 200 via the antenna 114.
- the buffer 106 and the buffer 110 When the buffer 106 and the buffer 110 acquire the ACK transmitted from the receiving device 200, the buffer 106 and the buffer 110 store the systematic bit and the parity bits Pl to Pn held when the ACK is acquired. Discard. Then, in the buffer 106 and the buffer 110, a systematic bit or a parity bit obtained by encoding the information bit of the next block among the protected information bits is written. As a result, ARQ processing for the information bits of the next block is started.
- FIG. 3 shows the internal structure of the receiver 200.
- reception RF 202 performs predetermined reception processing such as frequency conversion on a bucket received from antenna 201, and outputs the packet after the reception processing to separation circuit 250.
- Separation circuit 250 separates a symbol in which systematic bits are arranged and a symbol in which parity bits are arranged from a received packet.
- the symbol in which the separated systematic bits are arranged is output to combining circuit 204, and the symbol in which the separated parity bits are arranged is output to demodulation circuit 210.
- the separation circuit 250 includes a despreader 203 and a despreader 209.
- the despreader 203 performs despreading processing on the reception bucket output from the reception RF 202 using the spreading code A, and RAKE combines the despread signal.
- the systematic bits allocated to the scatter code A are extracted from the received packet in a symbol state.
- despreader 209 performs despreading processing on the received packet output from received RF 202 using spreading code B, and RAKE combines the despread signal.
- the parity bits assigned to the spreading code B are extracted in a symbol state from the received packet.
- demultiplexing circuit 250 performs despreading processing on received packets using different spreading codes to separate symbols in which systematic bits are arranged from symbols in which parity bits are arranged. I do.
- the systematic bit output from the despreader 203 is input to the synthesis circuit 204.
- the synthesizing circuit 204 includes an adder 205 and a buffer 206. Each time a packet is received, the adder 205 combines the symbol read from the buffer 206 with the symbol in which the systematic bit received in the current retransmission unit is arranged.
- the adder 205 is a composite symbol * The data is overwritten on the file 206 and output to the demodulation circuit 207.
- the combined symbol calculated by the adder 205 is overwritten in the buffer 206 each time retransmission is repeated. Therefore, the buffer 206 holds a symbol obtained by combining all the systematic bits received up to the current retransmission unit.
- the buffer 206 discards the held combined symbol.
- the information bit of the predetermined block (referred to as the information bit of the Mth block) is correctly received in the third reception (in the unit of the third retransmission).
- the information bit V of the (M-1) -th block is correctly received, a packet including the systematic bits and the parity bits obtained by encoding the information bits of the M-th block from the transmitting apparatus 100 is transmitted. # 1 is sent. Also, the symbols held in the buffer 206 are discarded.
- the k-th transmitted / received packet is referred to as a packet h # k.
- the receiving apparatus 200 receives the packet # 1, separates the symbol in which the systematic bit is arranged from the received packet # 1, and outputs the symbol to the adder 205. Since the symbol to be read is not held in the buffer 206, the adder 205 outputs the systematic bit as it is to the buffer 206 and a later-described demodulation circuit 207. Since the reception result of the first retransmission unit includes an error, NACK is transmitted to transmitting apparatus 100, and next packet (packet # 2) of the next (second retransmitting unit) is transmitted from transmitting apparatus 100. You.
- the receiving apparatus 200 receives this packet # 2, separates the symbol in which the systematic bit is arranged from the packet # 2, and outputs the symbol to the adder 205.
- the adder 205 reads out the symbol in which the systematic bit in the first retransmission unit is arranged from the buffer 206, and the readout symbol and the systematic bit in the second retransmission unit are arranged.
- the symbol is synthesized with the symbol, and this symbol synthesis result (synthesized symbol) is overwritten in the buffer 206. Since the reception result in the second retransmission unit also includes an error, NA CK is transmitted to transmitting apparatus 100,
- the next (third retransmission unit) bucket (packet # 3) is transmitted from transmitting device 100
- the receiving apparatus 200 receives the packet # 3, separates the symbol in which the systematic bit is arranged from the received packet # 3, and outputs the symbol to the adder 205.
- the adder 205 reads out a combined symbol of the systematic bit received in the first retransmission unit and the systematic bit received in the second retransmission unit from the buffer 206, and receives the symbol in the third retransmission unit.
- the symbol is synthesized with the symbol where the systematic bit is placed.
- the adder 205 overwrites the symbol synthesis result (synthesized symbol) on the buffer 206.
- the combined symbol obtained this time takes the value obtained by combining each of the systematic bits received in the first to third retransmission units.
- the buffer 206 at the time of reception in the k-th retransmission unit (before symbol combination), all the systematic bits received in the k-th eleventh retransmission unit from the first retransmission unit are synthesized.
- the symbol combination result (the symbol obtained by combining all the systematic bits received in the first to k-th retransmission units) is overwritten.
- ACK is transmitted to transmitting apparatus 100 and buffer 206.
- the buffer 206 discards the held symbol upon acquiring ACK. This completes the ARQ process for the information bits of the Mth block.
- a combined symbol obtained by combining the symbols in which the systematic bits received from the first retransmission unit to the k-th retransmission unit are arranged may be referred to as “combined symbol #k”.
- the combining circuit 204 arranges the combined symbol # k-11 read from the buffer 206 and the systematic bits included in the packet (packet #k) received in the k-th retransmission unit. Generates composite symbol #k by symbol combination with symbol ⁇ ⁇ .
- the combined symbol subjected to symbol combination in the combining circuit 204 is output to the demodulation circuit 207.
- the demodulation circuit 207 demaps the symbol in which the systematic bits are arranged.
- Dinning lever 208 restores the original order of the systematic bits de-mapped in demodulation circuit 207 and outputs the result to soft-decision value calculator 212.
- the despreader 209 performs despreading processing on the reception packet output from the reception RF 202 using the spreading code B, and performs RAKE combining of the despread signal, thereby receiving the signal.
- the symbol in which the parity bit Pk is arranged is extracted from the packet and output to the demodulation circuit 210.
- Demodulation circuit 210 performs a demapping process on parity bit Pk output from despreader 209. Dinning lever 211 restores the order of the parity bit Pk data output from demodulation circuit 210 to output to soft decision value calculator 212.
- the soft decision value calculator 212 calculates a soft decision value (Sk soft decision value) of the combined symbol # output from the Dinary member 208, and outputs the calculated Sk soft decision value to the decoder 214.
- the soft-decision value calculator 212 calculates a soft-decision value (Pk soft-decision value) of the parity bit Pk output from the din-leaver 211 and calculates the Pk soft-decision value into a soft-decision value buffer. Output to 213.
- the soft decision value of the combined symbol #k is referred to as “Sk soft decision value”, and the soft decision value of the parity bit Pk is referred to as “Pk soft decision value”.
- Buffer for soft decision value 213 Holds the soft decision value output from the soft decision value calculator 212 and discards the held soft decision value when ACK is acquired. In the k-th retransmission unit, the soft decision value buffer 213 holds P1 soft decision values to Pk soft decision values, respectively.
- the decoder 214 reads the P1 soft decision value to the Pk soft decision value from the soft decision value buffer 213, and outputs the read P1 soft decision value, P2 soft decision value,..., and Pk soft decision value. Error correction decoding is performed on the Sk soft decision value by using it as a check bit. That is, the decoder 214 likewise combines the P1 soft decision value, the P2 soft decision value,..., And the Pk soft decision value, and performs error correction decoding on the Sk soft decision value. If the encoder 101 uses the evening code, the error correction decoding uses the evening decoding. The decoding result is output to error detector 215.
- the decoder 214 reads the Sk soft-decision value from the soft-decision value buffer 213: inspects the P1 soft-decision value, the P2 soft-decision value, ..., and the Pk soft-decision value For error correction decoding. Therefore, as the number of times of receiving a bucket (that is, the number of times of transmitting a packet in the transmitting apparatus 100) increases, the redundancy of the parity bit used as a check bit in the decoding process increases, and the error correction capability in the decoding process improves. . Also, as the number of packet receptions increases, the level of the composite symbol #k improves, so that the distance between signals becomes smaller and the reception quality improves.
- FIG. 4 is a flowchart showing a flow of the ARQ process according to the present embodiment.
- the information bits blocked in the L blocks from the first block to the L-th block the information bits of the M-th block (1 ⁇ M ⁇ L) until the reception device 200 correctly receives the information bits (1 ⁇ M ⁇ L)
- the ARQ processing will be described.
- the encoder 101 performs error detection coding and error correction coding on the information bits of the M-th block to generate systematic bits and parity bits.
- the parity bit is subjected to a puncturing process by the puncture circuit 102, and the parity bits Pl to Pn are generated. Note that the processing at the number of repetitions k corresponds to the processing in the k-th retransmission unit.
- the modulation circuit 104 and the modulation circuit 108 arrange a systematic bit and a parity bit on a symbol on orthogonal coordinates.
- spreader 105 spreads the systematic bits using spreading code A.
- parity bits P 1 to ⁇ are spread by spreader 109 using a spreading code ⁇ ⁇ ⁇ different from spreading code ⁇ .
- the spread systematic bits are stored in buffer 106, and the spread parity bits P 1 -Pn are stored in buffer 110.
- a spreading code A different from spreading code B allocated to the symbol in which the noise bits are allocated is allocated to the symbol in which the systematic bits are allocated.
- the multiplexing circuit 112 outputs the symbol in which the systematic bits output from the buffer 106 are arranged, and the selection circuit 111 displays the symbol in which the parity bit P1 read from the buffer 110 is arranged.
- the protocol header and the code are multiplexed to generate a packet # 1, and the generated packet # 1 is transmitted to the receiving device 200.
- This packet # 1 is received by the receiving apparatus 200, and the received packet # 1 is subjected to predetermined reception processing and the like, and is input to the separation circuit 250 (the despreader 203 and the despreader 209) (ST405). .
- the received packet # 1 is subjected to despreading processing by demultiplexing circuit 250, and a symbol in which a systematic bit is arranged and a parity bit P 1 are output from a code-multiplexed signal. Are separated from the symbol where. That is, the received packet is multiplied by the spreading code A by the despreader 203 to extract a symbol in which the systematic bits are arranged, and the spreading code B different from the spreading code A is received by the despreader 209 in the received packet. Is multiplied to extract a symbol in which the parity bit P1 is arranged.
- the symbol in which the systematic bits separated from the received packet are arranged is written to buffer 206 in ST 407. Further, the symbol in which the systematic bit is arranged is output to demodulation circuit 207. Next, in ST 408, a predetermined demodulation process is performed on the systematic bit by demodulation circuit 207, and a predetermined demodulation process is performed on parity bit P1 by demodulation circuit 210.
- the soft decision value calculator 212 calculates a soft decision value of the systematic bit (S1 soft decision value) and a soft decision value of the parity bit P1 (P1 soft decision value). .
- This P1 soft decision value is held in the buffer 213 until the ARQ process for the information bit of the M-th block is completed.
- decoder 214 performs error correction decoding of S 1 soft decision value using P 1 soft decision value as a check bit.
- the error detector 215 performs error detection of the decoding result in ST407, and if there is no error, the process proceeds to ST412 to generate an AC, and if there is an error, the process proceeds to ST413 and the NACK Is generated.
- the generated ACK is transmitted to transmitting apparatus 100.
- the transmitting device 100 acquires the ACK, the ARQ process for the information bit of the Mth block ends, and the ARQ process for the information bit of the next block (the (M + 1) th block) starts.
- the generated NACK is transmitted to transmitting apparatus 100, and the process proceeds to ST414.
- ST 414 1 is added to the number of repetitions, k is set to 2, and the process proceeds to ST 404, where processing in the second retransmission unit is started.
- the multiplexing circuit 112 places a symbol in which a systematic bit is placed, the selection circuit 111 places a parity bit P2 read out from a buffer 110, and a protocol. The header and are multiplexed to generate a packet # 2, and the generated packet # 2 is transmitted to the receiving device 200.
- the packet # 2 is received by the receiving apparatus 200, and the received packet # 2 is subjected to predetermined reception processing and the like, and is subjected to a separation circuit 250 (a despreader 203 and a despreader 2). 0 9) (ST 405).
- received packet # 2 is subjected to despreading processing by demultiplexing circuit 250, and a symbol in which systematic bits are arranged and a parity bit P 2 are arranged from a code-multiplexed signal. Separated symbols.
- the systematic bit received in the previous retransmission unit (first retransmission unit) read from buffer 206 is placed in the symbol where the separated systematic bits are placed.
- the symbol is combined with the symbol.
- the combined symbol is overwritten in buffer 206 and output to demodulation circuit 207.
- the demodulation circuit 207 performs a demapping process on the symbol in which the systematic bit is arranged, and the demodulation circuit 210 performs a demapping process on the parity bit P 2.
- the soft decision value calculator 212 uses the soft decision value (S 2 soft decision value) of the combined systematic bits and the soft decision value of the parity bit P 2 (P 2 soft decision value). ) Are calculated respectively.
- This P2 soft decision value is held in the buffer 21 until the ARQ process on the information bit of the Mth block is completed.
- the decoder 2 14 performs error correction decoding of the S 2 soft decision value using the P 1 soft decision value and the P 2 soft decision value as check bits.
- error correction decoding is performed using parity bits having higher redundancy than the first retransmission unit as check bits. Specifically, the redundancy of the inspection bit is increased by the P2 soft decision value.
- Error-correction decoding generally uses redundancy of check bits. It is known that the higher the degree, the higher the error correction capability. Even when the one-time decoding is used as the decoding method according to the present embodiment, the error correction capability is improved by increasing the redundancy of the check bits, and is included in the decoded data with a small number of transmissions. Since errors can be eliminated, the throughput can be improved.
- error correction decoding is performed on the systematic bits after symbol combination. Since the signal level of the systematic bit after symbol combination is higher than that of the systematic bit without symbol combination, the distance between signals is increased, and the reception quality is improved. As a result, it is possible to eliminate errors included in decoded data with a small number of transmissions.
- the multiplexing circuit 112 divides the symbol in which the systematic bit is arranged, the symbol in which the parity bit P j read from the buffer 110 by the selection circuit 111 is arranged, and the protocol header.
- the packet #j is generated by multiplexing, and the generated packet #j is transmitted to the receiving device 200.
- the bucket #j is received by the receiving apparatus 200, and the received packet #j is subjected to predetermined reception processing and the like, and is input to the separation circuit 250 (the despreader 203 and the despreader 209) (ST405 ).
- received packet #j is subjected to despreading processing by demultiplexing circuit 250, and a symbol in which systematic bits are arranged and a symbol in which parity bits P j are arranged are separated from the code-multiplexed signal. Is done.
- a symbol obtained by combining the systematic bits received in the first retransmission unit to the (j-1) th retransmission unit in the buffer 206 is combined with each other (combined symbol # j— 1) is held.
- the symbol in which the systematic bit received in the j-th retransmission unit is arranged is symbol-synthesized with the synthesized symbol # j-11 read from the buffer 206 in ST 407. In this way, a symbol (combined symbol #j) is generated by combining the systematic bits received in the first to jth retransmission units.
- the combined symbol (synthesized symbol #j) is overwritten in the buffer 206 and output to the demodulation circuit 207.
- the demodulation circuit 207 performs demapping processing on the symbol in which the systematic bits are arranged, and the demodulation circuit 210 performs demapping processing on the symbol in which the parity bit P j is arranged. Demapping processing is performed.
- the soft decision value calculator 2 122 uses the soft decision value (S j soft decision value) of the systematic bit after symbol combination and the soft decision value (P j) of the parity bit P j. Soft decision value) is calculated. This P j soft decision value is held in the buffer 213 until the ARQ process on the information bit of the M-th block is completed.
- the decoder 2 14 uses the P 1 soft decision value, the P 2 soft decision value,..., And the P j soft decision value as check bits to determine the S j soft decision value.
- Error correction decoding is performed.
- error correction decoding is performed using a parity bit having a higher degree of redundancy than the first:! 11 retransmission unit as a check bit. Specifically, the redundancy of the check bit is increased by the P j soft decision value. Therefore, the error correction capability is improved in the case of reception in the retransmission unit of No.
- Decoder 2 for reception in j-th retransmission unit The synthesized symbol (synthesized symbol #j) input to 14 is higher in level than the synthesized symbol (synthesized symbol # j—1) input to the decoder 2 14 at the time of reception in the j-1th retransmission unit. Is large, the distance between signals increases, and the error rate improves. This makes it possible to eliminate errors included in the decoded data with a small number of transmissions, thereby improving the throughput.
- code-multiplexing is performed by performing despreading processing on a bucket in which systematic bits and parity bits arranged in different spreading codes are code-multiplexed.
- a symbol in which the systematic bit is arranged and a symbol in which the parity bit P1 is arranged are separated and extracted from the packet.
- the symbol in which the separated systematic bits are allocated can be compared with the systematic bits received up to the previous retransmission unit. Symbol combining can be performed, and the redundancy of check bits can be increased each time retransmission is repeated. As a result, the number of retransmissions until no error occurs can be reduced, so that throughput can be improved.
- FIG. 5 is a schematic diagram showing a flow of processing in receiving apparatus 200 according to Embodiment 1 of the present invention. Here, up to the third retransmission unit is shown for simplicity.
- bucket # 1 received in the first retransmission unit includes systematic bit S and parity bit P1
- packet # 2 received in the second retransmission unit is systematic bit
- the packet # 3 includes S and the parity bit P2
- the bucket # 3 received in the third retransmission unit includes the systematic bit S and the parity bit P3. Since different spreading codes are assigned to the systematic bit S and the parity bits P1 to P3, the receiving apparatus 200 converts the received packet from the received packet. It is possible to separate and extract the symbol in which the tematic bit S is arranged and the symbol in which each parity bit is arranged.
- the decoder 214 performs error correction decoding on the systematic bit S extracted from the packet # 1, using the parity bit P1 as a check bit. At this time, a dummy bit is inserted into a position corresponding to the bit that has been punctured and erased in the transmitting apparatus 100 to perform error correction decoding.
- systematic bit S is extracted from packet # 2, and the symbol is combined with the systematic bit extracted from packet # 1 to generate combined symbol # 2.
- the decoder 2 14 uses the parity bit P 2 extracted from the packet # 2 and the parity bit P 1 extracted from the packet # 1 in the first retransmission unit as check bits, and uses the parity bit P 2 as a check bit to check the symbol-combined sequence. Error correction decoding is performed on the stem bit (synthetic symbol # 2). That is, the parity bit P1 extracted in the first retransmission unit and the parity bit P2 extracted in the second retransmission unit are likelihood-combined, and the combined symbol # 2 is corrected using the likelihood-combined parity bit. Decrypt. In this way, by performing symbol combining, the signal level can be made larger than that of systematic bits without performing symbol combining, so that the reception quality in the second retransmission unit is higher than the reception quality in the first retransmission unit. Can also be improved.
- error correction decoding is performed using the parity bit P3 included in the packet # 3 in addition to the parity bit P1 and the parity bit P2 that have already been received. 4 improves the error correction capability.
- the symbol in which the systematic bits extracted from retransmission packet # 3 are arranged is combined with combined symbol # 2 to generate combined symbol # 3. Since the combined symbol # 3 has a higher signal level than the combined symbol # 2, it is possible to improve the reception quality in the third retransmission unit compared to the reception quality in the second retransmission unit.
- system By arranging the tick bits and the parity bits in different spreading codes, a packet in which the systematic bits and the parity bits are arranged in different symbols is formed.
- the receiving apparatus 200 that has received this packet can separate the symbol in which the systematic bit is arranged from the symbol in which the parity bit is arranged. Therefore, each time retransmission is repeated, the ratio of the parity bit to the check bit used for error correction decoding can be increased, and the reception quality can be improved by combining the systematic bits with symbols. As a result, the number of retransmissions until no error occurs can be reduced, so that throughput can be improved.
- the systematic state of the symbolic state (before being converted into bit information) obtained in the previous retransmission unit is converted.
- Bits are read from the buffer 206 to perform symbol synthesis. Since one symbol can hold information of a plurality (N) of bits, storing the systematic bits in the buffer 206 as symbol information before converting the bits into bit information allows the bit information to be stored.
- Buffer size can be 1 / N times larger than when storing systematic bits converted to. That is, in the present embodiment, by storing systematic bits in the buffer 206 in the state of symbols, the buffer size is made smaller than in the case where bit information is converted and stored in the buffer. You can do it.
- the arithmetic error generated during the soft decision process in soft decision value calculator 2 12 Therefore, it is possible to suppress the deterioration of the receiving performance based on.
- the soft-decision value calculator 2 12 by performing a simplified soft-decision value calculation process such as Max processing to reduce the amount of computation, the retransmission unit If the soft decision value of the systematic bits is calculated for each system bit and then combined, an operation error in the soft decision process will occur for each systematic bit. I will. Then, when combining the systematic bits including the error, the error increases and the receiving performance deteriorates.
- by calculating the soft decision value after symbol combination it is possible to reduce the occurrence of a calculation error only once and improve the reception performance.
- the data transmission apparatus has a configuration in which a transmitting apparatus 600 is provided in place of the transmitting apparatus 100 shown in FIG. 1, and a receiving apparatus 700 is provided in place of the receiving apparatus 200. Is done.
- FIG. 6 is a block diagram showing an internal configuration of transmitting apparatus 600 according to Embodiment 2 of the present invention
- FIG. 7 is an internal configuration of receiving apparatus 700 according to Embodiment 2 of the present invention.
- FIG. In the transmitting apparatus 600 shown in FIG. 6, the same parts as those of the transmitting apparatus 100 shown in FIG. 2 are denoted by the same reference numerals as in FIG. 2, and detailed description thereof will be omitted.
- the receiving device 700 shown in FIG. 7 the same parts as those in the transmitting device 100 shown in FIG. 3 are denoted by the same reference numerals as in FIG.
- This embodiment is different from the first embodiment in that systematic bits and parity bits are arranged in different symbols in a time-division manner.
- multiplexing circuit 6001 provides a systematic bit by providing a bit break in a packet, allocating a systematic bit and a parity bit to different bit breaks, and performing symbol conversion on the allocated bit sequence. And the parity bit are arranged in different symbols.
- the number of bits assigned to each bit segment is set according to the modulation scheme of modulation circuit 602.
- the modulation circuit 602 modulates the bit string including the systematic bits and the parity bits allocated in the multiplexing circuit 601 using a predetermined modulation method such as QPSK or 16QAM.
- an interleaver 103 for interleaving the systematic bit and an interleaver 107 for interleaving the parity bit are separately provided, so that the systematic bit can be separated from the systematic bit. Parity bits are prevented from being rearranged so as to be assigned to the same bit break. I Therefore, the interleaving in this embodiment is performed in a stage preceding the multiplexing circuit 61 (from the encoder 101), and is performed before the systematic bits and the parity bits are multiplexed. Preferably, the sorting is performed.
- a separating circuit 701 separates a received packet into a symbol in which systematic bits are arranged and a symbol in which parity bits are arranged in a unit of bit division. Separating circuit 701 outputs the symbol in which the systematic bits are arranged to combining circuit 204, and outputs the symbol in which the noise bit is arranged to demodulating circuit 210.
- FIG. 8 is a schematic diagram showing the flow of the ARQ process according to Embodiment 2 of the present invention.
- an encoder 101 provided in a transmitting apparatus 600, information bits are encoded to generate systematic bits and parity bits.
- the coding rate of encoder 101 is 1Z3, and information bits are transmitted in units of 10 bits.
- the 10 information bits are encoded in the encoder 101, and 10 systematic bits, a parity bit Pa, and a parity bit Pb are respectively generated.
- the parity bit Pa and the parity bit Pb are punctured in the puncture circuit 102 to generate 10-bit parity bits P1 to Pn.
- the parity bits P1 to Pn are stored in the buffer 110, and among the parity bits P1 to Pn stored in the buffer 110, a parity bit corresponding to the number of transmissions is selected by the selection circuit 111. And output to the multiplexing circuit 61.
- the case of the k-th transmission (the k-th retransmission unit) will be described as an example, and thus the parity bit P k is input to the multiplexing circuit 61.
- the multiplexing circuit 600 when composing a packet, sets a bit delimiter in units of several bits in the packet.
- the bit separation is set according to the modulation method in the modulation circuit 62 2 at the subsequent stage. That is, the multiplexing circuit 601 sets a bit break in units of the number of bits that the modulation circuit 602 places in one symbol (unit symbol). In this case, a systematic bit and a parity bit are arranged in this bit break.
- the modulation scheme used in the modulation circuit 602 is 16 PSK or 16 QAM, four bits are allocated to one symbol, so that a four-bit unit (four-bit (Break)) to set a bit break.
- the modulation method used in the modulation circuit 602 is BPSK
- a bit break is provided in units of 1 bit
- the modulation method is QPSK
- a bit break is provided in units of 2 bits.
- a bit break is set in 8-bit units.
- the multiplexing circuit 601 reads out a 10-bit systematic bit from the buffer 106. The first 8 bits of the 10 systematic bits are allocated to the first and second bit breaks, 4 bits at a time, and the remaining 2 bits are allocated to the third bit break.
- the 10-bit parity bit Pk is input to the multiplexing circuit 61.
- the 8 bits from the beginning of the 10-bit parity bit Pk are allocated to the 4th and 5th bit breaks, 4 bits at a time, and the remaining 2 bits are allocated to the 6th bit break Assigned to.
- a dummy bit is inserted into the 2-bit free area left in the sixth bit section. In this way, a bit break can be provided in a packet, and a systematic bit and a parity bit can be assigned to different bit breaks.
- the packet configured as described above is symbol-converted in modulation circuit 622 using 16QAM. That is, the 4-bit systematic bits assigned to the first bit segment are placed in the first symbol, and the 4-bit systematic bits assigned to the second bit segment are assigned to the second bit segment. The two-bit systematic bit and the two-bit dummy bit allocated to the symbol and assigned to the third bit break are the third bit. Placed on the th symbol. Also, the 4-bit parity bit assigned to the fourth bit segment is arranged in the fourth symbol, and the four systematic bits assigned to the fifth bit segment are assigned to the fifth symbol. The 2 parity bits and 2 dummy bits assigned to the 6th bit segment are assigned to the 6th symbol, and are assigned to the 6th symbol.
- each symbol is composed of only systematic bits or a combination of systematic bits and dummy bits, or only of parity bits or a combination of parity bits and dummy bits.
- the modulated packet is transmitted to receiving apparatus 700.
- the received packet is input to the separation circuit 700.
- Separating circuit 701 separates the received packet into symbols in which systematic bits are arranged and symbols in which parity bits are arranged. That is, the separation circuit 700 arranges the symbols and parity bits in which the systematic bits are arranged based on the arrangement information of the systematic bits and the parity bits transmitted from the transmitting apparatus 600 in advance. Identified symbols and separate them according to the identification result.
- the symbols in which the systematic bits are arranged are subjected to demodulation processing in the demodulation circuit 207 according to the modulation scheme of the modulation circuit 602. Further, the symbol in which the parity bit is arranged is subjected to demodulation processing in the demodulation circuit 210 according to the modulation scheme of the modulation circuit 62. As described above, the systematic bits and the parity bits are separated from each other.
- FIG. 9 shows reception apparatus 700 according to Embodiment 2 of the present invention.
- FIG. 3 is a schematic diagram showing a flow of processing in.
- the processes of symbol combining and likelihood combining in each retransmission unit are the same as those in Embodiment 1 shown in FIG. 5, and therefore detailed description is omitted.
- the processing shown in FIG. 9 differs from the processing shown in FIG. 5 in that the systematic bit and the parity bit are arranged in different symbols by time division.
- packet # 1 received in the first retransmission unit is configured to include a symbol in which systematic bits S are arranged and a symbol in which parity bits P1 are arranged
- the second retransmission unit The packet # 2 received in the packet includes a symbol in which the systematic bit S is arranged and a symbol in which the parity bit P2 is arranged
- the packet # 3 received in the third retransmission unit is the systematic bit. It is configured to include a symbol in which the bit S is arranged and a symbol in which the parity bit P3 is arranged. Since the systematic bit S and the priority bits P1 to P3 are assigned to different bit delimiters and symbol-converted, the systematic bit S is arranged from the received packet in the receiving device 700. Symbol and the symbol in which each parity bit is arranged can be separated and extracted.
- each retransmission unit in addition to the parity bits already received up to the previous retransmission unit, error correction decoding is performed using the parity bits included in the currently received bucket.
- the error correction capability of 2 14 is improved.
- the symbol in which the systematic bit S is allocated in the current retransmission unit is combined with the combination result of the symbol in which the systematic bit S has already been received in the previous retransmission unit, so that the previous retransmission is performed.
- the reception quality can be improved more than the unit.
- the transmitting apparatus 600 assigns a bit delimiter to the packet, allocates the systematic bit and the parity bit to different bit delimiters, and modulates the systematic bit. And parity bits are allocated to different symbols.
- Receiving device that received this packet The symbol 700 can separate a symbol in which a systematic bit is allocated from a symbol in which a parity bit is allocated. Therefore, each time retransmission is repeated, the ratio of the parity bit to the check bit used for error correction decoding can be increased, and the reception quality can be improved by symbolically combining the systematic bits. . As a result, the number of retransmissions until no error occurs can be reduced, so that throughput can be improved.
- Embodiment 3 of the present invention will be described with reference to FIGS.
- the present embodiment differs from Embodiment 1 in that the transmitting apparatus also communicates with a receiving apparatus for CC-type ARQ and a receiving apparatus for IR-type ARQ.
- Embodiment 4 also differs from Embodiment 1 in that the transmitting apparatus transmits the same parity bit between retransmission units for a part of the parity bit.
- FIG. 10 is a diagram showing a schematic configuration of a data transmission apparatus according to Embodiment 3 of the present invention.
- transmitting apparatus 1000 is connected to shared receiving apparatus 1200, CC receiving apparatus 1300, and IR receiving apparatus 1400 by a bidirectional transmission path.
- the transmitting apparatus 1000 transmits data to each of the shared receiving apparatus 1200, the CC receiving apparatus 1300, and the IR receiving apparatus 1400, and transmits predetermined data in accordance with AC KZN ACK.
- the CC receiver 1300 is a receiver that performs CC-type ARQ that combines symbols of a received packet, and the IR receiver 1400 receives a different parity bit each time retransmission is performed, and uses the plurality of parity bits as check bits.
- This is a receiving device that performs IR-type ARQ for performing error correction decoding
- the shared receiving device 1200 is a receiving device that performs both CC-type ARQ and IR-type ARQ.
- the transmitting device 1000 the shared receiving device 1200, the CC receiving device 1300, and the IR receiving device 1400 will be described in detail.
- FIG. 11 shows an embodiment of the present invention.
- FIG. 6 is a block diagram showing an internal configuration of a transmission device 10 ⁇ 0 according to 3.
- distribution circuit 1101 transmits a part of parity bits P1 to Pn output from modulation circuit 108 to spreader 105 as a parity bit (first parity bit) for retransmission. And the remainder to the spreader 109.
- P1 out of Pl to Pn is output to spreader 105 as a parity bit for retransmission, and the remaining P2 to Pn (second parity bits) are output to spreader 109.
- the same parity bit P1 for retransmission is transmitted between retransmission units.
- the parity bits P 2 to P n second parity bits
- different bits are transmitted between retransmission units.
- distribution circuit 1101 outputs parity bit P1 to spreader 105, and parity bits: P2 to Pn to spreader 109. The case of outputting is described.
- Spreader 105 performs a spreading process using spreading code A on the systematic bits output from modulation circuit 104 and parity bit P1 output from distribution circuit 1101.
- the spreader 109 spreads the knowledge bits P2 to Pn output from the distribution circuit 1111, using a spreading code B different from the spreading code A.
- a bit string composed of a systematic bit and a parity bit for retransmission (here, parity bit P1) is referred to as a first bit string, and a parity bit transmitted only in a predetermined retransmission unit (here, parity bit).
- P2 to Pn) are collectively referred to as a second bit string.
- the spreader 105 performs spreading processing on the first bit string using the spreading code A, and the spreader 109 uses the spreading code B for each parity bit included in the second bit string. By performing diffusion processing, the first bit string and the second bit string are assigned to different spreading codes.
- the selection circuit 1 102 reads out the parity bit corresponding to the number of transmissions from the parity bits P 2 to P n held in the Output. In other words, the selection circuit 1102 determines, based on information notified from a control station (not shown), the number of times (the number of retransmission units) the next transmission is for the information bits of the predetermined block, The parity bit according to the number of transmissions is selected. For example, in the case of the k-th transmission of the information bit of the predetermined block (in the case of the k-th retransmission unit), the parity bit P k + 1 is read from the buffer 110 and output to the multiplexing circuit 112.
- the multiplexing circuit 112 reads the symbol in which the systematic bit and the parity bit P 1 (first bit string) are arranged from the buffer 106, and outputs the read symbol and the selection circuit 110 2.
- a symbol in which the parity bit Pk + 1 (the second bit string) is arranged is multiplexed with a protocol header to generate a transmission packet, and the generated transmission packet is output to the transmission RF 113.
- the transmission RF 113 applies predetermined transmission processing such as frequency conversion and amplification to the transmission packet output from the multiplexing circuit 112 and transmits the packet via the antenna 114.
- FIG. 12 is a block diagram showing a configuration of shared receiving apparatus 1200 according to Embodiment 3 of the present invention.
- Shared receiving apparatus 1200 performs decoding processing by synthesizing the systematic bits included in the received packet between the retransmission units and by combining the parity bits with likelihood. That is, the shared receiving apparatus 1200 can be applied to both the CC-type AR Q and the IR-type AR Q.
- FIG. 12 the same parts as those in FIG. 3 are denoted by the same reference numerals as those in FIG. 3, and detailed description thereof will be omitted.
- FIG. 12 the same parts as those in FIG. 3 are denoted by the same reference numerals as those in FIG. 3, and detailed description thereof will be omitted.
- FIG. 12 the same parts as those in FIG. 3 are denoted by the same reference numerals as those in FIG. 3, and detailed description thereof will be omitted.
- reception: RF 202 performs predetermined reception processing such as frequency conversion on a packet received from antenna 201, and outputs a packet after the reception processing to demultiplexing circuit 1 201 .
- the separation circuit 1221 includes a symbol in which a systematic bit and a parity bit P1 (first bit string) are arranged from a received bucket and a parity bit: Pk + 1 (second bit string). Isolate symbol You.
- the symbol in which the separated first bit string is arranged is output to combining circuit 204, and the symbol in which the separated second bit string is arranged is output to demodulation circuit 210. More specifically, in the demultiplexing circuit 1221, a despreading process is performed on the reception packet output from the reception RF 202 using the spreading code A.
- the systematic bit and parity bit P 1 (first bit string) assigned to spreading code A are extracted from the received packet in a symbol state.
- the received packet output from the receiver 202 is subjected to despreading processing using the spreading code B, and the despread signal is RAKE-combined.
- the parity bit P k + 1 (second bit string) assigned to the spreading code B is extracted from the received packet in a symbol state.
- the demultiplexing circuit 1221 performs despreading processing on received packets using different spreading codes, so that the symbol in which the first bit sequence is arranged and the symbol in which the second bit sequence is arranged are arranged. And separate.
- FIG. 13 shows received packets in receiving apparatus (shared receiving apparatus 1200, CC receiving apparatus 130, and IR receiving apparatus 144) according to Embodiment 3 of the present invention. It is a schematic diagram which shows the flow of a process with respect to. Here, for simplicity of description, up to the third retransmission unit is shown.
- packet # 1 received in the first retransmission unit is configured to include a systematic bit and a parity bit P1 (first bit string) and a parity bit P2 (second bit string).
- Packet # 2 received in the retransmission unit is configured to include a systematic bit and a parity bit P1 (first bit string) and a parity bit P3 (second bit string), and is received in the third retransmission unit.
- Packet # 3 includes a systematic bit and a parity bit P1 (first bit string) and a parity bit P4. Since different spreading codes are assigned to the first bit string and the second bit string, the first bit string is arranged from the received packet in the shared receiver 1200. The extracted symbol and the symbol in which the second bit string is arranged can be separated and extracted.
- decoder 216 performs error correction decoding on systematic bit S using parity bit P1 and parity bit P2 as check bits.
- the first bit string (systematic bit S and parity bit P 1) is extracted from packet # 2, and symbol-combined with the first bit string extracted from packet # 1 in the previous retransmission unit.
- a synthetic symbol # 2 is generated.
- the decoder 2 14 checks the parity bit P1 after symbol combination, the parity bit P3 extracted from the packet # 2, and the parity bit P2 extracted from the packet # 1 in the first retransmission unit. And performs error correction decoding on the systematic bits after symbol combination.
- the parity bit P 1 and parity bit P 2 extracted in the first retransmission unit and the parity bit P 3 extracted in the second retransmission unit are likelihood-combined, and combined using the likelihood-combined parity bits.
- the error correction decoding is performed using the parity bit P3 included in the packet # 2 in addition to the parity bit P1 and the parity bit P2 already received, the error correction capability of the decoder 2 14 Is improved.
- the signal level can be made higher than the systematic bits without symbol combination by symbol combination, the reception quality in the second retransmission unit is improved compared to the reception quality in the first retransmission unit. Can be done.
- the third retransmission unit error correction decoding is performed using the parity bit P 4 included in the packet # 3 in addition to the parity bit P 1, the parity bit P 2, and the parity bit P 3 already received. Therefore, the error correction capability of the decoder 2 14 is improved. Also, the symbol in which the first bit string extracted from retransmission packet # 3 is arranged is combined with combined symbol # 2 to generate combined symbol # 3. Composite signal # 3 has a higher signal level than composite symbol # 2 Thus, the reception quality in the third retransmission unit can be improved over the reception quality in the second retransmission unit.
- FIG. 14 is a block diagram showing the internal configuration of the CC receiving apparatus 1300 according to Embodiment 3 of the present invention.
- the same parts as those in FIG. 3 according to Embodiment 1 are denoted by the same reference numerals as in FIG. 3, and detailed description thereof will be omitted.
- the reception RF 202 performs predetermined reception processing such as frequency conversion on a packet received from the antenna 201, and sends the packet after the reception processing to the separation circuit 1301.
- the separation circuit 1301 separates a symbol in which the systematic bit and the parity bit P1 (first bit string) are arranged and a symbol in which the parity bit Pk + 1 (second bit string) is arranged from the received packet. I do. That is, the demultiplexing circuit 1301 performs despreading processing on the reception bucket output from the reception 202 using the spreading code A, and RAKE combines the despread signal. As a result, the systematic bit and parity bit P 1 (first bit sequence) assigned to spreading code A are extracted from the received packet in the form of a symbol. The symbol in which the separated first bit string is arranged is output to the combining circuit 204.
- the decoder 2 14 performs error correction decoding on the systematic bit S extracted from the packet # 1, using the parity bit P1 and the parity bit P2 as check bits.
- the first bit sequence (systematic bit S and parity bit P 1) is extracted from packet # 2, and the first bit sequence extracted from packet # 1 in the previous retransmission unit is symbol-combined with the first bit sequence. This produces a synthetic symbol # 2.
- the decoder 2 14 uses the parity bit P1 after symbol combination as a check bit, and performs error correction decoding on the systematic bit after symbol combination.
- the symbol in which the first bit string extracted from retransmission packet # 3 is arranged is symbol-synthesized with synthesized symbol # 2 to generate synthesized symbol # 3. Since the combined symbol # 3 has a higher signal level than the combined symbol # 2, the reception quality in the third retransmission unit can be improved than the reception quality in the second retransmission unit.
- the CC receiving apparatus receives a symbol in which a first bit sequence already included in the received packet and a symbol in which the first bit sequence is already allocated. Combine. Therefore, high reception quality can be realized.
- the device since there is no configuration for extracting and combining different parity bits (second bit sequence) every time retransmission is performed, there is no need to provide a buffer used for likelihood combining of parity bits, and the device can be downsized. And has an advantageous effect that power consumption can be reduced.
- FIG. 15 is a block diagram showing an internal configuration of an IR receiving device 1400 according to Embodiment 3 of the present invention.
- the IR receiving apparatus 1400 performs symbol synthesis between the shared receiving apparatus 1200 shown in FIG. 12 and the retransmission unit of the symbol in which the first bit string is arranged. It differs in that it is not performed.
- the same parts as those in FIG. 12 are denoted by the same reference numerals, and detailed description thereof will be omitted.
- the reception RF 202 performs predetermined reception processing such as frequency conversion on a packet received from the antenna 201, and outputs a bucket after the reception processing to the separation circuit 1201.
- the separation circuit 1221 extracts a symbol in which a systematic bit and a parity bit P1 (first bit string) are arranged and a symbol in which a parity bit Pk + 1 (second bit string) is arranged from the received packet.
- the despreader (not shown) provided in the separation circuit 1201 performs despreading processing on the received packet output from the received RF 202 using the spreading code A and the spreading code B, and RAKE combining the signals of As a result, the systematic bit and packet assigned to spreading code A from the received packet are obtained.
- the parity bit P 1 (first bit string) and the parity bit P k + 1 (second bit string) assigned to the spreading code B are extracted in a symbol state.
- the symbol in which the separated first bit sequence is arranged is output to demodulation circuit 207.
- the decoder 2 14 performs error correction decoding on the systematic bit S extracted from the packet # 1 using the parity bit P1 and the parity bit P2 as check bits.
- the decoder 2 14 uses the parity bit P1 and the parity bit P2 extracted from the packet # 1 in the first retransmission unit and the parity bit P3 extracted from the packet # 2 as check bits. Then, the systematic bit S is subjected to error correction decoding. That is, the parity bit P1 and the parity bit P2 extracted in the first retransmission unit and the parity bit P3 extracted in the second retransmission unit are likelihood-combined, and the system is used using the likelihood-combined parity bit. Error-correcting decoding of the magic bit S.
- error correction decoding is performed by using the parity bit P4 included in the packet # 3 in addition to the parity bit P1, the parity bit P2, and the parity bit P3 that have already been received. Therefore, the error correction capability of the decoder 2 14 is improved.
- the IR receiving apparatus performs error correction decoding by performing likelihood synthesis of the newly received parity bit with the previously received parity bit each time retransmission is performed, so that the error correction capability is improved each time retransmission is performed. improves.
- the symbol combining of the symbols in which the systematic bits are arranged is not performed, it is possible to reduce the size of the device and reduce the power consumption as compared with the shared receiving device 120.
- a packet is configured such that a part of parity bits is the same between retransmission units.
- ARQ processing is performed by using the same parity bit (in this embodiment, parity bit P 1) between the systematic bit and the retransmission unit. It is possible to do.
- shared receiving apparatus 1200 performs error correction decoding using the likelihood-combined parity bits of the systematic bits after symbol combining as parity check bits, as in receiving apparatus 200 shown in Embodiment 1. Can be done. Furthermore, the IR receiving apparatus 1400 can perform error correction decoding by performing likelihood combining of different parity bits between retransmission units.
- Transmitting apparatus 100 ⁇ configures a packet so that a part of the parity bit is the same between retransmission units, so that shared receiving apparatus 12 0, CC receiving device 1300, and IR receiving device 1400 can communicate with each other.
- the receiving devices (the shared receiving device 1200, the CC receiving device 130, and the IR receiving device 1400) that communicate with the transmitting device 1000 are different from each other as described above. Has unique features. Therefore, it is considered that the user will use the receiving device according to each purpose.
- transmitting apparatus 1000 according to the present embodiment communicates with any of shared receiving apparatus 1200, CC receiving apparatus 1300, and IR receiving apparatus 1400. Since there is no need to separately install a transmitting device corresponding to each receiving device, it is possible to achieve a significant cost reduction.
- the overnight transmission device adopts a configuration in which a transmission device 170 is provided in place of transmission device 1000 shown in FIG.
- FIG. 17 shows the internal configuration of the transmitting device 170.
- Transmitting apparatus 170 differs from the third embodiment in that first bit string and second bit string are assigned to different bit divisions.
- the same parts as those in FIG. 10 are denoted by the same reference numerals as those in FIG.
- the same portions as those of transmitting apparatus 100 shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.
- the puncturing circuit 1701 is used for puncturing processing.
- the parity bit P1 of the generated parity bits P1 to Pn is output to the interleaver 103 as a parity bit for retransmission, and the remaining parity bits P2 to Pn are output to the interleaver 107.
- the multiplexing circuit 1702 sets a bit delimiter in the packet, and uses a first bit string composed of a systematic bit and a parity bit P1 for retransmission, and a parity bit output from the selection circuit 111.
- the configured second bit sequence is assigned to different bit divisions, and the bit sequence after the assignment is symbol-converted, so that the first bit sequence and the second bit sequence are arranged in different symbols.
- the transmitting device 17 ⁇ 0 transmits the packet thus configured to the shared receiving device 1200, CC receiving device 1300, and IR receiving device 1400.
- the shared receiving apparatus 12000 outputs a symbol in which the systematic bit and the parity bit P 1 (first bit string) are arranged from the received packet and the parity bit P k + 1 (second (Sequence of bits) is separated.
- the symbol in which the separated first bit string is arranged is output to combining circuit 204, and the symbol in which the separated second bit string is arranged is output to demodulation circuit 210.
- FIG. 18 is a schematic diagram showing the flow of processing of a received packet. Here, for simplicity of explanation, up to the third retransmission unit is shown.
- the decoder 216 performs error correction decoding on the systematic bit St using the parity bit P1 and the parity bit P2 as check bits.
- the decoder 2 14 checks the parity bit P1 and the parity bit P2 extracted from the packet # 1 together with the parity bit P3 extracted from the packet # 2 in the second retransmission unit. And performs error correction decoding on the systematic bits after symbol combination.
- the parity bits included in packet # 3 in addition to the parity bit P1, parity bit P2, and parity bit P3 already received. Since the error correction decoding is also performed using the bit P4, the error correction capability of the decoder 214 is improved.
- the separating circuit 1301 converts the systematic bit and parity bit P from the received packet.
- the symbol in which 1 (the first bit string) is arranged is separated from the symbol in which the notice bit P k + 1 (the second bit string) is arranged.
- CC receiving apparatus 1303 separates the first bit string from the second bit string, so that each time a packet is received, the first bit string included in the received packet is arranged.
- the symbol is symbol-synthesized with the symbol in which the first bit sequence already receiving the received symbol is arranged.
- reception RF 202 performs predetermined reception processing such as frequency conversion on a packet received from antenna 201, and outputs the packet after the reception processing to demultiplexing circuit 121.
- the separation circuit 1221 includes a symbol in which a systematic bit and a parity bit P 1 (first bit string) are located from a received packet, and a parity bit P k + 1 (second bit string). Separate symbols.
- the IR receiving apparatus 1400 separates the first bit sequence from the second bit sequence, thereby re-transmitting the newly received parity bit each time retransmission is performed.
- the packet is configured such that a part of the parity bit is the same between retransmission units.
- the ARQ process can be performed using the same parity bit (parity bit P 1 in the present embodiment) between the systematic bit and the retransmission unit.
- transmitting apparatus 1700 can communicate with any of shared receiving apparatus 1200, CC receiving apparatus 1300, and receiving apparatus 1400, There is no need to separately install a transmitter corresponding to each receiver, Wide cost reduction can be achieved.
- the data transmission apparatus of each of the above embodiments is applied to a digital wireless cellular system.
- a mobile station that moves freely in a cell is equipped with a receiving apparatus 200, a shared receiving apparatus 1200, a CC receiving apparatus 1300, or a receiving apparatus 1400.
- the transmitting device 100, the transmitting device 1000, or the transmitting device 170 0 is mounted on the base station.
- the transmitting device 100 (the transmitting device 1000 or the transmitting device 170) and the corresponding receiving device 200 (the shared receiving device 120, the receiving device for the CC 130, or By performing ARQ processing with the receiving apparatus 1400), the transmission quality and throughput of wireless communication are improved.
- a systematic bit and a parity bit are arranged in different symbols in a transmitting apparatus, so that a systematic bit and a parity bit are separated in a receiving apparatus.
- the transmission device can achieve CC-type AR It can communicate with any of the receiving device that performs Q, the receiving device that performs IR-type ARQ, and the receiving device that performs both CC-type ARQ and IR-type ARQ. As a result, it is not necessary to separately install a transmitting device corresponding to each receiving device, and a significant cost reduction can be achieved.
- the present invention is suitable for use in a communication system, a transmitting device, and a receiving device that perform error control in data transmission by performing an automatic retransmission request.
- the present specification is based on Japanese Patent Application No. 2000-398398 filed on December 27, 2000. This content is included here.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Communication Control (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020027011144A KR20020079913A (ko) | 2000-12-27 | 2001-12-26 | 송신 장치와 그 방법, 수신 장치와 그 방법, 통신 방법 및통신 시스템 |
EP01272868A EP1347593A4 (en) | 2000-12-27 | 2001-12-26 | TRANSMITTER, RECEIVER AND COMMUNICATION PROCESS |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000398398A JP3464649B2 (ja) | 2000-12-27 | 2000-12-27 | 送信装置、受信装置および通信方法 |
JP2000-398398 | 2000-12-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002054659A1 true WO2002054659A1 (fr) | 2002-07-11 |
Family
ID=18863376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2001/011448 WO2002054659A1 (fr) | 2000-12-27 | 2001-12-26 | Emetteur, recepteur et procede de communication |
Country Status (6)
Country | Link |
---|---|
US (1) | US20030014709A1 (ja) |
EP (1) | EP1347593A4 (ja) |
JP (1) | JP3464649B2 (ja) |
KR (1) | KR20020079913A (ja) |
CN (1) | CN1406420A (ja) |
WO (1) | WO2002054659A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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GB2380374A (en) * | 2001-07-25 | 2003-04-02 | Samsung Electronics Co Ltd | Hybrid automatic repeat request transmission (HARQ) with adaptive modulation (AMCS) |
FR2831369A1 (fr) * | 2001-10-19 | 2003-04-25 | Samsung Electronics Co Ltd | Procedes et appareils de re-emission de bits codes et de reception de bits codes re-emis |
GB2382284A (en) * | 2001-10-31 | 2003-05-21 | Samsung Electronics Co Ltd | Retransmission system in which bits are inverted and/or the mapping of bits to symbols is rearranged, depending on the number of previous retransmissions |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100464360B1 (ko) * | 2001-03-30 | 2005-01-03 | 삼성전자주식회사 | 고속 패킷 데이터 전송 이동통신시스템에서 패킷 데이터채널에 대한 효율적인 에너지 분배 장치 및 방법 |
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US7302278B2 (en) * | 2003-07-03 | 2007-11-27 | Rotani, Inc. | Method and apparatus for high throughput multiple radio sectorized wireless cell |
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CA2869452C (en) | 2004-10-12 | 2016-01-19 | Tq Delta, Llc | Resource sharing in a telecommunications environment |
EP1657845A3 (en) * | 2004-11-10 | 2012-03-07 | Alcatel Lucent | Dynamic retransmission mode selector |
US7835264B2 (en) * | 2004-12-29 | 2010-11-16 | Mitsubishi Denki Kabushiki Kaisha | Interleaver, deinterleaver, communication device, and method for interleaving and deinterleaving |
JP4631053B2 (ja) * | 2005-07-04 | 2011-02-16 | 国立大学法人東北大学 | 再送装置及び再送方法 |
JP4912311B2 (ja) | 2005-08-05 | 2012-04-11 | パナソニック株式会社 | 無線通信装置および無線通信方法 |
JP4704469B2 (ja) * | 2005-09-28 | 2011-06-15 | エルジー エレクトロニクス インコーポレイティド | ブロードキャストマルチキャストサービスのためのセルラネットワークのデータ協力中継方法 |
JP4606995B2 (ja) | 2005-10-28 | 2011-01-05 | Kddi株式会社 | デジタル信号伝送方法ならびに送信装置 |
JP3917633B1 (ja) * | 2005-11-21 | 2007-05-23 | シャープ株式会社 | デジタル復調装置、その制御方法、デジタル復調装置用プログラム、デジタル復調装置用プログラムを記録した記録媒体及びデジタル受信装置 |
JP4245602B2 (ja) * | 2005-11-25 | 2009-03-25 | シャープ株式会社 | デジタル復調装置、デジタル受信装置、デジタル復調装置の制御方法、デジタル復調装置の制御プログラム、及び、この制御プログラムを記録した記録媒体 |
EP3301871B8 (en) | 2006-04-12 | 2021-07-07 | TQ Delta, LLC | Method, apparatus and system for packet retransmission |
JP4768030B2 (ja) * | 2006-10-04 | 2011-09-07 | 富士通株式会社 | データ転送方法 |
US8223628B2 (en) * | 2007-01-10 | 2012-07-17 | Lantiq Deutschland Gmbh | Data transmission method, transmitter, receiver, transceiver and transmission system |
KR101246807B1 (ko) * | 2007-02-15 | 2013-03-26 | 삼성전자주식회사 | 통신시스템에서 하이브리드 자동재전송요청 수행 장치 및방법 |
DE102007014997B4 (de) * | 2007-03-28 | 2013-08-29 | Continental Automotive Gmbh | Redundante Signalübertragung |
US9686045B2 (en) | 2007-04-04 | 2017-06-20 | Lantiq Beteiligungs-GmbH & Co. KG | Data transmission and retransmission |
KR101304833B1 (ko) * | 2007-04-13 | 2013-09-05 | 삼성전자주식회사 | 이동 통신 시스템에서 기준 심볼 전력 할당에 따른 변조심볼을 매핑/디매핑하는 방법 및 송/수신기 |
WO2009016705A1 (ja) * | 2007-07-27 | 2009-02-05 | Fujitsu Limited | 通信装置 |
US8301964B2 (en) * | 2007-11-19 | 2012-10-30 | Research In Motion Limited | Incremental redundancy with resegmentation |
EP2061176B1 (en) * | 2007-11-19 | 2013-07-17 | Research In Motion Limited | Incremental redundancy with resegmentation |
JP5194896B2 (ja) * | 2008-03-07 | 2013-05-08 | 沖電気工業株式会社 | 符号化装置、復号装置及び符号化システム |
US8634333B2 (en) * | 2008-05-07 | 2014-01-21 | Qualcomm Incorporated | Bundling of ACK information in a wireless communication system |
JP2010050716A (ja) * | 2008-08-21 | 2010-03-04 | Sharp Corp | 通信装置、通信システム及び通信方法 |
US8375278B2 (en) * | 2009-07-21 | 2013-02-12 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured block codes |
US8516351B2 (en) * | 2009-07-21 | 2013-08-20 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured block codes |
US9397699B2 (en) * | 2009-07-21 | 2016-07-19 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured codes |
US8516352B2 (en) * | 2009-07-21 | 2013-08-20 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured block codes |
US8271858B2 (en) * | 2009-09-03 | 2012-09-18 | Telefonaktiebolget L M Ericsson (Publ) | Efficient soft value generation for coded bits in a turbo decoder |
JP2011193434A (ja) | 2009-10-28 | 2011-09-29 | Panasonic Corp | パリティパケットを用いた通信方法、通信装置及び中継器 |
JP5154621B2 (ja) * | 2010-09-06 | 2013-02-27 | Kddi株式会社 | デジタル信号伝送方法および受信装置 |
US9954643B2 (en) * | 2012-06-22 | 2018-04-24 | Samsung Electronics Co., Ltd. | Communication system with repeat-response combining mechanism and method of operation thereof |
US9130749B1 (en) * | 2012-09-12 | 2015-09-08 | Marvell Internatonal Ltd. | Method and apparatus for decoding a data packet using scalable soft-bit retransmission combining |
CN105227274B (zh) * | 2014-06-26 | 2019-04-30 | 深圳市中兴微电子技术有限公司 | 重传合并方法及装置 |
JP6175472B2 (ja) * | 2015-10-30 | 2017-08-02 | パナソニック株式会社 | 基地局、通信システムおよび干渉回避方法 |
JP7318033B2 (ja) * | 2017-08-23 | 2023-07-31 | 株式会社東芝 | 無線通信装置および無線通信方法 |
WO2019095362A1 (en) * | 2017-11-20 | 2019-05-23 | Qualcomm Incorporated | Techniques and apparatuses for hybrid automatic repeat request design of polar codes for ultra-reliable low latency communications |
DE102020216072A1 (de) * | 2020-12-16 | 2022-06-23 | Infineon Technologies Ag | Vorrichtung und Verfahren zum Bearbeiten von Bitfolgen |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000004196A (ja) * | 1998-03-10 | 2000-01-07 | Conexant Syst Inc | タ―ボ復号化を用いる無線多元サ―ビス通信環境下における再送信パケットキャプチャシステム |
JP2001197044A (ja) * | 2000-01-14 | 2001-07-19 | Ntt Docomo Inc | 伝送誤り制御方法 |
JP2002051030A (ja) * | 2000-07-11 | 2002-02-15 | Lg Electronics Inc | 通信システム及び該システムの信号伝送方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0691140B2 (ja) * | 1986-07-11 | 1994-11-14 | 日本電気株式会社 | 半導体集積回路 |
JP3212238B2 (ja) * | 1995-08-10 | 2001-09-25 | 株式会社日立製作所 | 移動通信システムおよび移動端末装置 |
DE69736347T2 (de) * | 1997-05-09 | 2007-07-12 | Stmicroelectronics S.R.L., Agrate Brianza | Digitale Photographievorrichtung mit einer Bildverarbeitungsvorrichtung |
EP2239876A3 (en) * | 1997-06-19 | 2011-01-26 | Kabushiki Kaisha Toshiba | Information data multiplexing transmission system, multiplexer and demultiplexer used therefor, and error correcting encoder and decoder |
US6778558B2 (en) * | 1998-02-23 | 2004-08-17 | Lucent Technologies Inc. | System and method for incremental redundancy transmission in a communication system |
US5978365A (en) * | 1998-07-07 | 1999-11-02 | Orbital Sciences Corporation | Communications system handoff operation combining turbo coding and soft handoff techniques |
US7406261B2 (en) * | 1999-11-02 | 2008-07-29 | Lot 41 Acquisition Foundation, Llc | Unified multi-carrier framework for multiple-access technologies |
US6308294B1 (en) * | 1999-11-17 | 2001-10-23 | Motorola, Inc. | Adaptive hybrid ARQ using turbo code structure |
AU779378C (en) * | 2000-01-20 | 2005-02-24 | Apple Inc. | Hybrid ARQ schemes with soft combining in variable rate packet data transmission |
-
2000
- 2000-12-27 JP JP2000398398A patent/JP3464649B2/ja not_active Expired - Fee Related
-
2001
- 2001-12-26 US US10/182,531 patent/US20030014709A1/en not_active Abandoned
- 2001-12-26 WO PCT/JP2001/011448 patent/WO2002054659A1/ja not_active Application Discontinuation
- 2001-12-26 EP EP01272868A patent/EP1347593A4/en not_active Withdrawn
- 2001-12-26 CN CN01805683A patent/CN1406420A/zh active Pending
- 2001-12-26 KR KR1020027011144A patent/KR20020079913A/ko not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000004196A (ja) * | 1998-03-10 | 2000-01-07 | Conexant Syst Inc | タ―ボ復号化を用いる無線多元サ―ビス通信環境下における再送信パケットキャプチャシステム |
JP2001197044A (ja) * | 2000-01-14 | 2001-07-19 | Ntt Docomo Inc | 伝送誤り制御方法 |
JP2002051030A (ja) * | 2000-07-11 | 2002-02-15 | Lg Electronics Inc | 通信システム及び該システムの信号伝送方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1347593A4 * |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2380374A (en) * | 2001-07-25 | 2003-04-02 | Samsung Electronics Co Ltd | Hybrid automatic repeat request transmission (HARQ) with adaptive modulation (AMCS) |
GB2380374B (en) * | 2001-07-25 | 2003-09-17 | Samsung Electronics Co Ltd | Apparatus and method for retransmitting high-speed data in a CDMA mobile communication system |
AU2002300260B2 (en) * | 2001-07-25 | 2004-09-23 | Samsung Electronics Co., Ltd. | Apparatus and method for retransmitting high-speed data in a CDMA mobile communication system |
FR2831369A1 (fr) * | 2001-10-19 | 2003-04-25 | Samsung Electronics Co Ltd | Procedes et appareils de re-emission de bits codes et de reception de bits codes re-emis |
GB2381719A (en) * | 2001-10-19 | 2003-05-07 | Samsung Electronics Co Ltd | Retransmitting high priority bits and low priority bits when the number of spreading codes available for transmission may vary |
GB2381719B (en) * | 2001-10-19 | 2003-12-10 | Samsung Electronics Co Ltd | Transceiver apparatus and method for efficient high-speed data retransmission and decoding in a CDMA mobile comunication system |
AU2002301552B2 (en) * | 2001-10-19 | 2004-04-29 | Samsung Electronics Co., Ltd. | Transceiver apparatus and method for efficient high-speed data retransmission and decoding in a CDMA mobile communication system |
US7027782B2 (en) | 2001-10-19 | 2006-04-11 | Samsung Electronics Co., Ltd. | Transceiver apparatus and method for efficient high-speed data retransmission and decoding in a CDMA mobile communication system |
GB2382284A (en) * | 2001-10-31 | 2003-05-21 | Samsung Electronics Co Ltd | Retransmission system in which bits are inverted and/or the mapping of bits to symbols is rearranged, depending on the number of previous retransmissions |
GB2382284B (en) * | 2001-10-31 | 2006-02-15 | Samsung Electronics Co Ltd | Transmitting/receiving apparatus and method for packet retransmission in a mobile communication system |
Also Published As
Publication number | Publication date |
---|---|
KR20020079913A (ko) | 2002-10-19 |
EP1347593A1 (en) | 2003-09-24 |
JP3464649B2 (ja) | 2003-11-10 |
EP1347593A4 (en) | 2006-01-25 |
CN1406420A (zh) | 2003-03-26 |
JP2002198938A (ja) | 2002-07-12 |
US20030014709A1 (en) | 2003-01-16 |
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