WO2002062029A2

WO2002062029A2 - Compensation method for a transceiver using two-point modulation

Info

Publication number: WO2002062029A2
Application number: PCT/DE2001/004956
Authority: WO
Inventors: Markus Hammes; Stefan Van Waasen
Original assignee: Infineon Technologies Ag
Priority date: 2001-02-02
Filing date: 2001-12-28
Publication date: 2002-08-08
Also published as: WO2002062029A3; DE50103813D1; EP1356651A2; JP2004518382A; ATE277471T1; DE10104775A1; EP1356651B1; US20040048590A1; CN100471188C; US6774738B2; CN1488219A

Abstract

The invention relates to a method for amplitude compensation in transceivers having a PLL circuit which works according to the principle of two-point modulation. The amplitude of an analog modulation signal is selected according to a modulation increase of a determined digital modulation signal, a pre-determined data sequence of the analog modulation signal is inputted, the modulation increase of the analog modulation signal is determined, and the amplitude of the analog modulation signal is corrected so that it corresponds to the difference between the modulation increase of the digital modulation signal and the determined modulation increase of the analog modulation signal.

Description

description

Matching procedure for a transceiver with two-point modulation

The invention relates to a matching method for PLL circuits operating according to the principle of two-point modulation, and relates in particular to a method for amplitude matching in transceivers for mobile radio systems with a PLL circuit operating according to the principle of two-point modulation. in the transmitter and a receiver working according to the limiter discriminator principle.

A low-cost implementation of a transmitter concept for transceivers in mobile radio systems is provided by transmitters with a modulator operating according to the principle of two-point modulation, which is known per se and in which it is possible to provide a PLL (phase-locked loop) circuit with signals modulate that have a bandwidth larger than the PLL bandwidth, and thereby achieve a frequency-independent transmission behavior of the PLL circuit.

3 shows in simplified form a known PLL circuit working on the principle of two-point modulation for such a transmitter with a phase frequency detector 1, a charge pump 2, a loop filter 3 and a voltage-controlled oscillator (VCO) 5 in the forward branch and a frequency divider 6 with a divisor value N in the feedback branch of the modulator.

To generate the two-point modulation, a summation point 4, which represents a high-pass point and is located in front of the voltage-controlled oscillator 5 in the forward branch (analog modulation, which is fed in at this point, acts on the pass control with a high-pass filtering through the closed control loop Output), an analog modulation and a digital modulation at the frequency divider 6 representing a low-pass point in the feedback branch introduced into the PLL circuit which has settled to the channel center frequency before the actual transmission process. The two modulation signals then overlap at the output of the PLL circuit in such a way that the desired frequency-independent behavior results.

With this type of transmitter concept, the PLL control loop remains closed. Due to requirements regarding the noise behavior, the bandwidth of the PLL control loop is also designed to be smaller than would be necessary for the transmission of modulated data. Therefore, in addition to the pure digital modulation, the analog modulation is used to compensate for the restricted bandwidth, in addition to a simultaneous phase of the analog and digital modulation, the correspondence of the amplitudes of these two modulation signals is of great importance.

Due to manufacturing tolerances in the components used for analog modulation with regard to, for example, the modulation steepness, the generation of the modulation voltage and the like, it is necessary to carry out an amplitude comparison between the analog and digital modulation after manufacture. If, in addition, influences caused by temperature changes are also to be taken into account, this amplitude comparison must take place before each transmission process.

A known adjustment method consists in introducing the two modulations, feeding the output signal of the PLL circuit to an external measurement receiver, demodulating there and carrying out a corresponding amplitude adjustment. Due to the non-linear behavior of the voltage-controlled oscillator 5 with respect to the frequency as a function of the voltage, however, such an amplitude adjustment must be carried out for each of a plurality of channels, which leads to a long measurement period and, moreover, requires the adjustment information to be stored in a memory. Further influences resulting from temperature changes cannot be taken into account.

Another known matching method involves the reception and de-modulation by the receiver section of the transmitter / receiver. For this, however, a complete second PLL circuit is required in the receiver, which, in addition to a considerably higher circuit complexity and therefore higher costs, makes it necessary to set this to a frequency when using a heterodyn receiver, which is the difference between the transmission frequency and the intermediate frequency corresponds.

The known adjustment methods are disadvantageous in that, on the one hand, a long measurement period and, on the other hand, a high expenditure on equipment or circuitry are associated with correspondingly high costs.

The invention is therefore based on the object of providing a matching method for a transmitter / receiver with two-point modulation, which enables quick amplitude matching with little effort and allows temperature influences to be taken into account.

This object is achieved by a method according to claim 1.

Advantageous developments of the method are the subject of the attached subclaims.

According to the invention, a matching method for a transmitter / receiver with a PLL circuit operating on the principle of two-point modulation is characterized by the following steps: selecting the amplitude of an analog modulation signal corresponding to the modulation stroke of a fixed digital modulation signal; Einprä- against a predetermined data sequence of the analog modulation signal; Determining the modulation stroke of the analog modulation signal at an output of the receiver; and correcting the amplitude of the analog modulation signal in accordance with the difference between the modulation stroke of the digital modulation signal and the determined modulation stroke of the analog modulation signal.

Before carrying out the adjustment process, the PLL circuit is set to a channel center frequency before a transmission process in order to provide a steady state.

The digital modulation signal is preferably deactivated during the adjustment process in order to suppress a regulation of the analog modulation when selecting an initial amplitude of the analog modulation signal.

More preferably, the predetermined data sequence of the analog modulation signal is impressed at a predetermined high-pass point in the forward branch of the PLL circuit, and the digital modulation signal is impressed at a predetermined low-pass point in the feedback branch of the PLL circuit, which is advantageous for the behavior of the arrangement Overall transfer function of the PLL circuit results.

In a particularly suitable manner, the digital modulation signal is impressed directly into a first frequency divider.

If the output signal of the PLL circuit is passed into a second frequency divider located in a signal path branching off from the feedback branch, divided in the second frequency divider and then fed to the receiver as one of input signals, a second PLL circuit in the receiver can advantageously be omitted. The divider value of the second frequency divider is preferably selected such that the output frequency of the second frequency divider corresponds to the intermediate frequency of the receiver.

Alternatively, an integer value can be selected as the divider value of the second frequency divider such that the output frequency of the second frequency divider is essentially in the vicinity of the intermediate frequency of the receiver, which results in an additional degree of freedom for the selection of the divider value, taking into account the actual frequency range of the receiver of the second frequency divider results.

The invention is described below with reference to a preferred embodiment with reference to the accompanying drawings. Show it:

1 shows a PLL circuit arrangement working according to the principle of two-point modulation, in which a matching method for a transmitter / receiver using the two-point modulation according to a preferred exemplary embodiment can be used;

2 shows a simplified flow chart of the adjustment method according to the preferred exemplary embodiment; and

FIG. 3 simplifies a known PLL circuit which works on the principle of two-point modulation.

1 shows a PLL circuit arrangement operating according to the principle of two-point modulation, in which a matching method for a transmitter / receiver (transceiver) using the two-point modulation according to a preferred exemplary embodiment can be used. As in the known PLL circuit according to FIG. 2, in the PLL circuit according to FIG. 1 there is a phase frequency detector 1, a charge pump 2, a loop filter 3, a summation point 4 and a voltage-controlled oscillator 5 in the waiting branch and a first frequency divider 6 is provided with a first divider value Ni in the feedback branch of the PLL circuit, and the PLL circuit is also already in a steady state on the channel center frequency before a transmission process.

In addition, a second frequency divider 7 with a second divider value N _{2 is} provided in a signal path branching off from the feedback branch of the PLL circuit after the first frequency divider 6, to which an FM demodulator 8 as part of a known, according to the limiter discriminator Principle working (not shown) heterodyne receiver is connected downstream.

The mode of operation of the circuit arrangement shown in FIG. 1 is described in more detail below.

A reference frequency f _{R is first} fed to the PLL circuit at a first input of the phase frequency detector 1. The reference frequency f _R is compared in the phase frequency detector 1 with the frequency in the feedback path behind the first frequency divider 6 and a control signal is generated which is processed in the charge pump 2, the loop filter 3 and the voltage-controlled oscillator 5 in a known manner , At the output of the voltage controlled oscillator thus an output signal of the frequency fvoo "appears f The output signal _VC o of the voltage controlled oscillator 5 which lies in the feedback path of the PLL circuit first frequency divider 6 is fed to i with the divider value, the output accordingly, a signal of frequency fvco / i delivers. To generate the two-point modulation, analog modulation is introduced at the summation point 4 located in front of the voltage-controlled oscillator 5 in the forward branch of the PLL circuit, and digital modulation is introduced into the PLL circuit at the first frequency divider 6 in the feedback branch of the PLL circuit.

The digitally modulated output signal f _Vco / Nι of the first frequency divider 6 is then a second input of the phase frequency detector 1 and a second frequency divider 7 with the divider value N in a signal path branching from the feedback branch of the PLL circuit after the first frequency divider 6 ₂ fed.

The second frequency divider 7 divides the output signal f _vco / Ni of the first frequency divider 6 according to its _{divider value} N ₂ , so that the output of the second frequency divider 7 _delivers a further divided output signal of the frequency f _VCo / (N ₂ * N _X ).

The output signal f _VC o / (N ₂ * Nι) of the second frequency divider 7 is then fed to the downstream FM demodulator 8 and demodulated by the latter.

Preferably, the divider value N _{2 of} the second frequency divider 7 is chosen so that the output frequency f _vco / (N ₂ * Nι) corresponds to the intermediate frequency of the heterodyne receiver, whereby a second complete PL control loop in the receiver for mixing down the output signal f _vco voltage-controlled oscillator 5 can advantageously be omitted.

Since the receiver is generally suitable for a larger frequency range due to possible frequency offsets, the divider value N _{2 of} the second frequency divider 7 can alternatively also be selected such that its output frequency fvco / (N ₂ * Nι), corresponding to a frequency offset, essentially in the Is close to the intermediate frequency. The exact location the output frequency f _VC o / (N ₂ * N _X ) is however known and can therefore be taken into account accordingly.

This advantageously results in an additional degree of freedom for the choice of the divisor value N ₂ , as will be explained below.

The output signal of the frequency divider 7 is also a digital signal. Since the downstream receiver works according to the limiter-discriminator principle and, for further processing of the value-discrete, time-continuous output signals of the limiter, it can also be implemented in both digital and analog design, the digital output signal of the frequency divider 7 is therefore suitable for feeding in after the limiter Input signal for this receiver.

It is noted that when processing complex-valued signals equivalent to the complex-valued limiter output signals, two output signals of the second frequency divider 7 which are phase-shifted by 90 ° are required.

Such an embodiment is possible in particular in the case of even-numbered divisor values N ₂ , which can advantageously be selected on the basis of the additional degree of freedom mentioned above.

The matching method applicable to the PLL circuit described above will be described in more detail below with reference to the flow chart of FIG. 2.

In a first step S1, the PLL circuit is preparatively set to the channel center frequency before a transmission process. Such an adjustment is necessary for operational reasons even without carrying out the adjustment procedure. An analog modulation and a digital modulation are then impressed in a second step S2, as described above.

In a third step S3, the digital modulation introduced at the first frequency divider 6 is deactivated and the amplitude of the analog modulation signal introduced at the summation point 4 is selected such that it corresponds to the set modulation stroke of the digital modulation signal, which due to its digital form has no tolerances, corresponds.

The digital modulation is thus deactivated during the adjustment process and only the analog modulation is used. Since the closed PLL control loop would regulate the analog modulation, the influence of this modulation in the transient phase must be assessed at predetermined times.

In a fourth step S4, a suitable data sequence of the analog modulation is then impressed.

In a fifth step S5, the modulation stroke generated by the analog modulation is subsequently determined at the output of the demodulator 8 of the receiver.

In a sixth step S6, the difference between the modulation stroke of the nominally set digital modulation signal and the determined modulation stroke of the impressed analog modulation signal is then determined.

Finally, in a seventh step S7, the amplitude of the impressed analog modulation signal is corrected in accordance with the difference between the nominally set digital modulation stroke and the determined analog modulation stroke. With the described method, a quantitative statement about the error occurring can thus be obtained in a simple manner and a suitable correction value can be determined by simple difference formation.

As described above, in a method for amplitude matching in transceivers for mobile radio systems with a PLL circuit in the transmitter operating on the principle of two-point modulation and a receiver operating on the limiter discriminator principle, the amplitude of an analog modulation signal selected according to a modulation stroke of a fixed digital modulation signal, a predetermined data sequence of the analog modulation signal is impressed, the modulation stroke of the analog modulation signal is determined at the output of a demodulator of the receiver, and the amplitude of the analog modulation signal in accordance with the difference between the modulation stroke of the digital modulation signal and corrected the determined modulation stroke of the analog modulation signal.

Claims

claims

1. Alignment method for a transmitter / receiver with a PLL circuit (1 to 6) operating according to the principle of two-point modulation, g e k e n n e e i c h n e t d u r c h

- Selecting the amplitude of an analog modulation signal according to the modulation stroke of a fixed digital modulation signal;

- impressing a predetermined data sequence of the analog modulation signal;

- determining the modulation stroke of the analog modulation signal at an output of the receiver (8); and

correcting the amplitude of the analog modulation signal in accordance with the difference between the modulation stroke of the digital modulation signal and the determined modulation stroke of the analog modulation signal.

2. The method of claim 1, d a d u r c h g e k e n n z e i c h n e t that - the PLL circuit (1 to 6) is set to a channel center frequency before a transmission process.

3. The method of claim 1, d a d u r c h g e k e n n z e i c h n e t that - the digital modulation signal is deactivated during the adjustment process.

4. The method of claim 1, d a d u r c h g e k e n n z e i c h n e t that - the predetermined data sequence of the analog modulation signal at a predetermined high-pass point (4) is impressed in the forward branch of the PLL circuit (1 to 6).

5. The method according to claim 1, characterized in that - The digital modulation signal is impressed at a predetermined low-pass point (6) in the feedback branch of the PLL circuit (1 to 6).

6. The method of claim 5, d a d u r c h g e k e n n z e i c h n e t that

- The digital modulation signal is impressed in a first frequency divider (6).

7. The method according to any one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that

- The output signal of the PLL circuit (1 to 6) is passed into a second frequency divider (7) lying in a signal path branching off from the feedback branch.

8. The method of claim 7, d a d u r c h g e k e n n z e i c h n e t that

- The output signal of the PLL circuit (1 to 6) in the second frequency divider (7) divided and then supplied to the receiver (8) as one of input signals.

9. The method according to any one of claims 6 to 8, d a d u r c h g e k e n n z e i c h n t that

- The divider value (N ₂ ) of the second frequency divider (7) is selected such that the output frequency of the second frequency divider (7) corresponds to the intermediate frequency of the receiver (8).

10. The method according to any one of claims 6 to 8, characterized in that - an integer value is selected as the divider value (N ₂ ) of the second frequency divider (7).

11. The method according to claim 10, dadurchgekennzeichn et that - the integer value is chosen such that the starting frequency of the second frequency divider (7) comes to lie near the intermediate frequency of the receiver (8).